JP2758844B2 - Semiconductor wafer slip line inspection method and semiconductor wafer evaluation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for inspecting a semiconductor wafer slip line, and more particularly to a method for inspecting the quality of a semiconductor wafer.
It relates to an inspection method for determining a grade.

[0002]

2. Description of the Related Art As one of inspections for judging the quality and grade of a semiconductor wafer, there is inspection of a slip line on the surface of a silicon substrate of a semiconductor wafer or on the surface of an epitaxial layer grown on the silicon substrate. Since the slip line is a crystal defect having a level shift at the atomic level, it appears on the surface as a straight line having no width and extending in a certain direction. Naturally, it is preferable that the number of existing slip lines is small. Conventionally, the state has been recognized by visual inspection by an operator using a microscope or the like. However, a visual inspection has many uncertainties and an accurate inspection cannot be expected.

In order to eliminate the uncertainty of visual inspection of a semiconductor wafer slip line, the inventor of the present invention has proposed an automatic slip line inspection method in Japanese Patent Laid-Open No. 4-42945. The outline will be described with reference to FIGS.

As shown in FIG. 13, a circularly polarized laser beam 52 emitted from a laser oscillator 51 is raster-scanned in the X direction (perpendicular to the paper) by a scanning mirror 53 controlled by an X-direction scan control unit 44. Then, the surface of the semiconductor wafer 10 is irradiated. On the other hand, a mounting table 54 on which the semiconductor wafer 10 is mounted by vacuum chucking is connected to an angle rotation variable arm 55, and the θ, γ, Y-control unit 45
Is set to a predetermined angle θ and a rotation angle γ, and is moved in the Y direction.
The entire surface of 0 is scanned and irradiated with laser. Since the slip line is determined by the crystal plane orientation and the orientation flat direction, the values of θ and γ are determined from both, so that the reflected light from the slip line can be detected as distinguished from the scattered light from foreign matter as much as possible. I have.

[0005] Light 5 reflected from the surface of the semiconductor wafer 10
6 is received by the photoelectric element 58 through the objective lens 57 and converted into a voltage, and the voltage is input to the comparator unit 42. The comparator unit 42 compares this voltage with the reference voltage from the reference voltage unit 41 and sends an information signal based on the result to the memory unit 43 for storage.

At the same time, the position information is input to the memory unit 43 from the X-direction scan control unit 44 and the θ, γ, Y-control unit 45, so that the memory unit 43 stores the state corresponding to the position coordinates of the semiconductor wafer. Is stored.

Depending on the setting of θ and γ, the reflected light 56 mainly contains data from the slip line, but also data on other surface conditions.

FIG. 14A schematically shows an example of data stored in the memory unit 43. In the semiconductor wafer 10, a slip line 11 mainly exists linearly extending in the Y direction. This shows that there are also scratches 12 shown by curves and foreign substances 13 shown by black circles.

Since the slip line is determined by the crystal plane orientation and the orientation flat direction as described above, the slip line exists linearly and with a length in a direction depending on A: plane orientation.

The slip line is not a straight line or a curve having a width because B is continuous, C is not present as a point, and D is a surface step due to slip.

Next, a slip line position coordinate output section 46
14 sent from the memory unit 43 in FIG.
From the data in the state of (A), by the logic of A to D,
The data shown in FIG. 14B is obtained by extracting only the slip line 11 by removing a flaw 12, a foreign substance 13 and the like existing as a straight line, a curve or an irregular shape having a point or a width.

Next, the data of FIG. 14B is input to the slip line measuring circuit 47, and the semiconductor chip lattice size L corresponding to the size of the semiconductor chip (product chip) shown in FIG. 14C is input. I do. That is, X direction and Y
A lattice 21 having an interval L in the direction is input, and each region 20 surrounded by the lattice 21 becomes a semiconductor chip region 20, and this lattice 21 is located at the center of a scribe region (cut region) of an actual semiconductor wafer. Can be considered.

Thus, the spacing L between the semiconductor chip lattices is
The length of one side of a regular quadrangular semiconductor chip arranged and formed on the semiconductor wafer.
In the case of 5 mm × 0.5 mm, L = 0.5 mm.

In the slip line measuring circuit 47, the coordinate data of the slip line 11 shown in FIG.
FIG. 14 is obtained by superposing the chip grid data of FIG.
The slip line map data based on the semiconductor chip lattice data shown in (D) is obtained.

FIGS. 14A to 14D are diagrammatically shown so that data can be easily understood. However, the slip line map data shown in FIG. 14D can be output from the slip line measurement circuit unit 47 as a slip line map based on the semiconductor chip lattice size by CRT display or print display.

Further, a total sum of lengths of all the slip lines in the semiconductor wafer is calculated and output from the data of FIG.

In this calculation, when the slip line 11 exists in the semiconductor chip region 20 having a square shape, the slip line having a length of 0.5 mm is counted regardless of the form in which the slip line 11 exists. On the other hand, when a slip line exists in a chip 20 that is not a regular square in the peripheral portion of the semiconductor wafer 10, it is counted as a slip line having a length of 0.25 mm. Therefore, in the semiconductor wafer, there are P semiconductor chips 20 in the form of regular squares on which the slip lines 11 exist, and Q
In this case, the sum of the lengths of the slip lines in the semiconductor wafer was calculated to be 0.5 mm × P + 0.25 mm × Q and output.

[0018]

However, according to the above-mentioned prior art, as shown in FIG. 15, even when one slip line 11 exists in the square semiconductor chip region 20 to be formed (A), the two More than one slip line 11
Both (B) and the case where the slip line 11 exists only halfway (C),
, The sum of the lengths of the slip lines in the semiconductor wafer 10 cannot be accurately calculated. Therefore, there is a problem that the evaluation of the semiconductor wafer cannot be sufficiently performed.

Conventionally, there has been no recognition of the relationship between the slip line and the yield rate (yield) of semiconductor chips. There has been a problem that the cost of the semiconductor chip cannot be predicted.

Accordingly, it is an object of the present invention to provide a semiconductor wafer slip line inspection method which enables more accurate evaluation of a semiconductor wafer by more accurately calculating the state of a slip line in the semiconductor wafer.

Another object of the present invention is to provide a semiconductor wafer evaluation method for predicting a production state of a semiconductor chip such as a non-defective product yield from a state of a slip line in a semiconductor wafer and discriminating a grade or a quality of the semiconductor wafer. It is to be.

[0022]

SUMMARY OF THE INVENTION A feature of the present invention is a method of inspecting a slip line on a main surface of a semiconductor wafer on which semiconductor chips of a predetermined size are formed and arrayed. On the slip line coordinate data of the line, slip line map data of the semiconductor wafer is obtained by superimposing fine grid data for forming a fine chip region having a size smaller than the size of the semiconductor chip. der method for calculating the sum of the lengths of slip lines in the semiconductor wafer by counting the number of said fine tip region slip lines are present
By setting the interval between the fine lattices arranged in a first direction and the interval between the fine lattices arranged in a second direction perpendicular to the first direction to the same value, the fine chip area except for the peripheral portion of the wafer is a square, the distance between the fine grid S, the number of square micro chip region where the slip line is present m, the slip line is present When the number of non-rectangular fine chip regions to be formed is n, the sum H of the lengths of the slip lines in the semiconductor wafer is H = S × m
+ (1/2) × S × n formula for semiconductor wafers
In the lip line inspection method.

Another feature of the present invention is a method of evaluating a semiconductor wafer in which semiconductor chips of a predetermined size are formed and arranged, wherein slip line coordinate data of a slip line existing on a main surface of the semiconductor wafer is added to the slip line coordinate data of the semiconductor chip. Slip line map data of a semiconductor wafer is obtained by superimposing semiconductor chip grid data for forming a semiconductor chip region having a size corresponding to the size, and counting the number (N) of the semiconductor chip regions where the slip lines exist; A semiconductor wafer evaluation method for obtaining a slip ratio by inputting the number of semiconductor chips (N ₀ ) that can be formed in the predetermined size on the semiconductor wafer and calculating N / N ₀ . Here, based on the semiconductor chip grid data obtained by superimposing fine grid data forming a fine chip area having a size smaller than that of the semiconductor chip area on the slip line map data of the semiconductor wafer based on the semiconductor chip grid data. Slip line map data is obtained, and using the slip line map data, the number (N _P ) of semiconductor chip regions in which the number of slip lines is large among the N semiconductor chip regions in which the slip lines are present is classified. It is preferable to calculate a plurality of types of the slip ratios. In this case, a plurality of slip lines are present in each of the N _P semiconductor chip regions where many slip lines are present, and the sum of the lengths of the plurality of slip lines in the semiconductor chip region is a semiconductor. It can be at least twice the length of one side of the chip.

[0024]

As described above, according to the present invention, the sum of the lengths of a plurality of slip lines in a semiconductor wafer is calculated using fine grid data for forming a fine chip area smaller than the size of a semiconductor chip. The wafer grade can be accurately evaluated.

In the present invention, since the slip ratio is calculated, and the slip ratio is calculated from various viewpoints by classifying the slip lines present in the respective semiconductor chip regions according to the degree thereof, the yield of non-defective semiconductor chips can be improved. You can actually make predictions.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

The method for inspecting a semiconductor wafer slip line and the method for evaluating a semiconductor wafer according to the present invention are shown in FIG.
And a processing method in a functional circuit unit corresponding to the slip line measuring circuit unit 47 of the inspection apparatus.

FIGS. 1 to 3 are flowcharts showing a first embodiment of the present invention.

First, each step of FIG. 1 will be described with reference to FIGS. 13 and 7. Step 110 of irradiating the surface of the semiconductor wafer 10 with a laser beam 52, a slip line 11, a scratch 12, 13, the X-direction scan control unit 44 and θ, γ,
Step 1 of inputting the position data from the Y-control unit 45 to the memory unit 43 and storing the data (FIG. 7A) of the wafer map of the semiconductor wafer 10 in the memory unit 43
20, the slip line position coordinate output circuit 46
The wafer map data (slip line coordinate data) from which the scratches were removed to extract the slip line 11 (FIG. 7)
(B)) is obtained, which is the same as in the prior art.

In the present invention, in step 140 of FIG. 2, fine grid data S (inter-fine grid spacing S) for slip line length measurement is input to a functional circuit section corresponding to the slip line measuring circuit section 47 of FIG. I do.

The fine lattice data S is finer than the semiconductor chip lattice data L (semiconductor chip lattice spacing L) surrounding the semiconductor chip region having the same dimensions as the semiconductor chips arranged and formed. For example, the dimension L between the semiconductor chip lattices
Is 0.5 mm, the dimension S between the fine lattices is 0.1 mm
It is. FIG. 7 (C) shows that the fine gratings 31 are arranged at intervals of S = 0.1 mm in the Y direction and the X direction, respectively, and are 0.1 mm × 0.1 mm formed by being surrounded by the fine gratings 31.
1 schematically shows a data map of a fine lattice in which the fine chip regions 30 are arranged in a matrix.

Next, in step 150 of FIG.
The microgrid data of FIG. 7C is superimposed on the slip line coordinate data of FIG. 7B to create a slip map of the semiconductor wafer by the fine lattice. FIG. 7D illustrates this state.

FIGS. 7 (A) to 7 (D) are diagrammatically shown for easy understanding of data, as in FIG.

If necessary, the slip line map data shown in FIG. 7D is output from the slip line measuring circuit 47 or a functional circuit unit corresponding thereto as a slip line map based on the semiconductor chip lattice size by CRT display or print display. can do.

Further, in step 150 of FIG. 2, the number m of the square regions (the number in the entire region of the semiconductor wafer 10) which is the fine chip region 30 with the slip line 11 and the slip line 11 and the fine grid 31 , The number of regions (the number in the entire region of the semiconductor wafer 10) n which are not formed into a regular square because the slip line 11 exists and is located at the periphery of the semiconductor wafer 10 Count and sum H of the lengths of all slip lines in the semiconductor wafer
Is calculated from the equation H = S × m + (１ ／) × S × n.
As described above, when S = 0.1 mm, H (mm) =
0.1 × m + 0.05 × n. This calculation result is shown in FIG.
In step 180, the output is output from the functional circuit unit.

In the prior art shown in FIG. 14, in the case of (A) where one slip line 11 exists in the semiconductor chip region 20 of 0.5 mm × 0.5 mm surrounded by the semiconductor chip lattice 21, 2 In both the case where there are two slip lines 11 (B) and the case where only half of the slip lines 11 exist (C), the semiconductor chip region 2
Since the total slip line length of the entire semiconductor wafer was calculated assuming that the total length of the slip line at 0 was 0.5 mm, the error from the actual state became large, and the semiconductor wafer could not be evaluated correctly.

On the other hand, according to the present embodiment, as shown in FIG. 9, each fine chip area 3 of 0.1 mm × 0.1 mm based on the size S (0.1 mm) of the fine grid 31.
Since the slip line length is calculated based on whether or not the slip line 11 exists at 0, in the case of (A) where one slip line 11 penetrating in the Y direction exists in the semiconductor chip region 20, the semiconductor chip region 20 Is 0.1 mm × 5 = 0.5 mm, and there are two slip lines 11 penetrating in the Y direction (B).
In the case of (1), the slip line length in the semiconductor chip region 20 is 0.1 mm × 10 = 1.0 mm. In the case of (C) in which only half of the slip line 11 exists, the slip line length in the semiconductor chip region 20 Is 0.1mm ×
Assuming that 3 = 0.3 mm, the total length of the slip line of the entire semiconductor wafer is calculated, so that the semiconductor wafer can be correctly evaluated according to the actual state.

The sum H of the lengths of the slip lines of the semiconductor wafer calculated in step 150 is directly used in step 180 of FIG. 3 in the slip line measuring circuit 47 (FIG. 1).
3) Alternatively, it can be output from a functional circuit unit corresponding thereto by CRT display or print display.

In this embodiment, the subsequent step 160
Input the dimension data L (FIG. 8A) of the semiconductor chip lattice 21 according to the dimensions of the semiconductor chip (product chip), and superimpose the wafer map data of the semiconductor chip lattice 21 on the slip line data in step 170. Slip line map data based on the semiconductor chip lattice data is created (FIG. 8B), and in step 180, this slip line map data is output as a slip line map based on the semiconductor chip lattice size by CRT display or print display. This step 160,
170 itself is the same as the prior art.

FIGS. 4 to 6 are flow charts showing a second embodiment of the present invention.

After step 130 in FIG. 1, in step 240 in FIG. 4, semiconductor chip lattice data L, for example, L =
Enter 0.5 mm. Further, fine grid data S, for example, S = 0.1 mm is input.

In the next step 250, a wafer map of the slip line (slip line coordinate data)
Then, the semiconductor chip lattice data and the fine lattice data are superimposed to create slip line map data of the semiconductor wafer.

A part of this data is shown schematically in FIG. In FIG. 10, the semiconductor chip lattice 21 shown by a solid line
L × L (0.5 mm × 0.5 mm) semiconductor chip region 20 is formed, and S × S (0.1 mm × 0.1 mm) surrounded by a fine grid 31 indicated by a dotted line.
Is formed, and the slip line 11 is formed.
It is shown.

Next, in step 260 of FIG. 5, the state of the slip line 11 in each semiconductor chip area 20 is calculated.

First, the number N of the semiconductor chip regions 20 in the square semiconductor chip grid 21 where the slip lines 11 exist is counted.

Next, among the above N pieces, the slip line 11
There many (the total length longer) counts the number N _P of the semiconductor chip regions 20 are present. The length of the slip line 11 in each semiconductor chip region 20 is calculated by calculating the slip line 11 in each of a plurality of (5 × 5 = 25 in this embodiment) fine chip regions 30 in each semiconductor chip region. This is performed by determining the presence or absence of the presence.

For example, there are a plurality of slip lines 11 in the semiconductor chip region 20 and the total length of the plurality of slip lines 11 (the total length in the semiconductor chip region) is The number N _P of semiconductor chip regions 20 that are twice (1.0 mm) or more than the length L (0.5 mm) of one side is counted assuming that many slip lines exist.

Then, in step 270, 0.5 mm × 0.5 mm which can be formed on this semiconductor wafer
The number (N ₀ ) of semiconductor chips having a size of mm is input.

In the example of FIG. 11, the number N of the semiconductor chip regions (E + F) in which the slip lines 11 are present in the square semiconductor chip region 20 is 6 (2 + 4). The number N _P of the semiconductor chip regions (E) in which many 11 are present is two, and the number of semiconductor chip regions G in which the slip lines 11 are not present is 22 and can be formed in a regular square on the semiconductor wafer. The number of possible semiconductor chips N ₀ is 28 (6 + 2)
2).

Next, in step 280 of FIG.
And the second slip ratio are calculated.

The first slip ratio is given by the formula (N / N ₀ ) × 1
It is calculated by 00%, and shows the ratio of the semiconductor chip area where the slip line exists regardless of the length (total length in the semiconductor chip area).

The second slip ratio is calculated by the formula (N _P / N ₀ ) ×
The ratio is calculated based on 100%, and indicates the ratio of only the semiconductor chip region where the length (the total length in the semiconductor chip region) is long, that is, where many slip lines exist.

Next, at step 290, the first and second slip ratios are measured by the slip line measuring circuit 47 (FIG. 1).
3) or output from a functional circuit unit corresponding thereto by CRT display or print display.

FIG. 12 is a diagram showing an example of a relationship line 60 between the slip rate and the yield (yield rate or non-defective rate) of the product (semiconductor chip).

The relationship line 60 differs for each product type.
In the case of 2, a semiconductor device (semiconductor chip) of a kind corresponding to the relation line is placed on a semiconductor wafer having a slip rate of substantially zero.
The yield (non-defective product rate or yield rate) in the case of forming
%, But the same type has a slip rate of 15%
Can be estimated to be 70% when formed on a semiconductor wafer, thereby making it easy to predict the production situation and production cost, and to enhance production management.

Here, whether to use the first slip ratio or the second slip ratio as the slip ratio is determined depending on the product type.

For example, in a highly integrated memory device, most of the silicon substrate of a semiconductor chip is used as an element region (active region). Therefore, even if a slip line exists even a little, there is a high probability of failure. In such a kind, the relationship line 60 that matches the actual result is obtained by using the first slip rate as the slip rate on the horizontal axis in FIG.

On the other hand, in a semiconductor chip on which discrete transistors and the like are formed, only a small portion at the center of the silicon substrate is used as an element region (active region), and a bonding pad is provided on most of the periphery. Since it is a field area, even if a small amount of a slip line exists, the probability that it is located in the element area and becomes defective is small.
In this case, using the second slip ratio, which counts only the semiconductor wafer region where many slip lines exist, results in the relationship line 60 that matches the actual results.

It is preferable that the sum H of the lengths of the slip lines in the semiconductor wafer is small because the slip ratio is small.
Therefore, it is necessary to accurately measure the sum H of the lengths of the slip lines, grade the semiconductor wafers or lots thereof, and manage the quality of the semiconductor wafers or lots.

However, even when the sum H of the lengths of the slip lines is small, when most of the existing slip lines are located across the center of the semiconductor wafer, the slip ratio becomes large and the yield is low. descend. Therefore, it is necessary to properly grasp the slip ratio of each semiconductor wafer.

In the present invention, the use of a fine grid allows accurate macro-management by precise measurement of the sum H of the lengths of the slip lines, and the use of the fine grid allows the calculation of the slip rate appropriate for each product type. Therefore, it is possible to perform production management according to the current situation by using both of them.

In the above embodiment, the semiconductor chip area 20
That is, the case where the semiconductor chip is a square of 0.5 mm × 0.5 mm is illustrated. However, it goes without saying that the present invention can be applied to a rectangular semiconductor chip, for example, a semiconductor chip of 0.5 mm × 1.0 mm.

On the other hand, in the above embodiment, the case where the fine chip area 30 by the fine grid 31 is 0.1 mm × 0.1 mm has been exemplified. However, depending on the required accuracy, for example, a fine chip area of 0.05 mm × 0.05 mm (S = 0.05) or a 0.2 mm × 0.2 mm (S = 0.2)
It is possible to change to a fine chip area of It is preferable that the fine chip area is square because the input of the fine lattice data S can be commonly input to the X axis and the Y axis.

[0064]

As described above, according to the present invention, the sum of the lengths of a plurality of slip lines in a semiconductor wafer is obtained by using fine grid data for forming a fine chip area smaller than the size of a semiconductor chip. Is calculated, the value can be calculated precisely, thereby enabling accurate evaluation of the semiconductor wafer.

In the present invention, since the slip ratio is calculated, and the slip ratio is calculated from various viewpoints by classifying the slip lines existing in each semiconductor chip according to the degree thereof, the semiconductor wafer is used. In this case, it is possible to appropriately predict the production status of each product type and the yield of non-defective products.

[Brief description of the drawings]

FIG. 1 is a diagram sequentially illustrating steps in an embodiment of the present invention.

FIG. 2 is a continuation of FIG. 1, showing the first embodiment of the present invention in the order of steps.

FIG. 3 is a diagram sequentially illustrating steps subsequent to FIG. 2;

FIG. 4 is a continuation of FIG. 1, showing the second embodiment of the present invention in the order of steps.

FIG. 5 is a diagram sequentially illustrating steps subsequent to FIG. 4;

FIG. 6 is a diagram sequentially illustrating steps subsequent to FIG. 5;

FIG. 7 is a diagram illustrating a slip line and a fine grid in the first embodiment of the present invention.

FIG. 8 is a diagram illustrating a slip line and a semiconductor chip lattice according to the first embodiment of the present invention.

FIG. 9 is a view for explaining a method of inspecting a slip line in a semiconductor chip region and a fine grid in the first embodiment of the present invention.

FIG. 10 is a diagram illustrating a slip line, a semiconductor chip grating, and a fine grating according to a second embodiment of the present invention.

FIG. 11 is a diagram showing a relationship between a slip line in a semiconductor wafer and a semiconductor chip according to a second embodiment of the present invention.

FIG. 12 is a diagram showing a relationship between a slip ratio and a product yield in the second embodiment of the present invention.

FIG. 13 is a diagram showing a slip line measuring device used in an embodiment of the present invention and a conventional technique.

FIG. 14 is a diagram illustrating a slip line and a semiconductor chip grating in a conventional technique.

FIG. 15 is a diagram for explaining a method of inspecting a slip line in a semiconductor chip region in the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Semiconductor wafer 11 Slip line 12 Scratches 13 Black circle 20 Semiconductor chip area 21 Semiconductor chip lattice 30 Micro chip area 31 Micro lattice 41 Reference voltage section 42 Comparator section 43 Memory section 44 X direction scan control section 45 θ, γ, Y-control section 46 Slip line position coordinate output circuit unit 47 Slip line measurement circuit unit 51 Laser oscillator 52 Circularly deflected laser beam 53 Scanning mirror 54 Mounting table 55 Angle rotation variable arm 56 Reflected light 57 Objective lens 58 Photoelectric element 60 Product collection for slip ratio Line showing rate 110-180, 240-290 Each step

Claims (4)

(57) [Claims] 1. A method of inspecting a slip line on a main surface of a semiconductor wafer on which semiconductor chips of a predetermined size are arranged and formed, the slip line coordinate data of a slip line present on the main surface of the semiconductor wafer is added to the semiconductor device. Slip line map data of the semiconductor wafer is obtained by superimposing fine lattice data for forming a fine chip region having a size smaller than the size of a chip, and in the slip line map data, A method of calculating the sum of the lengths of the slip lines in the semiconductor wafer by counting the number thereof, wherein the array is arranged in a first direction.
A second direction perpendicular to the distance between the fine lattices and the first direction;
The spacing between the fine grids arranged in
With the exception of the peripheral portion of the semiconductor wafer,
The thin chip area is a regular square, and
Is S, the square of the square where the slip line exists
The number of fine chip areas is m and the slip line exists
Where n is the number of non-rectangular fine chip regions
In the case, the length of the slip line in the semiconductor wafer
A method for inspecting a slip line of a semiconductor wafer, wherein a total sum H is calculated by an equation of H = S × m + (１ ／) × S × n . 2. A semiconductor wafer evaluation method in which semiconductor chips of a predetermined size are arranged and formed, wherein a slip line coordinate data of a slip line existing on a main surface of the semiconductor wafer is provided with a size corresponding to the size of the semiconductor chip. Slip line map data of the semiconductor wafer is obtained by superimposing the semiconductor chip lattice data forming the semiconductor chip area of the semiconductor chip area, the number (N) of the semiconductor chip areas where the slip lines are present is counted, and enter the number of semiconductor chips (N _O) which can be formed at a predetermined size, method for evaluating a semiconductor wafer, comprising obtaining a slip ratio by calculating the N / N _O. 3. A fine chip and a semiconductor chip grid in which fine grid data for forming a fine chip area smaller than the size of the semiconductor chip area are superimposed on slip line map data of a semiconductor wafer based on the semiconductor chip grid data. The slip line map data based on the data is obtained, and by using the slip line map data, the number (N _P ) of the semiconductor chip regions where the slip lines are present among the N semiconductor chip regions where the slip lines are present 3. The method for evaluating a semiconductor wafer according to claim 2 , wherein a plurality of types of the slip ratios are calculated by classifying and counting the slip ratios. Wherein said slip lines there are many N _P
A plurality of slip lines exist in each of the semiconductor chip regions, and the sum of the lengths of the plurality of slip lines in the semiconductor chip region is at least twice the length of one side of the semiconductor chip. The method for evaluating a semiconductor wafer according to claim 3, wherein: