JPH05291494A - Integrated circuit device - Google Patents

Integrated circuit device

Info

Publication number
JPH05291494A
JPH05291494A JP11533092A JP11533092A JPH05291494A JP H05291494 A JPH05291494 A JP H05291494A JP 11533092 A JP11533092 A JP 11533092A JP 11533092 A JP11533092 A JP 11533092A JP H05291494 A JPH05291494 A JP H05291494A
Authority
JP
Japan
Prior art keywords
integrated circuit
bypass capacitor
package
power supply
supply noise
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11533092A
Other languages
Japanese (ja)
Inventor
Akira Mizuno
昭 水野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Ibaraki Ltd
Original Assignee
NEC Ibaraki Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Ibaraki Ltd filed Critical NEC Ibaraki Ltd
Priority to JP11533092A priority Critical patent/JPH05291494A/en
Publication of JPH05291494A publication Critical patent/JPH05291494A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PURPOSE:To reduce the number of parts and hence ensure high density packaging of a printed board by constructing a power supply noise removal bypass capacitor integrally with an integrated circuit package. CONSTITUTION:A bypass capacitor 2 is formed integrally with a package 1. Lead terminals 3-1-3-8 are inserted into corresponding through-holes 5 provided in a through-hole substrate 4, and are electrically interconnected through soldering. Hereby, the bypass capacitor 2 absorbs any power supply noise, and hence an integrated circuit is supplied with stable power for its normal operation. Accordingly, there is eliminated the need of an independent power supply noise prevention bypass capacitor to reduce the number of parts and the number of processes of assembling for improvement of reliability.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【技術分野】本発明は集積回路装置に関し、特に電源ノ
イズ除去用のバイパスコンデンサが必要な集積回路装置
の構造に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device, and more particularly to the structure of an integrated circuit device requiring a bypass capacitor for removing power source noise.

【0002】[0002]

【従来技術】電源ノイズにより集積回路装置の論理回路
部分が誤動作するのを防止するために、電源ラインとグ
ランドラインとの間にバイパスコンデンサを挿入するこ
とが広く実施されている。
2. Description of the Related Art It is widely practiced to insert a bypass capacitor between a power supply line and a ground line in order to prevent a logic circuit portion of an integrated circuit device from malfunctioning due to power supply noise.

【0003】図4に、集積回路装置1とバイパスコンデ
ンサ2とをプリント基板4に実装する場合の斜視図を示
す。また、図5にはその等価回路を示しており、これ等
図に示す如く、集積回路装置1とその電源入力端子との
間にバイパスコンデンサ2を接続しており、部品実装上
は、集積回路装置1とバイパスコンデンサ2との間には
ある距離を取っている。
FIG. 4 shows a perspective view of the integrated circuit device 1 and the bypass capacitor 2 mounted on the printed circuit board 4. Further, FIG. 5 shows an equivalent circuit thereof. As shown in these drawings, a bypass capacitor 2 is connected between the integrated circuit device 1 and its power input terminal. There is a distance between the device 1 and the bypass capacitor 2.

【0004】尚、図において、3はリード端子を示し、
5は基板4に設けられたスルーホールである。
In the figure, 3 indicates a lead terminal,
Reference numeral 5 is a through hole provided in the substrate 4.

【0005】この様に、従来の技術においては、集積回
路とは別個に電源ノイズ防止用のバイパスコンデンサを
使用しているので、高密度実装の妨げになると共に、実
装部品点数が多くなるので、組立工数がそれだけ増加
し、人間が目視にて検査を行う場合にも、ミスを犯す可
能性が高くなって信頼性の点でも問題がある。
As described above, in the conventional technique, since the bypass capacitor for preventing the power supply noise is used separately from the integrated circuit, it hinders high-density mounting and increases the number of mounting parts. The number of assembling steps increases, and even when a human visually inspects, there is a high possibility of making mistakes, and there is a problem in reliability.

【0006】[0006]

【発明の目的】そこで、本発明はかかる従来技術の欠点
を解決すべくなされたものであって、その目的とすると
ころは、部品点数の削減を図って組立工数の減少及び信
頼性の向上を可能とした集積回路装置を提供することに
ある。
SUMMARY OF THE INVENTION Therefore, the present invention has been made to solve the above-mentioned drawbacks of the prior art. The object of the present invention is to reduce the number of parts to reduce the number of assembling steps and improve the reliability. An object is to provide an integrated circuit device that enables it.

【0007】[0007]

【発明の構成】本発明による集積回路装置は、電源ノイ
ズ除去用のバイパスコンデンサをパッケージと一体構成
した構造となっている。
The integrated circuit device according to the present invention has a structure in which a bypass capacitor for removing power supply noise is integrated with the package.

【0008】[0008]

【実施例】以下、図面を用いて本発明の実施例を説明す
る。
Embodiments of the present invention will be described below with reference to the drawings.

【0009】図1は本発明の実施例の斜視図であり、図
4と同等部分は同一符号にて示している。本例では、ス
ルーホール基板4に装着可能な構造の集積回路パッケー
ジ1を有し、このパッケージ1と一体的にバイパスコン
デンサ2が形成されている。尚、このパッケージ1は8
本のリード端子3−1〜3−8を有しているものとす
る。
FIG. 1 is a perspective view of an embodiment of the present invention, and the same portions as those in FIG. 4 are designated by the same reference numerals. In this example, an integrated circuit package 1 having a structure attachable to a through hole substrate 4 is provided, and a bypass capacitor 2 is formed integrally with the package 1. In addition, this package 1 is 8
It is assumed that the book has lead terminals 3-1 to 3-8.

【0010】図2は図1の等価回路図であり、電源に接
続されているリード線は、リード端子3−4を通じパッ
ケージ内部で2方向に分岐する。その一端は集積回路へ
通じ、他端はバイパスコンデンサ2のA極へと通じてい
る。また、グランド(GND)に接続されているリード
線は、リード端子3−8を通じパッケージ内で2方向に
分岐する。その一端は集積回路へ、他端はバイパスコン
デンサ2のB極へと夫々通じている。
FIG. 2 is an equivalent circuit diagram of FIG. 1. The lead wire connected to the power supply is branched into two directions inside the package through the lead terminal 3-4. One end thereof leads to the integrated circuit, and the other end thereof leads to the A pole of the bypass capacitor 2. The lead wire connected to the ground (GND) branches in two directions in the package through the lead terminal 3-8. One end thereof communicates with the integrated circuit and the other end communicates with the B pole of the bypass capacitor 2.

【0011】図1を参照すると、リード端子3−1〜3
−8はスルーホール基板4に設けられているスルーホー
ル5に夫々対応して挿入され、半田付けされることによ
り電気的接続が行われるようになっている。これによ
り、バイパスコンデンサ2は電源からのノイズを吸収
し、集積回路へ安定な電源が供給され正常動作が可能と
なるのである。
Referring to FIG. 1, lead terminals 3-1 to 3-3
-8 are inserted correspondingly to the through holes 5 provided in the through hole substrate 4 and soldered so that electrical connection is made. As a result, the bypass capacitor 2 absorbs the noise from the power source, the stable power source is supplied to the integrated circuit, and the normal operation becomes possible.

【0012】図3は本発明の他の実施例の斜視図であ
り、図1と同等部分は同一符号により示している。本例
においても、集積回路パッケージ1とバイパスコンデン
サ2とは一体形成されており、8本のリード端子3−1
〜3−8を有している。この場合の等価回路も図2と同
一となる。
FIG. 3 is a perspective view of another embodiment of the present invention, and the same portions as those in FIG. 1 are designated by the same reference numerals. Also in this example, the integrated circuit package 1 and the bypass capacitor 2 are integrally formed, and eight lead terminals 3-1 are provided.
~ 3-8. The equivalent circuit in this case is also the same as in FIG.

【0013】すなわち、電源に接続されているリード線
はリード端子3−4を通じパッケージ内部で2方向に分
岐する。その一端は集積回路へ通じ、他端はバイパスコ
ンデンサ2のA極へと通じている。また、グランドに接
続されているリード線はリード端子3−8を通じパッケ
ージ内部で2方向に分岐し、その一端は集積回路へ、他
端はバイパスコンデンサ2のB極へと夫々通じている。
That is, the lead wire connected to the power supply is branched into two directions inside the package through the lead terminal 3-4. One end thereof leads to the integrated circuit, and the other end thereof leads to the A pole of the bypass capacitor 2. The lead wire connected to the ground branches into two directions inside the package through the lead terminal 3-8, one end of which leads to the integrated circuit and the other end of which leads to the B pole of the bypass capacitor 2.

【0014】図3を参照すると、リード端子3−1〜3
−8は表面実装基板7に設けられたパッド6に夫々搭載
されて半田付けされ、電気的に接続される。これによ
り、バイパスコンデンサ2は電源からのノイズを吸収し
て集積回路へ安定な電源を供給して回路を正常に動作さ
せることが可能となるのである。
Referring to FIG. 3, lead terminals 3-1 to 3-3
-8 is mounted on each of the pads 6 provided on the surface mount board 7, soldered, and electrically connected. As a result, the bypass capacitor 2 can absorb noise from the power source and supply a stable power source to the integrated circuit to operate the circuit normally.

【0015】尚、集積回路パッケージ1の下面にバイパ
スコンデンサ2を密着させる構造を示しているが、パッ
ケージ内にこのコンデンサ2を内蔵する様に構成しても
良く、要はパッケージ1とコンデンサ2とが構造上一体
になる様にすれば良いものである。
Although a structure is shown in which the bypass capacitor 2 is closely attached to the lower surface of the integrated circuit package 1, the bypass capacitor 2 may be built in the package. It is good if they are integrated in structure.

【0016】[0016]

【発明の効果】叙上の如く、本発明によれば、電源ノイ
ズ除去用のバイパスコンデンサを集積回路パッケージと
一体的に構成したので、部品点数が削減され、プリント
基板の高密度実装が可能となると共に、組立工数の削減
につながって、信頼性の向上が図れるという効果があ
る。
As described above, according to the present invention, since the bypass capacitor for removing the power supply noise is formed integrally with the integrated circuit package, the number of parts is reduced and the high density mounting of the printed circuit board becomes possible. In addition, there is an effect that the number of assembling steps can be reduced and the reliability can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示す斜視図である。FIG. 1 is a perspective view showing an embodiment of the present invention.

【図2】本発明の実施例の等価回路図である。FIG. 2 is an equivalent circuit diagram of an embodiment of the present invention.

【図3】本発明の他の実施例を示す斜視図である。FIG. 3 is a perspective view showing another embodiment of the present invention.

【図4】従来の集積回路装置の実装状態を示す斜視図で
ある。
FIG. 4 is a perspective view showing a mounted state of a conventional integrated circuit device.

【図5】図4の装置の等価回路を示す図である。5 is a diagram showing an equivalent circuit of the device of FIG.

【符号の説明】[Explanation of symbols]

1 集積回路パッケージ 2 バイパスコンデンサ 3−1〜3−8 リード端子 4 プリント基板 5 スルーホール 6 パッド 1 Integrated Circuit Package 2 Bypass Capacitor 3-1 to 3-8 Lead Terminal 4 Printed Circuit Board 5 Through Hole 6 Pad

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 電源ノイズ除去用のバイパスコンデンサ
をパッケージと一体形成したことを特徴とする集積回路
装置。
1. An integrated circuit device in which a bypass capacitor for removing power supply noise is formed integrally with a package.
【請求項2】 前記パッケージはスルーホール基板に装
着可能な構造であることを特徴とする請求項1記載の集
積回路装置。
2. The integrated circuit device according to claim 1, wherein the package has a structure mountable on a through-hole substrate.
【請求項3】 前記パッケージは表面実装基板に装着可
能な構造であることを特徴とする請求項1記載の集積回
路装置。
3. The integrated circuit device according to claim 1, wherein the package has a structure mountable on a surface mount substrate.
JP11533092A 1992-04-08 1992-04-08 Integrated circuit device Pending JPH05291494A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11533092A JPH05291494A (en) 1992-04-08 1992-04-08 Integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11533092A JPH05291494A (en) 1992-04-08 1992-04-08 Integrated circuit device

Publications (1)

Publication Number Publication Date
JPH05291494A true JPH05291494A (en) 1993-11-05

Family

ID=14659895

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11533092A Pending JPH05291494A (en) 1992-04-08 1992-04-08 Integrated circuit device

Country Status (1)

Country Link
JP (1) JPH05291494A (en)

Similar Documents

Publication Publication Date Title
US5343075A (en) Composite stacked semiconductor device with contact plates
US5387814A (en) Integrated circuit with supports for mounting an electrical component
JPH05102648A (en) Printed board
JPS616846A (en) Plug-in package with capacitor
JPH05291494A (en) Integrated circuit device
JPH05259599A (en) Printed wiring board
JP2715945B2 (en) Mounting structure of ball grid array package
JP2788899B2 (en) Integrated circuits for surface mounting
JP2646710B2 (en) SOP type SMD double-sided printed board
JP2819775B2 (en) Hybrid integrated circuit device
JPH09190923A (en) Printed inductor
JP2000195586A (en) Circuit board for card connector
JPH06314885A (en) Multilayer printed wiring board module
JPH05218218A (en) Electronic component package and mounting thereof
JPH0745977Y2 (en) Board connection structure
JP2704076B2 (en) Integrated circuit package
JPS62208691A (en) Double-sided mounting hybrid integrated circuit
JPH034471A (en) Ic socket to which electronic parts can be mounted
JPS60218864A (en) Mounting method of electronic-parts package and structure of electronic-parts package
JPH0582947A (en) Printed board
JPH08195540A (en) Electric circuit device
JPH11260959A (en) Semiconductor package
JPS62243393A (en) Printed board
JPH0473992A (en) Hybrid circuit device
JPH06325966A (en) Two-terminal chip component