JPH05291299A - Formation of metallic electrode - Google Patents

Formation of metallic electrode

Info

Publication number
JPH05291299A
JPH05291299A JP9257892A JP9257892A JPH05291299A JP H05291299 A JPH05291299 A JP H05291299A JP 9257892 A JP9257892 A JP 9257892A JP 9257892 A JP9257892 A JP 9257892A JP H05291299 A JPH05291299 A JP H05291299A
Authority
JP
Japan
Prior art keywords
compound semiconductor
layer
protective film
metal
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9257892A
Other languages
Japanese (ja)
Inventor
Katsuhiko Mitani
克彦 三谷
Yoshinori Imamura
慶憲 今村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9257892A priority Critical patent/JPH05291299A/en
Publication of JPH05291299A publication Critical patent/JPH05291299A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To provide a technique to form fine metallic films with good controllability on a compound semiconductor layer such as GaAs or the like. CONSTITUTION:After a protection film 102 of single atom layer level mainly consisting of S is formed on a GaAs layer 101, a part of the protection film 102 is selectively removed by irradiation of a focused energy beam, for example, an ion beam 103 to leave the protection film 102 only in the desired fine region. Next, a W film 104 is deposited only on the protection film 102 of the fine region by application of selective CVD technique of a metal, for example, W. Thereby, controllability within a fine region such as a line width of an energy beam, for example, ion beam 103 focused on the GaAs layer 101.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は化合物半導体素子におけ
る金属電極の形成方法に係り、特に、化合物半導体表面
に微細な金属電極を形成する方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal electrode in a compound semiconductor device, and more particularly to a method for forming a fine metal electrode on the surface of a compound semiconductor.

【0002】[0002]

【従来の技術】GaAsを主とする化合物半導体はSi
に比べ電子移動度が大きく、超高速デバイスへの応用が
検討されている。GaAs高速デバイスの中で、例え
ば、電界効果型トランジスタ(MESFET)の高速,高
性能化を図るためには、Siデバイスと同様に素子の微
細化による寄生成分の低減が有効である。特にゲート長
を0.1μm 前後に短縮することにより、電子のバリス
ティック伝導の可能性が生じるため素子の大幅な高性能
化が図れる。GaAsMESFETのゲート電極には耐
熱性の優れたW或いはWSi金属が用いられることが多
い。W或いはWSi金属の微細加工には、例えば、ドラ
イ プロセス シンポジウム(1984),II−2,p
p25−30において記載されているように、CF4
SF6,NF3等のガスを用いたドライエッチングが検討
されている。
2. Description of the Related Art Compound semiconductors mainly composed of GaAs are Si
Electron mobility is higher than that of, and its application to ultra-high speed devices is being investigated. Among GaAs high-speed devices, for example, in order to achieve high speed and high performance of a field effect transistor (MESFET), it is effective to reduce parasitic components by miniaturizing the elements as in the Si device. In particular, by shortening the gate length to around 0.1 μm, there is a possibility of ballistic conduction of electrons, so that the device can be significantly improved in performance. In most cases, W or WSi metal having excellent heat resistance is used for the gate electrode of GaAs MESFET. For fine processing of W or WSi metal, for example, Dry Process Symposium (1984), II-2, p.
as described in p25-30, CF 4 ,
Dry etching using a gas such as SF 6 or NF 3 is being studied.

【0003】[0003]

【発明が解決しようとする課題】上述したCF4,S
6,NF3 等のガスによるドライエッチング技術では
レジストと充分な選択比がとれず加工断面形状及びゲー
ト長の制御が困難であり、0.3μm 以下の微細なゲー
ト電極を精度良く形成することが不可能である。また、
レジストマスクを通常の光リソグラフィ技術によりパタ
ーニングしているため0.3μm 以下の微細加工が困難
である。
[SUMMARY OF THE INVENTION] CF 4 described above, S
With a dry etching technique using a gas such as F 6 or NF 3 , it is difficult to control the processed cross-sectional shape and the gate length because a sufficient selection ratio cannot be obtained with the resist. Is impossible. Also,
Since the resist mask is patterned by the usual photolithography technique, it is difficult to perform fine processing of 0.3 μm or less.

【0004】[0004]

【課題を解決するための手段】ゲート電極を形成する化
合物半導体層表面の酸化膜を除去した後、S,Se等を
含む極薄層保護膜を前記化合物半導体表面上に形成す
る。次に、エネルギ線の照射により、ゲート電極を形成
する微細な領域を除いて前記S,Se等を含む極薄層保
護膜を除去する。次いで、前記S,Se等を含む極薄層
保護膜を有するゲート電極形成領域の化合物半導体層上
に選択的に金属を被着する。
The oxide film on the surface of a compound semiconductor layer forming a gate electrode is removed, and then an ultrathin protective film containing S, Se and the like is formed on the compound semiconductor surface. Next, the ultrathin layer protective film containing S, Se and the like is removed except for the fine region where the gate electrode is formed by irradiation with energy rays. Then, a metal is selectively deposited on the compound semiconductor layer in the gate electrode formation region having the ultrathin layer protective film containing S, Se or the like.

【0005】[0005]

【作用】化合物半導体表面に形成した極薄層のS,Se
等を含む保護膜の所望領域を集束したエネルギ線の照射
により除去することにより、収束したエネルギ線のビー
ム径のオーダ(電子線の場合数nm以下)の微細な領域
の保護膜を化合物表面に残すことができる。S,Se等
を含む保護膜を有する化合物半導体表面ではフェルミ準
位のピンニングが解け、吸着分子との間で電荷移動が起
こり、CVDによる金属被着が可能である。
[Function] An ultrathin layer of S and Se formed on the surface of the compound semiconductor
By removing the desired area of the protective film including the like by irradiation with focused energy rays, a protective film in a fine area of the beam diameter of the converged energy ray (several nm or less in the case of electron beam) is formed on the compound surface. You can leave. On the surface of the compound semiconductor having a protective film containing S, Se, etc., Fermi level pinning is released, charge transfer occurs with adsorbed molecules, and metal deposition by CVD is possible.

【0006】[0006]

【実施例】【Example】

<実施例1>本発明の一実施例を図1に示す工程図を用
いて説明する。半絶縁性基板100に形成したn型Ga
As層101を過飽和の硫化アンモニウム溶液に浸漬し
た後、減圧雰囲気で加熱処理(250〜500℃)によ
り、n型GaAs層101の表面にSを主とする単原子
層レベルの保護膜102を形成した(図1(a))。次に
試料の所望領域に集束イオンビーム103(Siイオ
ン,加速電圧50kV)を走査させることにより、保護
膜102を選択的に除去した(図1(b))。次いで、選
択W−CVD技術を試料に適用して、n型GaAs層1
01上にパターニングされた保護膜102上に選択的に
W膜104の被着を行った(図1(c))。このときの選
択W−CVD条件は、ガス流量WF6 :2sccm,SiH
4:1sccm,全ガス圧0.12torr,基板温度320℃で
ある。
<Embodiment 1> An embodiment of the present invention will be described with reference to the process chart shown in FIG. N-type Ga formed on the semi-insulating substrate 100
After the As layer 101 is immersed in a supersaturated ammonium sulfide solution, heat treatment (250 to 500 ° C.) is performed in a reduced pressure atmosphere to form a monatomic layer-level protective film 102 mainly containing S on the surface of the n-type GaAs layer 101. (Fig. 1 (a)). Next, a desired region of the sample was scanned with a focused ion beam 103 (Si ions, accelerating voltage of 50 kV) to selectively remove the protective film 102 (FIG. 1B). Then, the selective W-CVD technique is applied to the sample to apply the n-type GaAs layer 1
The W film 104 was selectively deposited on the protective film 102 patterned on 01 (FIG. 1C). The selective W-CVD conditions at this time are as follows: gas flow rate WF 6 : 2 sccm, SiH
4 : 1 sccm, total gas pressure 0.12 torr, substrate temperature 320 ° C.

【0007】以上の工程により、GaAs層101上の
微細な領域にW膜104の形成が可能になった。ここ
で、本実施例ではn型GaAs層101上に対してW膜
104の被着を行っているが、InAs等のその他のII
I−V 化合物半導体層に対しても適用可能である。
Through the above steps, the W film 104 can be formed in a fine region on the GaAs layer 101. Here, although the W film 104 is deposited on the n-type GaAs layer 101 in this embodiment, other II such as InAs is used.
It is also applicable to the IV compound semiconductor layer.

【0008】<実施例2>本発明の一実施例を図2に示
す工程図を用いて説明する。半絶縁性基板200上に形
成したn型GaAsよりなる能動層201を過飽和の硫
化アンモニウム溶液に浸漬した後、減圧雰囲気で加熱処
理(250〜500℃)により、n型GaAs層よりな
る能動層201の表面にSを主とする単原子層レベルの
保護膜202を形成した(図2(a))。次に電子線20
3の照射により、微細なゲート電極形成領域以外の保護
膜202を除去した(図2(b))。電子線203の加速
電圧は50kVでありビーム径は約20nmである。ま
た、電子線照射時に試料を加熱することにより、保護膜
202の除去を容易にした。
<Embodiment 2> An embodiment of the present invention will be described with reference to the process chart shown in FIG. The active layer 201 made of n-type GaAs formed on the semi-insulating substrate 200 is immersed in a supersaturated ammonium sulfide solution, and then heat-treated (250 to 500 ° C.) in a reduced pressure atmosphere to form an active layer 201 made of an n-type GaAs layer. A monoatomic layer-level protective film 202 mainly containing S was formed on the surface of the (FIG. 2A). Next, electron beam 20
By the irradiation of No. 3, the protective film 202 other than the fine gate electrode formation region was removed (FIG. 2B). The acceleration voltage of the electron beam 203 is 50 kV and the beam diameter is about 20 nm. In addition, the protective film 202 was easily removed by heating the sample during electron beam irradiation.

【0009】次いで、選択W−CVD技術を試料に適用
して、能動層201上にパターニングされた保護膜20
2上に選択的にW被着を行い、ゲート電極204を形成
した(図2(c))。このときの選択W−CVD条件は、
ガス流量WF6 :2sccm,SiH4:1sccm,全ガス圧
0.12torr,基板温度320℃である。次にAuGe/
Ni/Auよりなるソース・ドレイン電極205を通常
のリフトオフ法により形成してMESFETを完成した
(図2(d))。
Next, the selective W-CVD technique is applied to the sample to pattern the protective film 20 on the active layer 201.
Then, W was selectively deposited on the layer 2 to form the gate electrode 204 (FIG. 2C). The selective W-CVD conditions at this time are
The gas flow rate is WF 6 : 2 sccm, SiH 4 : 1 sccm, the total gas pressure is 0.12 torr, and the substrate temperature is 320 ° C. Next is AuGe /
The source / drain electrodes 205 made of Ni / Au were formed by an ordinary lift-off method to complete the MESFET (FIG. 2 (d)).

【0010】本実施例によれば、通常の光リソグラフィ
技術の解像限界以下の微細な領域にドライエッチングを
用いることなくゲート電極204を形成できる。従来の
技術において記述したようにMESFETはゲート電極
204の短縮により大幅な高速,高性能化が図れる。
According to this embodiment, the gate electrode 204 can be formed in a fine region below the resolution limit of the ordinary photolithography technique without using dry etching. As described in the prior art, the MESFET can achieve significantly high speed and high performance by shortening the gate electrode 204.

【0011】[0011]

【発明の効果】集束したエネルギ線の線幅と同程度のG
aAs層上の微細領域に金属膜の形成を制御性良く行う
ことができる。
EFFECT OF THE INVENTION G of the same width as the focused energy ray width
The metal film can be formed in a fine region on the aAs layer with good controllability.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例1の工程図。FIG. 1 is a process diagram of a first embodiment of the present invention.

【図2】本発明の実施例2の工程図。FIG. 2 is a process diagram of a second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

100…半絶縁性基板、101…n型GaAs層、10
2…保護膜、103…イオンビーム、104…W膜。
100 ... Semi-insulating substrate, 101 ... N-type GaAs layer, 10
2 ... Protective film, 103 ... Ion beam, 104 ... W film.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】化合物半導体層の表面の酸化膜を除去した
後、極薄層保護膜を前記化合物半導体の表面上に形成す
る工程,エネルギ線の照射により、所望領域の前記極薄
層保護膜を除去する工程,金属の選択CVD技術により
前記化合物半導体層の上の前記極薄層保護膜を除去され
た化合物半導体層表面に金属を被着することなく、前記
極薄層保護膜が形成されている前記化合物半導体の層上
に選択的に金属を被着する工程を含むことを特徴とする
金属電極の形成方法。
1. A step of forming an ultrathin layer protective film on the surface of the compound semiconductor after removing the oxide film on the surface of the compound semiconductor layer, and irradiation of energy rays, whereby the ultrathin layer protective film in a desired region is formed. And removing the ultra-thin layer protective film on the compound semiconductor layer by a metal selective CVD technique without forming a metal on the surface of the compound semiconductor layer. A method of forming a metal electrode, comprising the step of selectively depositing a metal on the layer of the compound semiconductor.
【請求項2】請求項1において、前記化合物半導体層表
面の酸化膜を除去した後、前記極薄層保護膜を前記化合
物半導体の表面上に形成する工程が、前記化合物半導体
層を過飽和の硫化物溶液に浸漬する工程及び大気圧下或
いは減圧下で熱処理を施す工程を含む金属電極の形成方
法。
2. The step of forming the ultrathin layer protective film on the surface of the compound semiconductor after removing the oxide film on the surface of the compound semiconductor layer according to claim 1, 1. A method for forming a metal electrode, which comprises a step of immersing in a metal solution and a step of performing heat treatment under atmospheric pressure or reduced pressure.
【請求項3】請求項1において、前記エネルギ線の照射
による所望領域の前記極薄層保護膜の除去工程が、電子
或いはイオン等の荷電粒子線のマスクレス照射により行
われる金属電極の形成方法。
3. The method for forming a metal electrode according to claim 1, wherein the step of removing the ultrathin layer protective film in a desired region by irradiation with the energy beam is performed by maskless irradiation with a charged particle beam such as electrons or ions. ..
JP9257892A 1992-04-13 1992-04-13 Formation of metallic electrode Pending JPH05291299A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9257892A JPH05291299A (en) 1992-04-13 1992-04-13 Formation of metallic electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9257892A JPH05291299A (en) 1992-04-13 1992-04-13 Formation of metallic electrode

Publications (1)

Publication Number Publication Date
JPH05291299A true JPH05291299A (en) 1993-11-05

Family

ID=14058319

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9257892A Pending JPH05291299A (en) 1992-04-13 1992-04-13 Formation of metallic electrode

Country Status (1)

Country Link
JP (1) JPH05291299A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6583034B2 (en) 2000-11-22 2003-06-24 Motorola, Inc. Semiconductor structure including a compliant substrate having a graded monocrystalline layer and methods for fabricating the structure and semiconductor devices including the structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6583034B2 (en) 2000-11-22 2003-06-24 Motorola, Inc. Semiconductor structure including a compliant substrate having a graded monocrystalline layer and methods for fabricating the structure and semiconductor devices including the structure

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