JPH05290579A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To accelerate an access time in a semiconductor memory. CONSTITUTION:The logical threshold value voltage of the inverter 101 of an output signal potential detection circuit 1 is made 2.2V or above and the logical threshold value voltage of the inverter 103 is made 0.8V or below previously. When D is on an H level and DB is on an L level, a P channel transistor 201 is turned on and an N channel transistor 202 is turned off and though a node P is voltage-raised, when the node P is arrived at the logical threshold voltage of the inverter 101, the P channel transistor 301 is turned off and Dout is prevented from being voltage-raised to source potential. When D is on a low level and DB is on a high level, though the node P is voltage-dropped gradually, the N channel transistor 302 is turned off when the node P arrives at the logical threshold value voltage of the inverter 103 and the node P is prevented from being voltage-dropped to grounded potential. Then, the voltage amplitude of an output signal is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to circuit means for limiting an amplitude voltage of an output signal in an output circuit.

[0002]

2. Description of the Related Art A semiconductor memory device using CMOS technology has a voltage amplitude of an input / output signal from 0 V to a power supply potential and half the power supply potential as an intermediate potential because of its element capability and characteristics of CMOS technology. Then, a CMOS logic voltage level is generally set such that the range from 0 V to the intermediate potential is “Low” level (hereinafter, L level) and the range from the intermediate potential to power supply potential is “High” level (hereinafter, H level). Is being used for. On the other hand, in the TTL semiconductor device, the voltage amplitude of the input / output signal is from 0 V to the power supply potential, and 0.
A TTL logic voltage level is used which sets the voltage to an L level when the voltage is 8 V or less and the H level when the voltage is 2.2 V or more. From this, in the CMOS semiconductor memory device, the input / output voltage level is made TTL compatible, that is, the L level always drops below 0.8 V, and the H level always becomes 2.2.
It is common to have CMOS logic voltage levels and TTL logic voltage levels available above V.

FIG. 3 is a circuit diagram showing an example of a conventional output circuit. In FIG. 3, 5 is an output buffer circuit, and 2 is an output driver circuit. The data signal read from the memory cell is input to the signal line D, and the inverted signal of D is D
Input to B. If D is H level, output driver circuit 2
N-channel transistor 202 of the OFF state, D
Since B is at the L level which is an inverted signal of D, the P-channel transistor 201 is in the ON state. Therefore, the output signal line Dout becomes the power supply potential. When D changes from H level to L level, the N-channel transistor 202 is turned on and DB is H which is an inverted signal of D.
Since it becomes the level, the P-channel transistor 201 becomes O
The N state is set. Therefore, the output signal line Dout is 0V
become. A timing chart showing the operation of the circuit of FIG. 3 is shown in FIG.

[0004]

However, the above-mentioned conventional techniques have the following problems.

Although the storage capacity of semiconductor memory devices has been increasing year by year, the current situation is that the chip size does not change significantly, and the size of the semiconductor elements, the width of the wiring, and the wiring of the semiconductor memory device. By reducing the distance between
Supports an increase in storage capacity without increasing the chip size. However, as the size of the semiconductor device is reduced, various problems occur, and it takes time to change the signal of the CMOS logic voltage level, that is, to change the voltage from 0 V to the power supply potential or vice versa. There is a problem that the size becomes large. Therefore, the present invention is intended to solve such a problem, and its purpose is to detect the voltage of a data signal output from an output circuit and control the output driver circuit to control the voltage amplitude of the output signal. It is another object of the present invention to provide a semiconductor memory device having circuit means for reducing the TTL logic voltage level within a range satisfying the TTL logic voltage level.

[0006]

According to another aspect of the present invention, there is provided a semiconductor memory device in which an output circuit has circuit means for detecting a voltage of an output signal and circuit means for performing switching control by the circuit means for detecting a voltage of the output signal. , Limiting the voltage amplitude of the output signal.

[0007]

According to the structure of the present invention, by detecting the voltage of the output data signal and controlling the output driver circuit, when the input signal voltage is at the L level, the voltage of the data output line is up to 0.8V. When the input signal voltage is H level, by outputting the data signal whose voltage is limited within the range of the lower limit of 2.2V, the voltage amplitude of the output signal is ensured while ensuring the range satisfying the TTL logic voltage level. To reduce.

[0008]

1 is a circuit diagram showing an embodiment of the present invention.
D is a line into which the data signal read from the memory cell is input, DB is a line into which the inverted signal of D is input, and Dout is a line from which the signal is output. 1
Is an output signal voltage detection circuit (hereinafter referred to as a detection circuit), which detects the amplitude of the output signal by setting the logical threshold voltage of the inverters 101 and 104. In this embodiment, it is assumed that the logical threshold voltage of the inverter 101 is 2.2V and the logical threshold voltage of the inverter 104 is 0.8V. Reference numeral 2 is an output driver circuit, and 3 is a switching circuit for controlling a voltage change of the node P.

Now, assume that the node P is 0V in the initial state. Therefore, the input voltage level of the detection circuit 1 is also 0V.
Then, both the node Q and the node R become L level. Therefore, the P-channel transistor 3 of the switching circuit 3
01 is in the ON state, and the N-channel transistor 302 is in the OFF state. At this time, when an H level signal is input to D and an L level signal is input to DB, the P channel transistor 201 of the driver circuit 2 is turned on.
And the N-channel transistor 202 is turned off.
It becomes a state. Therefore, since the P-channel transistor is ON and the N-channel transistor is OFF in both the driver circuit 2 and the switching circuit 3, the voltage of the node P (that is, the output data line Dout) rises to the power supply potential. However, the node P is 2.2
When the voltage becomes V, the logical threshold voltage of the inverter 101 of the detection circuit 1 is reached, the node Q becomes H level, and the P-channel transistor 301 of the switching circuit 3 becomes OFF state. Therefore, the potential of the node P becomes 2 Do not rise above 2V. Further, when the potential of the node P reaches 0.8 V, the N-channel transistor 302 of the switching circuit 3 is turned on, but since the N-channel transistor 202 of the driver circuit 2 is turned off,
No current flows in the ground potential line.

Next, it is assumed that D becomes L level and DB becomes H level. Then, the P-channel transistor 201 of the driver circuit 2 is turned off and the N-channel transistor 202 is turned on. further,
N-channel transistor 302 of switching circuit 3
Since it is still in the ON state, the potential of the node P starts to drop to the ground potential. Then, when the potential of the node P drops to 0.8 V, the logical threshold voltage of the inverter 104 of the detection circuit 1 is reached, so that the node Q becomes L level,
N-channel transistor 302 of switching circuit 3
Is turned off, the voltage drop at the node P stops. Also at this time, the P-channel transistor 301 of the switching circuit 3 is turned on when the potential of the node P becomes lower than 2.2 V, but the P-channel transistor 301 of the driver circuit 2 is turned on.
Since the channel transistor 201 is in the OFF state, no current will flow in from the power supply potential line.

In the initial state, it is assumed that an L level data signal is input to D and an H level data signal is input to DB. As described above, the P-channel transistor 301 of the switching circuit 3 is in the ON state and the N-channel transistor 302 is in the OFF state, but since D is at the H level and DB is at the L level, the P of the driver circuit 2 is P.
The channel transistor 201 is turned off and the N channel transistor 202 is turned on. At this time, since the node P is cut off from both the power supply potential line and the ground potential line, the potential state at that time is maintained. In this example, 0V (that is, L level) is maintained. Next, if D changes to H level and DB changes to L level,
The P-channel transistor 201 of the driver circuit 2 is O
The N state is set and the N channel transistor 202 is turned off.
It becomes a state. The P-channel transistor 301 of the switching circuit 3 is in the ON state and the N-channel transistor 3
Since 02 is in the OFF state, the voltage of the node P rises to the power supply potential. However, as described above, when the inverter 101 of the detection circuit 1 reaches 2.2V, the N-channel transistor 301 of the switching circuit 3 is turned off, and the potential of the node P does not exceed 2.2V. Further, when D becomes H level and DB becomes L level, the P-channel transistor 201 of the driver circuit 2 is
Is in the OFF state, the N-channel transistor 202 is in the ON state, the P-channel transistor 301 of the switching circuit 3 is in the OFF state, and the N-channel transistor 302 is in the ON state, so that the voltage of the node P drops to the ground potential. However, this is also caused by the inverter 104 of the detection circuit 1 when the voltage becomes 0.8 V, as described above.
Is turned off, the potential of the node P does not drop below 0.8V. Therefore, regarding the voltage amplitude of the output data signal, by setting the logical threshold voltage of the inverter 101 of the detection circuit 1 to the lower limit of 2.2 V or more and the logical threshold voltage of the inverter 104 to the upper limit of 0.8 V or less,
The amplitude can be made smaller than the CMOS logic voltage level while satisfying the TTL logic voltage level.

FIG. 5 is a circuit diagram showing another embodiment of the present invention. The circuit 6 in FIG. 5 is an output driver control circuit,
The circuit 1 is the same as the detection circuit 1 described above, and the inverter 1
The logic threshold voltage of 01 is set to 2.2 V or more and the logic threshold voltage of the inverter 103 is set to 0.8 V or less.
For the sake of explanation, assume that the logical threshold voltage of the inverter 101 is 2.2V and the logical threshold voltage of the inverter 103 is 0.8V. The output driver circuit 2 is also the same as the circuit described above.

It is assumed that the node P is 0V in the initial state. Assuming that an L level signal is input to D and an H level signal is input to DB, the output of the detection circuit 1 is L level, and therefore the NA of the output buffer control circuit 6 (hereinafter, control circuit 6) is NA.
The input of the ND gate 601 becomes the L level which is the output of the detection circuit and the H level which is the signal of the DB, and therefore the output becomes the H level. In response to this, the P-channel transistor 201 of the driver circuit 2 is turned off. on the other hand,
Since the input of the NOR gate 602 becomes the L level which is the output of the detection circuit and the L level of D, the output becomes the H level and the N-channel transistor 202 is turned on. Therefore, Dout outputs L level.

Next, when D becomes H level and DB changes to L level, the input of the NAND gate 601 becomes the L level of the detection circuit output and the L level of DB, so the output becomes L level and the P channel transistor. 201 is turned on. Since the input of the NOR gate 602 becomes the L level of the detection circuit output and the H level of D, the output is the L level and the N-channel transistor 202 is in the OFF state. Therefore, the voltage of the node P rises to the power supply potential, but when it reaches 2.2 V, it becomes the logical threshold voltage of the inverter 102 of the detection circuit 1, so that the node S becomes the H level. Therefore, the output of the NAND gate 601 becomes H level, the P-channel transistor 201 is turned off, and the node P stops increasing in voltage. In this process, when the node P becomes 0.8 V or more, it becomes the logical threshold voltage of the inverter 104 of the detection circuit 1 and the node T
Changes to H level, but the output of the NOR gate does not change at L level and the N-channel transistor 202 is OF
Keep F state.

Further, when D becomes L level and DB changes to H level, the node P is at H level, so the node S
Becomes H level and DB becomes H level, so that the output of the NAND gate 601 becomes H level and the P-channel transistor 201 becomes OFF state. And node T is H
Since the D level becomes the L level at the level, the output of the NOR gate 602 becomes the H level and the N channel transistor 20
Since 2 is turned on, the voltage of the node P drops to the ground potential. However, when the potential of the node P becomes 0.8 V or less, the logical threshold voltage of the inverter 104 of the detection circuit is reached, so that the node T becomes L level and the input of the NOR gate 602 becomes L level of the node T and D level. Since it goes to L level, the output of the NOR gate goes to L level, and the N-channel transistor 202 is turned off. Therefore, the node P stops the voltage drop. Also in this process, when the potential of the node P becomes 2.2 V or less, the logic threshold voltage of the inverter 102 of the detection circuit is reached, and therefore the node S becomes L level, but the output of the NAND gate remains at H level and does not change. .. In this way, the voltage amplitude of the output signal can be limited even in the circuit of FIG.

The above description of FIG. 5 is for the case where D changes from the initial state to the L → H → L (DB is H → L → H) level, but D is H → L → H. (DB
It goes without saying that the voltage amplitude of the output signal can be suppressed in the same process even when changes from the L level to the L level. A timing chart of the circuit of FIG. 5 is shown in FIG.

In the above embodiment, the output driver circuit is MOSF.
Although the case of ET has been described, the present invention can be applied to a bipolar transistor and other elements, and the output driver circuit 2 and the switch circuit 3 in FIG. 1 are all P-channel transistors or all N-channel transistors. With the configuration, the same effect as that of the circuit of FIG. 1 can be obtained by inverting the signal given to the gate.

[0018]

As described above, in the output circuit of the present invention, by shortening the amplitude voltage width of the output signal, the access time can be shortened and the TTL can be achieved.
Since the signal voltage amplitude is reduced within the range that satisfies the logical voltage level, connection with an electronic device having a TTL compatible input level can be performed without any change.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an output circuit of a semiconductor memory device showing an embodiment of the present invention.

2 is a timing chart showing the operation of the circuit of FIG.

FIG. 3 is a circuit diagram showing an example of a conventional output circuit.

4 is a timing chart showing the operation of the circuit of FIG.

FIG. 5 is a circuit diagram of an output circuit of a semiconductor memory device showing another embodiment of the present invention.

FIG. 6 is a timing chart showing the operation of the circuit of FIG.

[Explanation of symbols]

1 ... Output signal potential detection circuit 101 ... Output voltage detection inverter 102 ... Inverter 103 ... Output voltage detection inverter 104 ... Inverter 2 ... Output driver circuit 201 ... P channel Transistor 202 ... N channel transistor 3 ... Switching circuit 301 ... P channel transistor 302 ... N channel transistor 4 ... Inverter 5 ... Output buffer circuit 501-505 ... Buffer inverter 6・ ・ ・ Output driver control circuit 601 ・ ・ ・ NAND gate 602 ・ ・ ・ NOR gate D ・ ・ ・ Data signal line DB ・ ・ ・ Inverted data signal line Dout ・ ・ ・ Output signal line P, Q, R, S, T ... Nodes in each figure

Claims (1)

[Claims] 1. An output circuit comprising circuit means for detecting a voltage of an output signal and circuit means for controlling switching of the output circuit by the circuit means for detecting a voltage of the output signal, and limiting a voltage amplitude of the output signal. A semiconductor memory device characterized by.