JPH052868A - Fifo memory and bi-directional communication system - Google Patents

Abstract

PURPOSE:To execute the bi-directional transfer of data by providing separately first and second memory cell arrays holding transfer data from a first port to the second port and from the second port to the first port and the control means of first-in and first-out. CONSTITUTION:The first memory cell array 11 which can hold data to be transferred from the first port 30 to the second port 40 is provided. An R address counter 12 and W address counter 15 controlling the operation of the first memory cell array 11 by the form of the first-in and first-out of data are provided. Next, the second memory cell array 21 which can hold data to be transferred from the second port 40 to the first port 30. Then, the R address counter 22 and W address counter 25 for controlling the operation of the second memory cell array 21 by the form of the first-in and first-out of data are provided. Thus, inverse directional communication is possible even if transfer data exists in the memory cell array 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a FIFO (first-in first-out) memory in which data is written and read in a fixed order, and a bidirectional communication technique in the memory, for example, in a bidirectional communication system including a plurality of terminal systems. Related to effective technology.

[0002]

2. Description of the Related Art When data is transferred between a plurality of devices or functional blocks having different data processing speeds or transfer speeds, such a difference in capability or speed is absorbed.
An IFO memory or the like can be used as the buffer memory. Such a FIFO memory has, for example, a memory cell array in which a plurality of memory cells are arranged in a matrix, an address decoder for addressing the memory cells included in the memory cell array, and a write / read operation for the addressed memory cells. And a read / write circuit for performing the same, and further includes a read address counter and a write address counter for internally generating an access address. The read address counter increments the data read address and supplies it to the address decoder, and the write address counter sequentially increments the write address for each data write operation and supplies it to the address decoder. Each address counter is configured by a ring counter or the like having the number of bits corresponding to the storage capacity of the memory cell array. When the data is empty, the values of the read address counter and write address counter match, the value of the write address counter is incremented each time writing is performed, and the value of the read address counter is incremented each time reading is performed. It The values of the read address counter and the write address counter are always monitored internally, and if the two values match during a write operation, new write cannot be accepted. Notify the device or function module. When the two values match during the read operation, there is no more data to be read, and this state is notified to the device or functional module from which the data is read by an empty signal.

As the above-mentioned FIFO memory, there is a bidirectional communication FIFO memory which enables bidirectional communication.
As an example of a document describing such a FIFO memory, "A B published in ESSCIRC" 86.
idealDataTransmis
sion 32K × 8 Dual Port FIFO
There is "Memory". According to this, the two ports A and B can be switched by changing the logical state of the PS pin, and by providing such a function, the system A and the system B coupled to the FIFO memory concerned can be connected. Two-way communication between them is possible.

[0004]

A conventional F for bidirectional communication.
When the present inventor examined the IFO memory, the memory cell array, the peripheral circuit for controlling the memory cell array, and the flag logic circuit are each provided in only one system.
For example, if the data transfer from the system B to the system A is started before the transmission of the data to be transferred from the system A to the system B is completely completed, a part of the data to be transferred from the system A to the system B is lost. , The data transferred from system B to system A may be destroyed. Therefore, the data transfer from system A to system B must be completed before the data transfer from system B to system A is completed. It has been found to have the drawback of not being able to start. That is, according to the present inventor, the conventional bidirectional communication FIFO memory has a drawback that the data transfer in the other direction cannot be started until the data transfer in the one direction is completely completed. It was revealed.

It is an object of the present invention to provide a FIFO memory which can start data transfer in the other direction without waiting for the end of the data transfer in one direction, and a bidirectional communication system including such a FIFO memory. To do.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, a first memory cell array capable of holding data to be transferred from the first port to the second port,
First control means for controlling the operation of the first memory cell array in a first-in first-out format for data, a second memory cell array capable of holding data to be transferred from the second port to the first port, and the second memory A second control means for controlling the operation of the cell array in a first-in first-out format of data is included to form a FIFO memory.
In a more specific aspect, a first write address counter for updating a data write address to the first memory cell array, and a first read address counter for updating a data read address from the first memory cell array. And a second write address counter for updating the data write address to the second memory cell array, and a data read address from the second memory cell array. The second control means can be formed to include a second read address counter for updating.
Furthermore, such a FIFO memory can be formed on one semiconductor substrate.

[0009]

According to the above-mentioned means, the first memory cell array capable of holding the data to be transferred from the first port to the second port, and the first control means for controlling the operation of the first memory cell array in the first-in first-out format of the data. And a second memory cell array capable of holding data to be transferred from the second port to the first port, and second control means for controlling the operation of the second memory cell array in a first-in first-out format of data.
Even if the data related to the data transfer from the first port to the second port exists in the first memory array cell,
By utilizing the memory array cells, it is possible to transfer data from the second port to the first port, which allows data transfer in the opposite direction without waiting for the end of data transfer in one direction. Acts like.

[0010]

FIG. 2 shows a bidirectional communication system according to an embodiment of the present invention.

In FIG. 2, reference numeral 1 is a FIFO memory that enables bidirectional communication by absorbing the difference in communication speed between the terminal system 3 and the terminal system 5,
A communication LSI 2 for enabling serial communication using a serial communication line is arranged between the FIFO memory 1 and the terminal system 3, and the FIFO memory 1 is also provided.
A communication LSI 4 for enabling serial communication using a serial communication line is arranged between the device and the terminal system 5. For example, the data to be transferred from the terminal system 3 to the terminal system 5 may be the communication LS from the terminal system 3.
Data transmitted to the FIFO memory 1 via I2 and read from the FIFO memory 1 in a first-in first-out format are transmitted to the terminal system 5 in a serial format via the communication LSI 4. Data to be transferred from the terminal system 5 to the terminal system 3 is
Is transmitted from the FIFO memory 1 to the FIFO memory 1 via the communication LSI 4, and the data read from the FIFO memory 1 in the first-in first-out format is transmitted to the terminal system 3 in the serial format via the communication LSI 2.

FIG. 1 shows a detailed configuration example of the FIFO memory 1.

As shown in FIG. 1, the FIFO memory 1 enables data transfer in the other direction without waiting for the end of data transfer in the one direction. It has a FIFO memory unit. First
The FIFO memory unit 10 functions as a buffer memory when transferring data from the terminal system 5 to the terminal system 3 in FIG. 2, and includes a memory cell array 11 in which a plurality of memory cells are arranged in an array, a communication LSI 4 Output data from the memory cell array 11
Data input buffer (Din Buffer) for writing to
r) 18, a write (W) address counter 15 for generating a write address of the memory array cell 11, the write address counter 15 and the data input buffer 18
Write controller (W Contr)
16), a data output buffer (Dout Buffer) 17 for transferring output data from the memory array cell 11 to the communication LSI 2, and a memory cell array 11
Read (R) address counter 12 for generating a read address, a read controller (R Control) 17 for controlling the operation of the read address counter 12 and the data output buffer 17, and a full flag F.
Flag logic (Logi for generating F1 * (* indicates low active) and empty flag EF1 *
c) comprises 14 Data input / output ports 30, 40
Are shared by the first FIFO memory unit 10 and the second FIFO memory unit 20. That is, the input / output port 30
Is a data input buffer 18 and a data output buffer 27.
And functions as a data input port for the first FIFO memory unit 10 and the second FIFO memory unit 2
For 0, it functions as a data output port. Similarly, the input / output port 40 is coupled to the data input buffer 28 and the data output buffer 17, and functions as a data output port for the first FIFO memory unit 10 and as a data input port for the second FIFO memory unit 20. .

In the above configuration, the reset signal RSa
When the input logic state of * satisfies the condition of the minimum reset pulse width and is asserted to the low level, the read counter 1
2 and the write counter 15 are always returned to the initial state. During this reset cycle, the flag logic 14
Thus, the empty flag EF1 * is set to the low level and the full flag FF1 * is set to the high level. The write cycle is started by asserting the write enable signal Wa * to the low level when the full flag FF1 * is not set. That is, when the write enable signal Wa * is asserted to the low level, the input buffer 18 is controlled by the write controller 16.
Is activated, transfer data from the terminal system 5 can be fetched, and the fetched data is stored in the memory array 11 according to the address generated by the write address counter 15. The data writing in this case is performed continuously and independently of any simultaneous read operation. At the time of data overflow, the flag logic 14 asserts the full flag FF1 * at a low level to prohibit the subsequent write operation. In response to this, the communication LSI 4 on the terminal system 5 side is
The data transmission to the FO memory 1 is stopped. The read cycle is started by the read enable signal Ra * being asserted to the low level when the empty flag EF1 * is not set. Data is accessed independently of the simultaneous write operation and in the order in which they were written. When the read enable signal Ra * is negated to the high level, all the output terminals of the data output buffer 17 are in the high impedance state until the next read operation, whereby the data input buffer 28 can take in the data. . When the final data is read from the memory cell array 11, the flag logic 14 asserts the empty flag EF1 * to the low level, and the subsequent data read operation is prohibited. In the above write cycle, the empty flag EF1 * is negated to a high level, and thereafter, the valid read cycle can be activated.

The second FIFO memory section 20 is also the first FI
It is configured similarly to the FO memory unit 10. That is, the first
The FIFO memory unit 20 functions as a buffer memory at the time of data transfer from the terminal system 3 to the terminal system 5 in FIG. 2, and includes a memory cell array 21 in which a plurality of memory cells are arranged in an array, a communication memory cell 21. The output data from the LSI 2 is fetched and is stored in the memory cell array 2
Data input buffer 28 for writing to 1, write address counter 25 for generating a write address of memory array cell 21, and write address counter 25
And a write controller 26 that controls the operation of the data input buffer 28, a data output buffer 27 that transfers output data from the memory array cell 21 to the communication LSI 4, and a read address counter that generates a read address of the memory cell array 21. 22, a read controller 27 that controls the operation of the read address counter 22 and the data output buffer 27, and a full flag FF.
It includes flag logic 24 for generating 2 * and empty flag EF2 *.

In the above configuration, the reset signal RSb
When the input logic state of * satisfies the condition of the minimum reset pulse width and is asserted to the low level, the read counter 2
2 and the write counter 25 are always returned to the initial state. During this reset cycle, the flag logic 24
Thus, the empty flag EF2 * is set to the low level and the full flag FF2 * is set to the high level. The write cycle is started by asserting the write enable signal Wb * at a low level when the full flag FF2 * is not set. That is, when the write enable signal Wb * is asserted to the low level, the input buffer 28 is controlled by the write controller 26.
Is activated, transfer data from the terminal system 3 can be fetched, and the fetched data is stored in the memory array 21 in accordance with the address generated by the write address counter 25. The data writing in this case is performed continuously and independently of any simultaneous read operation. At the time of data overflow, the flag logic 24 asserts the full flag FF2 * at a low level to prohibit the subsequent write operation. In response to this, the communication LSI 2 on the terminal system 3 side is
The data transmission to the FO memory 1 is stopped. The read cycle is started by the read enable signal Ra * being asserted to the low level when the empty flag EF2 * is not set. The data is accessed independently of the simultaneous write operation and in the order of writing. When the read enable signal Rb * is negated to the high level, all the output terminals of the data output buffer 27 are in the high impedance state until the next read operation, whereby the data input buffer 28 can take in the data. . When the final data is read from the memory cell array 21, the empty flag EF2 * is asserted to the low level by the flag logic 24, and the subsequent data read operation is prohibited. In the above write cycle, the empty flag EF2 * is negated to a high level, and thereafter, the valid read cycle can be activated.

By thus providing the first FIFO memory unit 10 and the second FIFO memory unit 20, data transfer from the terminal system 3 to the terminal system 5 and conversely data transfer from the terminal system 5 to the terminal system 3 are performed. Transfer is enabled, in which case the second FIFO memory unit 20 is used for data transfer from the terminal system 3 to the terminal system 5, and the terminal system 5 to the terminal system 3
By using the first FIFO memory unit 10 for data transfer to and from the terminal system 3, the first FIFO memory unit 10 is used even when data to be transferred from the terminal system 3 to the terminal system 5 exists in the memory array cell 21. By doing so, the data transfer from the terminal system 5 to the terminal system 3 can be started, and the terminal system 3
Even when data to be transferred from the terminal system 5 to the terminal system 5 exists in the memory cell array 11, the data transfer from the terminal system 3 to the terminal system 5 can be started by using the second FIFO memory unit 20.

According to the above embodiment, the following operational effects can be obtained.

(1) Terminal system 3 to terminal system 5
The second FIFO memory unit 20 is used for the data transfer to the terminal system 5 and the first FIFO memory unit 10 is used for the data transfer from the terminal system 5 to the terminal system 3.
For example, even when the data to be transferred from the terminal system 3 to the terminal system 5 exists in the memory array cell 21, the data transfer from the terminal system 5 to the terminal system 3 is started by using the first FIFO memory unit 10. Further, the data to be transferred from the terminal system 3 to the terminal system 5 can be stored in the memory cell array 11
, The data transfer from the terminal system 3 to the terminal system 5 can be started by using the second FIFO memory unit 20.
Two-way data communication between the five can be efficiently performed.

(2) Since the FIFO memory 1 as described above is formed on one semiconductor substrate and integrated into one chip, the hardware scale of the bidirectional communication system to which it is applied can be reduced. In addition, reliability can be improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and it goes without saying that various modifications can be made without departing from the scope of the invention. Yes.

For example, the FIFO memory and the communication LSI in the above embodiment may be formed on one semiconductor substrate.

In the above description, the case where the invention made by the present inventor is mainly applied to the two-way communication system which is the field of application which is the background of the invention has been described, but the present invention is not limited thereto and a plurality of The present invention can be applied to a multiprocessor system including the above processor and other systems that require bidirectional communication.

The present invention can be applied to a condition including at least a first port and a second port that enable data input / output.

[0025]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the first memory cell array capable of holding the data to be transferred from the first port to the second port, the first control means for controlling the operation of the first memory cell array in the first-in first-out format of the data, and the second port. Unidirectional data transfer by separately providing a second memory cell array capable of holding data to be transferred from the first port to the first port, and second control means for controlling the operation of the second memory cell array in a first-in first-out format of data. The data transfer in the opposite direction can be started without waiting for the end of.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a FIFO memory according to an embodiment of the present invention.

FIG. 2 is a configuration block diagram of a two-way communication system including the FIFO memory.

[Explanation of symbols]

1 FIFO memory 2 Communication LSI 3 terminal system 4 Communication LSI 5 terminal system 10 First FIFO section 11 memory cell array 12 Read address counter 13 Read controller 14 flag logic 15 Write address counter 16 Write controller 17 Data output buffer 18 data input buffer 20 Second FIFO unit 21 memory cell array 22 Read address counter 23 Read controller 24 flag logic 25 Write Address Counter 26 Write Controller 27 data output buffer 28 data input buffer 30 First I / O port 40 Second I / O port

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Fujio Yamamoto             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Date             Tachicho LSI Engineering             Within the corporation (72) Inventor Hidenori Kitajima             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony company Hitachi Ltd. Musashi factory

Claims (4)

[Claims] 1. A first memory cell array capable of holding data to be transferred from the first port to the second port in a FIFO memory having a first port and a second port for enabling input / output of data, respectively. A first control means for controlling the operation of the first memory cell array in a first-in first-out data format; a second memory cell array capable of holding data to be transferred from the second port to the first port; A FIFO memory including a second control means for controlling the operation of the second memory cell array in a first-in first-out data format. 2. A first control means for updating a data write address to the first memory cell array.
The second control means includes a write address counter and a first read address counter for updating the data read address from the first memory cell array, and the second control means for updating the data write address to the second memory cell array. 2. The FIFO memory according to claim 1, further comprising a second write address counter and a second read address counter for updating a data read address from the second memory cell array. 3. The semiconductor device according to claim 1, wherein the semiconductor substrate is formed on one semiconductor substrate.
Alternatively, the FIFO memory described in 2. 4. A two-way communication system comprising the FIFO memory according to claim 1, 2 or 3, and a terminal system which is coupled so as to be able to exchange data with each other via the FIFO memory.