JPH0247145B2 - RUUPUSHIKIDEETADENSOSOCHI - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a loop data transmission device used for exchanging data between a plurality of digital data processing devices.

Conventional configuration and problems thereof In recent years, a method of configuring a communication path between a plurality of digital data processing devices has been attracting attention. For example, multiprocessor systems are considered to be useful for speeding up digital data processing, and the method of configuring communication paths between the plurality of processors is important. A loop data transmission device is used as a communication path between various digital data processing devices such as these processors and peripheral devices.

Conventionally, a device having a configuration as shown in FIG. 5 has been known as a loop data transmission device.

Problems in the data transmission system and configuration of the conventional loop data transmission device will be explained using FIG.

In FIG. 5, 1 to 6 are data processing devices, 10
~15 are queue memories, 20~22 are data buses, 23~25 are input ready signals, 26~28 are write signals, 30~32 are data buses, 33~
35 is an output ready signal, 36 to 38 are shift signals, 40 to 42 are input interfaces, 50 to 5
5 is a ring bus data line, 56-61 is a ring bus acknowledge signal, 62-67 is a ring bus output ready signal, 70-72 is an output interface, 80-82 is a data bus, 83-85 is an input ready signal. Signals, 86-88 are write signals, 9
0 to 92 are data buses, 93 to 95 are output ready signals, and 96 to 98 are read signals.

In FIG. 5, three data processing devices 1,
Consider transmitting data from each of the data processing devices 2 and 3 to only a desired one of the three data processing devices 4, 5, and 6. For example, when transmitting data from the data processing device 2 to the data processing device 4, the data processing device 2 includes destination information corresponding to the destination data processing device 4 in the output data and outputs the data onto the data bus 21. After confirming that the input ready signal 24 of the queue memory 11 is on, a write signal 27 is generated to temporarily store the data in the queue memory 11. At this time, the queue memory 11 outputs the output ready signal 3.
Turn on 4. The stored data is stored in the queue memory 11 until the input interface 41 confirms that the data line 51 of the ring buses 50 to 67 is empty and the ring bus acknowledge signal 58 is in the reset state. After meeting at the input interface 4,
1 from the queue memory 11 to the data bus 31.
The data is read through the ring bus and output onto the data line 52 of the ring bus. At this time, a bit indicating that the ring bus data line 52 is not a vacant slot is added to the ring bus data line 52, a shift signal 37 is generated, and the ring bus output ready signal 64 is turned on. .

The data on the data line 52 of the ring bus is
After the input interface 42 learns that the output ready signal 64 of the ring bus is turned on, it checks whether the slot is empty or not, but since it is not an empty slot, the slot is directly connected to the data line 53 of the ring bus.
The ring bus acknowledge signal 5
8 is turned on, and the ring bus output ready signal 6
5 is turned on.

The data on the data line 53 of the ring bus is
After the output interface 72 learns that the output ready signal 65 of the ring bus has turned on, it checks whether the slot is empty and the destination information, but since the destination information does not correspond to the data processing device 6, the data is output as is on the data line 54 of the ring bus, and the acknowledge signal 59 of the ring bus is output as is.
is turned on, and the ring bus output ready signal 66
is turned on.

The operation of the output interface 71 is similar to that of the output interface 72, and outputs the data sent from the output interface 72 as it is onto the data line 55 of the ring bus, and turns on the acknowledge signal 60 of the ring bus. and turn on the ring bus output ready signal 67.

The data on the data line 55 of the ring bus is
After the output interface 70 learns that the output ready signal 67 of the ring bus is turned on, it checks whether the slot is empty and the destination information. Therefore, the output interface 70 outputs the data onto the data bus 80, turns on the acknowledge signal 61 of the ring bus, and after confirming that the input ready signal 83 is on, generates the write signal 86 and writes the data to the queue memory. The data is written to 13. After this, the queue memory 13 turns on the output ready signal 93.

The data processing device 4 generates the read signal 96 only when it is ready to receive data and the output ready signal 93 is on,
Data is read from the queue memory 13 through the data bus 90. This completes a series of data transmissions.

FIG. 6 shows input interfaces 40 to 40 in FIG.
42 is a block diagram for explaining in detail,
The input interface 41 will be explained as an example.
Normally, when the input interface 41 outputs data onto the data line 51 of the ring bus, the control unit 100 learns that the input interface 40 has outputted data onto the data line 51 of the ring bus, and the controller 100 outputs the switching signal. 101 is set in the reset state, the data switching section 102 bypasses the data as it is onto the data line 103, waits until it is confirmed that the acknowledge signal 58 of the ring bus is in the reset state, generates the latch signal 104, and transfers the data. is read into the latch 105, the ring bus acknowledge signal 57 is turned on, and the latch 105
The data read into the data line 5 of the ring bus
After adding enough delay time to confirm on 2,
The operation of turning on the ring bus output ready signal 64 is repeated. The ring bus acknowledge signal 57 is reset when the ring bus output ready signal 63 goes into the reset state, and the ring bus output ready signal 64 is reset when the ring bus acknowledge signal 58 goes on. Ru. However, only when the queue memory 11 outputs new data, that is, only when the queue memory 11 outputs data onto the data bus 31 and turns on the output ready signal 34, the execution of the repetitive operation is repeated. It is temporarily interrupted at the break and performs the next interrupt-like operation. In other words, the output ready signal 6 of the ring bus
3 is turned on, the empty slot confirmation unit 106 checks the control bit 107 on the data line 51 indicating whether or not the slot is empty, and if the empty slot confirmation result 108 is in the reset state, it turns on. Up to this point, the switching signal 101 is reset and the data on the data line 51 of the ring bus is transferred directly to the data line 10 as in the above-mentioned repeated operation.
3, waits until it is confirmed that the ring bus acknowledge signal 58 is in the reset state, generates the latch signal 104, reads the data into the latch 105, turns on the ring bus acknowledge signal 57, and waits until the ring bus acknowledge signal 58 is in the reset state. After a delay time long enough for the data read into the latch 105 to be established on the data line 52 of the ring bus, the operation of turning on the output ready signal 64 of the ring bus is repeated. The vacant slot confirmation result 108
When the slot is turned on, the switching signal 101 is turned on, and the control bit adding section 110 resets the control bit 109 indicating whether or not the slot is empty to the data on the data bus 31, and the added data is transferred to the data. Bypass on the line 103, turn on the ring bus acknowledge signal 57, wait until the ring bus acknowledge signal 58 is in the reset state, generate the latch signal 104, and load the data into the latch 105. After the data is shifted out onto the data bus 31 by generating the shift signal 37, and the data read into the latch 105 is established on the data line 52 of the ring bus, the data is shifted out onto the data line 52 of the ring bus. The output ready signal 64 is turned on, and the above interrupt-like operation is completed. The other input interfaces 40, 42 are also exactly the same.

FIG. 7 shows the output interfaces 70 to 70 in FIG.
72 is a block diagram for explaining in detail,
The output interface 70 will be explained as an example.
The output interface 70 outputs a ring bus output ready signal 67 to indicate that the output interface 71 has output data onto the data line 55 of the ring bus.
When the slot is turned on, the control unit 111 becomes aware of the fact that the slot in the data is empty, and the control unit 111 first checks the control bit 112 indicating whether or not the slot is empty in the data and the destination information 11 in the data.
3 to the empty slot confirmation unit 114 and the destination verification unit 11
Find out in 5. Only when the slot is not empty and the destination information 113 corresponds to the data processing device 4, that is, only when the empty slot confirmation result 116 is in the reset state and the destination verification result 117 is on, the switching signal 118 is turned on. The data switching unit 119 bypasses the data directly onto the data bus 80, waits for the input ready signal 83 to turn on, generates the write signal 86, turns on the ring bus acknowledge signal 61, and outputs the control bit. When the ring bus acknowledge signal 56 is in the reset state, the addition command signal 121 is turned on for the addition unit 120, and the control bit 123 indicating whether or not there is a vacant slot in the open data line 122 is turned on. Wait until it is confirmed that the latch 1 is present, generate the latch signal 124, and
After a delay time sufficient for the data read into the latch 125 to be established on the data line 50 of the ring bus, the output ready signal 62 of the ring bus is turned on. Whether the empty slot confirmation result 116 is on or the destination verification result 11
7 is in the reset state, the switching signal 11
8 to the reset state and the data line 5 of the ring bus
The data on the data line 122 is bypassed directly onto the data line 122, and after waiting until it is confirmed that the acknowledge signal 56 of the ring bus is in the reset state, the latch signal 124 is generated and the data on the data line 122 is transferred to the latch 125. read, turn on the ring bus acknowledge signal 61, and close the latch 12.
After a delay time long enough for the data read into the ring bus to be established on the data line 50 of the ring bus, the output ready signal 62 of the ring bus is turned on. The ring bus acknowledge signal 61 is reset when the ring bus output ready signal 67 goes into the reset state, and the ring bus output ready signal 62 is reset by the ring bus acknowledge signal 5.
6 is turned on, it is reset. The other output interfaces 71 and 72 are also exactly the same.

In the loop data transmission device configured as shown in FIG.
1, 42 and all output interfaces 70,
Separate queue memory 1 for each of 71 and 72
0, 11, 12, 13, 14, and 15 are required, so when the amount of each data flowing into the loop data transmission device fluctuates drastically, for example, around a certain time, a large amount of data is output only from the data processing device 1. , even if a large amount of data is output only from the data processing device 3 at another time, all the queue memories 10 to 15 are set so that each of the queue memories 10 to 15 does not overflow. Capacity must be determined. In other words, since each queue memory 10 to 15 must have a memory capacity that does not overflow, each queue memory 10 to
15 has a very large capacity, which is disadvantageous in reducing the size of a loop data transmission device or a multiprocessor system using the loop data transmission device.

Also, from another perspective, all queue memory 1
There are few situations in which the queue memories 10 to 15 are nearly fully stored, and it can be pointed out that the usage efficiency of the queue memories 10 to 15 as a whole is low.

Another disadvantage is that an extra control bit 107 or 112 indicating whether or not a slot is vacant must be added to the data on the ring bus.
Furthermore, this means that each input interface 40
- 42, the configuration (control bit addition unit 1
10) A configuration (empty slot confirmation unit 106) for monitoring the control bits on the data line of the ring bus on the input side is required, and each output interface 70 to 72 has a configuration for monitoring the control bit on the data line of the ring bus on the input side. After outputting the data on the ring bus on the input side to the queue memories 10 to 15, the control bit on the data line of the ring bus on the output side is turned on. Configuration (control bit adding section 12
0) is required. Also,
As seen in FIGS. 6 and 7, latches 105 and 125 are required for each interface.
Therefore, each interface 40 to 42, 70
-72 has the disadvantage that the structure becomes complicated.

Purpose of the Invention The purpose of the present invention is to solve the above conventional problems, reduce the total memory capacity in the device, simplify the device configuration, and provide a small and inexpensive loop data transmission device. It is in.

Composition of the Invention The present invention is a loop data transmission device equipped with a circular closed circuit in which a plurality of interfaces are connected by an active transmission line, and which has low usage efficiency, which is common to conventional loop data transmission devices. All queue memories are unified, and the functions of conventional queue memories are provided in a newly introduced circular active transmission line. As a result, the unified memory is used efficiently, so the total memory capacity required for the entire device is small, and the device can be made smaller and cheaper. Furthermore, the present invention simplifies the configuration of the interface portion that controls the circular transmission line by introducing an active transmission line consisting of a first-in first-out memory.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described based on FIGS. 1 to 4. FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, three data processing devices 131, 132, 133 each have
A system is depicted in which data is transmitted only to a desired device among the data processing devices 134, 135, and 136.

Each of 140 to 145 in FIG. 1 is an active transmission line composed of first-in first-out memories, and all of them are connected to input interfaces 150, 151, 152 and output interfaces 153, 154, 155, respectively. They are connected in a ring shape through the cables to form a ring-shaped transmission path.

160-171 are data lines, 172-177 are output ready signals, 178-183 are write signals, 184-189 are shift signals, 190-19
5 is an input ready signal, 200-202 is a data bus, 203-205 is an output ready signal, 206-
208 is a read signal, 210 to 212 are input ready signals, 213 to 215 are data buses, 216
~218 is a write signal.

A data transmission system of a loop type data transmission device embodying the present invention will be explained with reference to FIG. For example, consider the case where data is transmitted from the data processing device 132 to the data processing device 134. It is assumed that the data processing device 132 includes destination information corresponding to the data processing device 134, which is the destination, in the data to be output. The data output from the data processing device 132 is sent to the input interface 15.
1 to the annular transmission path, this data is output to the data processing device 134 which is the destination and becomes ready to receive the data, until the data processing device 134 receives the data via the output interface 153. Continue circling around the circular transmission line to meet up. The data in this circular transmission path has an extra control bit 1 that indicates whether the data is in an empty slot or not, which was required in the conventional example.
07 or 112 is unnecessary, and has the advantage that the data bit width is smaller than that of the conventional example.

FIG. 2 shows the input interface 150 of FIG.
152 is a block diagram for explaining in detail the input interface 151. FIG. In the input interface 151, the active transmission line 141 on the input side is normally connected to the data line 162.
Output ready signal 1 indicates that data has been output on
73 is turned on, the control unit 220 knows,
The switching signal 221 is reset and the data switching section 222 transfers the data as it is to the data line 1.
63, waits until the active transmission line 142 turns on the input ready signal 191, generates the write signal 179, and then outputs the write signal 179 to the active transmission line 1.
42, the simple operation of generating the cyst signal 185 and shifting out the data on the data line 162 is repeated. However, only when the data processing device 132 is capable of outputting data, that is, only when the data processing device 132 turns on the output ready signal 204, the execution of the repetitive operation is temporarily interrupted at a break in the repetitive operation. , turns on the switching signal 221, generates the read signal 207, and outputs the data processing device 13.
2 onto the data bus 201,
The data is bypassed directly onto the data line 163, and the write signal 17 is waited until the active transmission line 142 turns on the input ready signal 191.
9 and sends it to the active transmission path 142, the interrupted repeating operation is resumed.
The other input interfaces 150, 152 are also exactly the same. Since the input interfaces 150 to 152 operate in a simple manner as described above, a simple structure is possible. A configuration 110 for resetting a control bit indicating whether data required by the conventional input interfaces 40, 41, and 42 is in an empty slot, a configuration 106 for monitoring the control bit of input data, and a latch. 105 is not necessary.

FIG. 3 shows the output interface 153 of FIG.
155 is a block diagram for explaining in detail the output interface 153. FIG. The output interface 153 normally outputs an output ready signal 17 to indicate that the active transmission line 145 on the input side has outputted data onto the data line 170.
7 is turned on, the control unit 223 resets the switching signal 224 and causes the data switching unit 225 to directly transfer the data to the data line 17.
1, waits until the active transmission line 140 turns on the input ready signal 195, generates the write signal 183, and then outputs the write signal 183 to the active transmission line 14.
0, the simple operation of generating a shift signal 189 and shifting out the data on the data line 170 is repeated. However, only when the data processing device 134 is in a state where it can receive data, that is, only when the input ready signal 210 is turned on, the destination verification section 227 checks the destination information 226 in the data on the data line 170. Only when the destination information 226 and the data processing device 134 correspond, that is, only when the destination verification result 228 is on, the switching signal 224 is turned on and the data switching unit 225 bypasses the data as it is onto the data bus 213 and writes it. signal 21
6 to cause the data processing device 134 to take in the data, a shift signal 189 is generated to shift out the data on the data line 170, but if they do not correspond, that is, the destination verification result 228 is In the case of the reset state, the switching signal 22
4 is reset, the data on the data line 170 is directly bypassed onto the data line 171 by the data switching unit 225, and the active transmission line 140 is
After waiting until input ready signal 195 is turned on, a write signal 183 is generated and sent to the active transmission line 140, and then a shift signal 189 is generated to shift out the data on data line 170. Thereafter, the repeating operation is resumed. The other output interfaces 154 and 155 are also exactly the same. Conventional output interfaces 70, 71,
Configuration 1 for monitoring a control bit indicating whether data is in an empty slot or not, which was required by 72.
14, the arrangement 120 and latch 125 for turning on the control bits are not required.

First, the functions of the active transmission lines 140 to 145 in FIG. 1 will be briefly described. For example, the active transmission line 140 is essentially the output interface 1
53, and serves to propagate the data groups to the input interface 150 while maintaining the order in which the data groups were received. Input interface 15
0 receives the data group according to the order. If the input interface 150 cannot receive data, the data group is temporarily stored in the active transmission path 140 while maintaining the order until the input interface 150 is able to receive the data.
The functions of all other active transmission lines are also exactly the same.

FIG. 4 is a block diagram for explaining the active transmission lines 140 to 145 in detail, taking the active transmission line 140 as an example. Blocks 230 to 232 are registers, and there are as many registers as there are storage stages of active transmission lines, that is, as many stages as first-in-first-out memories. The register groups are cascaded by data lines 234, 235, and 236. The input data line is 171, and the output data line is 160. Data lines 234-236, 1
71 and 160 may each have 5 lines, ie, 5 bits, or may each have 32 lines, ie, 32 bits. As for the control signals, the write signal is 1.
83, the input ready signal is 195, the output ready signal is 172, and the shift signal is 184. Block 237 is an input control section, blocks 238 to 240 are register control sections, and block 241 is an output control section.

Input ready signal 195 is active transmission line 1
If data for that number of stages is stored in 40,
and is turned on except in transient cases during write operations or internal data propagation operations. The write operation by the write signal 183 is valid only when the input ready signal 195 is on.

When the input ready signal 195 is on and the write signal 183 is generated, first the register control unit 2
A register write signal 242 is generated from 38,
The data on data line 171 is written to register 230, temporarily resetting input ready signal 195, but then register write signal 243
occurs, and the data written in the register 230 is written in the register 231. At this point, the input ready signal 195 is turned on again. Furthermore, writing to the subsequent register occurs, and the data input from the data line 171 is propagated toward the register 232 on the output side. For example, in an initial state where there is no data stored in the active transmission path 140, one generation of the write signal 183,
In other words, if only one set of data is input,
The data propagates more and more and is finally written into the register 232, turning on the output ready signal 172. Next, when another set of data is input, the propagation of that data is stopped when it is written to one register before the register 232. In this way, it is possible to store data corresponding to the number of register stages of the active transmission line 140 while maintaining the input order, and it is also possible to read out the data group in accordance with the above order. For example, in the above case, shift signal 1
84, the first set of data stored in the register 232, that is, the data on the data line 160, is shifted out and lost, and the output ready signal 172 is immediately reset and the above-mentioned data is lost. The contents of the register one position before the register 232 are written to the register 232 in the reverse procedure to the data writing case, and the output ready signal 172 is turned on again. That is, the contents of the register are shifted rightward by one position, and at this time, the contents of the second set of data are output on the data line 160. If the shift signal 184 is generated again in this state, the second set of data stored in the register 232 will be shifted out and lost, and the number of data in the active transmission path will become zero.
Output ready signal 1 until new data is input
72 remains reset.

As mentioned above, the active transmission line has not only the function of a simple transmission line but also the function of a queue memory for waiting, so the closed circuit of the active transmission line that connects them in a ring is composed of multiple queue memories as shown in Figure 5. Since it is possible to centralize and share the memory without physically or functionally distributing it, it is possible to increase the efficiency of use as a queue memory. That is, it has the advantage that the total memory capacity required for the entire loop data transmission device can be significantly reduced.

As the active transmission line, for example, first-in-first-out memory (SN74S225; manufactured by TI) can be used. Furthermore, when integrating a system such as a loop data transmission device or a multiprocessor system including a loop data transmission device, manufacturing technology for first-in first-out memory is established. , as can be easily inferred from FIG. 4, can be realized by a simple arrangement of repeating elements of silicon devices. It is easy to directly connect the groups with the silicon elements corresponding to the active transmission lines 140 to 145. This is because it does not require a large capacity like the queue memory shown in Figure 5, that is, the active transmission line in Figure 1 may have fewer stages than the queue memory, so the array of silicon elements is physically shorter. It is to become something. As mentioned above, this embodiment has the advantage of being suitable for integrated circuit implementation.

The embodiment shown in FIG. 1 is a data transmission system in which each piece of data in a circular transmission path includes destination information corresponding to the destination data processing device as a control signal. A data transmission method different from such a data transmission method in which the destination of data is made clear at the time of sending the data and the destination information is included in the data itself can also be cited as an embodiment of the present invention. In other words, the destination of the data is not clarified at the time of sending the data, and the data itself is sent out into a circular transmission path without including destination information, and when it reaches the output interface while circulating in the circular transmission path. If the data processing device corresponding to the output interface is in a state where it can receive data, the data is sent to the data processing device, but if the data processing device is not in a state where it can receive data, it is sent again. As an example, a data transmission method in which the data continues to circulate in a circular transmission path is possible. In this case, the control signal that determines the destination of data at the output interface is the input ready signal 210, 211, or 212 in FIG. Therefore, the block diagram of the embodiment of this method is exactly the same as that in FIG. 1, and the input interfaces 150 to 151 in FIG.
are exactly the same, and in the block diagram of the output interfaces 153 to 155 in FIG.
The one that removes matches.

The embodiment shown in FIG. 1 is an example in which each interface has only either the input interface function or the output interface function, but the interface has the input interface function and the output interface function. It may also have the following functions. For example, if a digital data processor, which is an example of a data processing device, is connected to each of multiple interfaces that have both the functions of an input interface and the function of an output interface, a high-performance processor that can freely communicate with each other can be created. You can easily configure a multiprocessor system.

Effects of the Invention As explained above, the loop data transmission device of the present invention provides the same functions as the conventional loop data transmission device with a smaller memory capacity and a simpler interface by providing a ring-shaped active transmission path. This can be achieved with the face configuration, and
The integrated circuit can be easily integrated both in terms of scale and structure, and its practical effects are great.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a loop data transmission device showing an embodiment of the present invention, Fig. 2 is a detailed block diagram of the input interface in Fig. 1, and Fig. 3 is a detailed block diagram of the output interface in Fig. 1. 4 is a detailed block diagram of the active transmission line in FIG. 1, FIG. 5 is a block diagram of a conventional loop data transmission device, and FIG. 6 is a detailed diagram of the input interface in FIG. 5. FIG. 7 is a detailed block diagram of the output interface in FIG. 131-136...data processing device, 140-1
45... Active transmission line, 150-152... Input interface, 153-155... Output interface, 160-171... Data line, 172-1
77... Output ready signal, 178-183... Write signal, 184-189... Shift signal, 190-
195...Input ready signal, 200-202...Data bus, 203-205...Output ready signal, 20
6-208...Read signal, 210-212...Input ready signal, 213-215...Data bus, 2
16-218...Write signal, 220...Control unit,
221...Switching signal, 222...Data switching unit, 22
3... Control unit, 224... Switching signal, 225... Data switching unit, 226... Destination information, 227... Destination collation unit, 228... Destination collation result, 230-232... Register, 234-236... Data line, 237... Input control Part, 238-240...Register control part, 2
41...Output control unit, 242-244...Register write signal.

Claims (1)

[Claims] 1. A plurality of interfaces provided corresponding to a plurality of data processing devices, and a plurality of active transmission lines connecting the plurality of interfaces to form a circular closed circuit. each of the plurality of active transmission lines is configured with a first-in-first-out memory having an arbitrary number of stages of one or more, and at least one of the plurality of interfaces is connected to a corresponding data processing device and has an input selection function that selectively sends any one of the data sent from the active transmission line on the input side to the active transmission line on the output side of itself based on the input control signal, and the rest of the plurality of interfaces are A loop type data loop having an output selection function that selectively sends data sent from an active transmission line on the input side to either the corresponding data processing device or the active transmission line on the output side based on the output control signal. Transmission device. 2. The loop data transmission device according to claim 1, wherein each of the plurality of interfaces has both an input selection function and an output selection function.