JPH05282473A - Data processor - Google Patents

Abstract

PURPOSE:To improve the throughput of a program including data input and output to and from an external data memory on a data driving system data processor which has a cyclic pipeline. CONSTITUTION:A packet generation part 12 generates a packet which has an instruction for reading data out of the external data memory 22 and an instruction for writing data after arithmetic in the external data memory 22 in addition to an arithmetic instruction. Then a data input part 14 arranged before an ignition control part 16 reads data required for the arithmetic out of the external data memory 22 and a data output part 20 arranged behind an arithmetic execution part 18 writes result data in the external data memory 22 right after the arithmetic execution. Consequently, two-term arithmetic can be performed only by circulating the packet on the cyclic pipeline by one round.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processor, and more particularly to a data driven data processor having a cyclic pipeline coupled to an external data memory.

[0002]

2. Description of the Related Art In a conventional data driven data processing apparatus 1, as shown in FIG.
The firing control unit 3, the data input / output unit 4, and the operation execution unit 5 are connected in a cyclic pipeline (ring) structure. In such a data processing device 1, when a program written in a high-level language (C language) as shown in FIG. 4 is executed, the processing is performed as shown in FIG. That is, after starting the program, first, in step S1, the packet generation unit 2 generates a packet having an instruction to read the value of the variable x from the external data memory 6. Further, in step S3, a packet having an instruction to read the value of the variable y from the external data memory 6 is generated. Next, in step S5, the data input / output unit 4 reads data from the address of the variable x. In step S7, the data input / output unit 4 similarly reads data from the address of the variable y. After that, when these packets circulate on the cyclic pipeline and are input to the packet generation unit 2, a process of replacing the instruction of each packet with a binary operation instruction (x + y) is performed in each of steps S9 and S11. And output from the packet generator 2. Each packet output from the packet generator 2 is
It is input to the firing control unit 3, and in step S13, a process of queuing packets is performed. The packet that arrives first among the two packets is recorded in the queuing memory of the firing control unit 3 and waits for the packet to be the partner of the calculation to be input to the firing control unit 3. When the second packet to be operated is input to the firing control unit 3, a new packet having a binary operation instruction and two data is generated from the two packets and sent to the operation execution unit 5. ..
Then, in step S15, the calculation execution unit 5 calculates two data, that is, adds x and y, and sets the calculation result in the data part of the input packet.
Output from the calculation execution unit 5. The packet output from the operation execution unit 5 is input to the packet generation unit 2, and in step S17, an instruction to write data in the external data memory 6 is set in the packet and output from the packet generation unit 2. After that, when this packet is input to the data input / output unit 4, in step S19, a process of writing the data of the data unit of the packet, that is, the data after the execution of the operation to the external data memory 6, is performed, and the operation of executing the program is performed. To finish.

[0003]

As described above, when the program as shown in FIG. 4 is executed by the data processing device 1, the packet needs to go around the cyclic pipeline three times. At this time, the operation efficiency of each functional unit that constitutes the data processing device 1 is low, which is a cause that the processing efficiency of a program that frequently uses input / output processing to / from the external data memory 6 cannot be improved.

Therefore, a main object of the present invention is to provide a data processing device which has a high processing efficiency even for a program which requires input / output from an external data memory.

[0005]

The present invention includes a packet pair detection means for detecting a pair of packets transmitted through a cyclic pipeline, and an operation execution means for executing an operation based on the packet pair. In a data driven data processing device that inputs data from an external data memory to a pipeline and outputs data from a cyclic pipeline to an external data memory, data is input from the external data memory to the cyclic pipeline before the packet pair generation means. And a data output means for outputting data from the cyclic pipeline to the external data memory at a stage subsequent to the operation executing means.

[0006]

In the packet generating means, a packet having an instruction for inputting data from the external data memory and an instruction for outputting data after the execution of the operation to the external data memory is generated in the instruction section. By arranging the data input means for inputting the data from the external data memory before the packet pair detection means, it is possible to input the data from the external data memory before performing the packet pair detection. Further, by arranging the data output means for outputting data to the external data memory after the arithmetic execution means,
Immediately after execution of the operation, data after the operation is executed is written to the external data memory. As a result, in the case of the program of FIG. 4 described above, the arithmetic program can be executed by making one round of the packet on the cyclic pipeline.

[0007]

According to the present invention, even in a program that requires input of data from an external data memory and output of data to an external data memory, the number of times a packet circulates on a cyclic pipeline is reduced. Because you can
The processing efficiency is improved. The above-mentioned objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of the embodiments with reference to the drawings.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a data processing apparatus 10 of this embodiment includes a packet generation unit 12, a data input unit 14, an ignition control unit 16, an operation execution unit 18 and a data output unit 20, which are cyclic. It is connected to the pipeline structure. Then, the external data memory 22 is coupled to the data input unit 14 and the data output unit 20.

The packet generator 12 reads out packet information stored in an external program memory (not shown), generates a packet based on the packet information, and outputs the packet. The packet output from the packet generation unit 12 is input to the data input unit 14. Data input unit 14
If a read instruction from the external data memory 22 is set in the instruction section of the packet input to the data input section, the data input section 14 reads data from the external data memory 22 (input Yes) processing is executed. The read data is set in the data part of the packet, and is output from the data input part 14 onto the cyclic pipeline. The data output from the data input unit 14 is input to the ignition control unit 16 through the cyclic pipeline.

When the operation instruction set in the packet input to the firing control unit 16 is a binary operation instruction,
The firing control unit 16 waits for a pair of packets. If the packet to be paired has not arrived, the packet information is written in the waiting memory (not shown) of the firing control unit 16. If the packet to be paired has already arrived and the packet information has been written to the queuing memory, the packet information written to the queuing memory is read, and the packet information and the packet information is input later. Packet and 2
One packet having a term operation instruction and two data is generated and output from the firing control unit 16. If the unary operation instruction is set in the packet input to the firing control unit 16, the queuing control unit 16 outputs the packet as it is without waiting processing. The packet output from the firing control unit 16 is input to the calculation execution unit 18.

The operation executing section 18 reads out the operation instruction set in the input packet and executes the operation on the data set in the data section of the packet. When the packet operation instruction is a binary operation instruction, a predetermined binary operation is performed on the two data set in the data portion of the input packet. The execution result of the operation is set in the data part of the input packet and is output from the operation executing part 18. The packet output from the calculation execution unit 18 is input to the data output unit 20.

When the packet input to the data output unit 20 has an instruction for writing data in the external data memory 22 in addition to the normal operation instruction, the data output unit 20 outputs the data in the data portion of the packet. A process of writing (outputting) to the external data memory 22 is performed. Then, after the writing is completed, the packet is output from the data output unit 20. When the write command to the external data memory 22 is not set in the packet, the data output unit 20 outputs the packet as it is. The packet output from the data output unit 20 is input to the packet generation unit 12. In the packet generator 12, the content of the packet to be executed next is read from the external program memory,
A new packet is generated.

In such a data processing apparatus 10, when executing the program shown in FIG. 4 exemplified above, the processing operation as shown in FIG. 2 is performed. After starting the program, first, in step S21, the packet generation unit 1
By 2, the instruction for reading the data of the variable x from the external data memory 22, the instruction for performing the binary operation, and the instruction for writing the data after the operation to the external data memory 22 are set in the packet, and the packet is generated from the packet generation unit 12. Is output. In step S23, the packet generator 12 sets an instruction for reading the data of the variable y from the external data memory 22, an instruction for performing a binary operation, and an instruction for writing the data after the operation to the external data memory 22 in the packet. The packet is output from the packet generator 12.

Thereafter, in step S25, the value of the variable x is set to the external data memory 2 by the data input unit 14.
2 and the data is set in the data part of the packet. Further, in step S27, the value of the variable y is set to the external data memory 2 by the data input unit 14.
2 and the data is set in the data part of the packet.

In step S29, the ignition control unit 1
At 6, waiting processing is performed on the packet output from the data input unit 14 to form a pair. By this queuing processing, when two packets to be subjected to the binary operation are prepared, one packet having the binary operation instruction and the two data is generated from them. This new packet is sent from the firing control unit 16 to the operation executing unit 18, and in step S31, the operation executing unit 18 performs a binary operation on two data in the data portion of the input packet, that is, x +.
Calculate y. The calculation result z is set in the data part of the packet and sent from the calculation execution part 18 to the data output part 20. Then, in step S33, a process of writing the operation result to the address of the variable z is performed based on the data write command to the external data memory 22 set in the command part of the packet.

As described above, in the data processing device 10 of this embodiment, the binary operation program as shown in FIG. 4 can be executed only by the packet making one round in the cyclic pipeline. Therefore, the processing efficiency is significantly higher than the conventional one.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart showing an operation when the binomial arithmetic program shown in FIG. 4 is executed in the data processing device of FIG. 1 embodiment.

FIG. 3 is a block diagram showing a conventional technique.

FIG. 4 is an example of a program for performing binary operation processing.

5 is a flowchart showing an operation when the binomial arithmetic program shown in FIG. 4 is executed in the data processing device shown in FIG.

[Explanation of symbols]

 10 ... Data processing device 12 ... Packet generating unit 14 ... Data input unit 16 ... Ignition control unit 18 ... Calculation execution unit 20 ... Data output unit 22 ... External data memory

Claims (1)

[Claims] 1. An external data memory in the cyclic pipeline, comprising packet pair detection means for detecting a pair of packets transmitted through the cyclic pipeline, and operation execution means for executing an operation based on the packet pair. From the external data memory to the cyclic pipeline in the preceding stage of the packet pair generation means, in which the data is input from the cyclic pipeline and the data is output from the cyclic pipeline to the external data memory. A data processing device, wherein data input means for inputting data is arranged, and data output means for outputting data from the cyclic pipeline to the external data memory is arranged after the operation executing means.