JPH07152794A - Logic simulator - Google Patents

Abstract

PURPOSE:To interrupt/resume simulation by designating description information when simulation is executed through the use of a hardware description language. CONSTITUTION:A construction information output means 11 outputs construction information (c) on hardware, and an operation information output means 12 outputs operation information (d) on hardware. A line information output means 13 adds line information to operation information (d). An execution control means 14 processes execution information included in the operation information (d). An interruption control means 15 refers to interruption information (e) when the execution control means 14 detects line information on operation information (d), controls the interruption/resumption of simulation, rewrites/refers to interruption information (e) and displays the hardware description language (b) of an interrupted place. A command control means 16 executes the command of a simulator by the instruction of the interruption control means 15. Thus, simulation can be interrupted/resumed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulator, and more particularly to a logic simulator used for design verification of a board or the like constituting an LSI or a computer.

[0002]

2. Description of the Related Art In a conventional logic simulator, logic simulation is interrupted when a signal change or a specified signal value condition is satisfied. However, interruption processing is performed by specifying a line number in a hardware description language (hereinafter referred to as HDL). Didn't go. Therefore, in order to check in which part of the HDL the specified signal is described, the signal defined in the HDL is associated with the number of lines of the HDL before the simulation is started, and the signal value is obtained after the simulation is completed. The display was made in correspondence with the HDL (Japanese Patent Laid-Open No. Hei 2)
-272644 gazette. Logic simulation result display method).

[0003]

In the above-mentioned conventional method, the simulation cannot be interrupted by designating the HDL file name and the number of lines.

[0004]

The logic simulator of the present invention is a logic simulator that performs simulation by using HDL representing the structure and operation of hardware as an input, after performing syntax analysis and semantic analysis on HDL. Structure information output means for inputting information, extracting the structure of hardware and outputting it as structure information, and inputting information after performing syntax analysis and semantic analysis for HDL, extracting the operation of hardware and operating Operation information output means for outputting as information, line information output means for adding line information consisting of a corresponding HDL file name and line number to the operation information, and structure information and operation information as input Execution control means for processing the included execution information and line information, and when the execution control means detects the line information included in the operation information. And interruption control means for referring to the interruption information, rewriting and reference and HDL Viewing interrupt location and control interruption information simulation suspend and resume,
The command control means is provided for executing the command of the simulator according to the instruction of the interruption control means.

[0005]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the logic simulator of the present invention.

As shown in FIG. 1, the logic simulator of this embodiment receives the HDL analysis information a, which is the information after syntax / semantic analysis on HDLb, and extracts the hardware structure to extract the structure information. The structure information output means 11 for outputting as c, the operation information output means 12 for inputting the HDL analysis information a and extracting the operation of the hardware and outputting as operation information d, and the HDL corresponding to the operation information d
Line information output means 13 for adding a file name and a line number, and an execution control means 14 for processing the execution information contained in the operation information d by inputting the structure information c and the operation information d.
When the execution control means 14 detects the line information included in the operation information d, the interruption information e is referred to, the interruption / restart control of the simulation, the rewriting / reference of the interruption information, and the HDL display of the interruption point are performed. The control means 15 and the command control means 16 for executing the command of the simulator according to the instruction of the interruption control means 15.

FIG. 2 is a diagram showing structure information. The structure information stores the signal value and the identifier of the operation information indicating the operation of the circuit at the connection destination of the signal. The execution control unit 14 refers to the signal value from the structure information, and executes the operation information of the connection destination when the signal changes to perform the simulation.

FIG. 3 is a diagram showing operation information. The operation information includes signal propagation information, execution information indicating the operation of the circuit, HDL file names, and line information for storing line numbers. The execution control means 14 executes the simulation when the execution information is read, and transfers the control to the interruption control means 15 when the line information is read.

FIG. 4 is a diagram showing interruption information. The interruption information stores an interruption condition and an interruption flag for identifying whether the interruption condition is valid or invalid. The interruption control means 15 searches for an interruption condition that matches the line information from among valid interruption flags. If a match is found, the simulation will stop.

FIG. 5 is a flow chart showing an example of the operation in the logic simulator of this embodiment. When the simulation is started (step 51), first, the structural information is read (step 52), and then the operation information is read one instruction at a time (step 53). When the operation information is execution information, simulation execution such as signal value propagation is performed according to the execution information (step 55). When the simulation execution (step 55) is completed, it is determined whether the simulation is completed (step 56). If not completed, the process returns to operation information reading (step 53). If it is finished, the simulation is finished (step 5).
A) do. If the motion information is line information, the interruption information is referred to determine whether the simulation is to be interrupted (step 5).
7). If not interrupted, read operation information (step 5)
Return to 3). Command execution if interrupted (step 5
Perform 8). In command execution (step 58), rewriting / reference of signal value, HDL corresponding to the interrupted part
The part is displayed. When the simulation restart command is executed (step 59), the process returns to the operation information reading (step 53).

[0012]

As described above, the logic simulator of the present invention interrupts the simulation by designating the HDL file name and the number of lines, and refers to the signal value at that time or rewrites the signal value to perform the simulation. By being able to restart, the HDL rewriting time, the HDL analysis time, and the simulation input data generation time can be saved.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a logic simulator of the present invention.

FIG. 2 is a diagram showing structural information in the logic simulator of the present embodiment.

FIG. 3 is a diagram showing operation information in the logic simulator of this embodiment.

FIG. 4 is a diagram showing interruption information in the logic simulator of the present embodiment.

FIG. 5 is a flowchart showing an example of the operation of the logic simulator of this embodiment.

[Explanation of symbols]

 11 structure information output means 12 operation information output means 13 line information output means 14 execution control means 15 interruption control means 16 command control means a HDL analysis information b HDL c structure information d operation information e interruption information

Claims (2)

[Claims] 1. A logic simulator that performs a simulation using a hardware description language that expresses the structure and operation of hardware as input, and inputs information after performing syntax analysis and semantic analysis on the hardware description language, A structure information output means that extracts the hardware structure and outputs it as structure information, and inputs the information after parsing and semantic analysis to the hardware description language, and extracts the hardware operation and outputs it as operation information. Operation information output means for outputting, line information output means for adding line information consisting of a file name and line number of a corresponding hardware description language to the operation information, operation information by inputting structure information and operation information Execution control means for processing the execution information and line information included in the When the information is detected, the interruption information is referred to, the interruption control is performed by controlling the interruption and restart of the simulation, rewriting the interruption information, displaying the hardware description language of the interruption information, and the instruction of the interruption control means. And a command control means for executing the command of (1). 2. The operation information is read one by one after the structure information is read, and when the operation information is the execution information, the simulation is executed according to the execution information. After executing the simulation, determine whether the simulation is finished,
If it is not finished, return to the operation information reading. If it is finished, the simulation is ended. If the operation information is line information, refer to the interruption information to judge whether the simulation is interrupted. If not interrupted, return to the operation information reading. , In the case of interruption, the command is executed. In the command execution, the signal value is rewritten and referenced, and the hardware description language part corresponding to the interrupted part is displayed. When the command to restart the simulation is executed, the operation information is displayed. A logic simulator characterized by returning to reading.