JPS6057436A - Arithmetic processor - Google Patents

Abstract

PURPOSE:To attain the continuous use of an arithmetic unit as well as the check of an arithmetic function by providing plural arithmetic circuits of the same function within the arithmetic unit. CONSTITUTION:An operation I0 is started at a time point T0 when an arithmetic unit is not used for a continuous operation. In such a case, a corresponding operand O0 is fetched to registers 12a and 12b since registers 12a, 12b, 13a and 13b are all idle. Then arithmetic circuits 13a and 13b perform operations respectively. The results of these operations are held at a register 16 via a selection circuit 15, and at the same time the parities are produced from the arithmetic results by parity generating circuits 14a and 14b respectively. These parities are compared with each other by a comparator 17, and the result of this comparison is fetched by a register 18. Two machine cycles are needed for a period between the arithmetic start and the fetching of the check result. Therefore, the hardware of double structure is used in case the instruction for use of the arithmetic unit has an interval of >=1 instruction. Thus the function check is possible for the arithmetic circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an arithmetic processing device whose arithmetic unit is composed of a plurality of elements, which can be flexibly controlled and used depending on the situation.

Conventional technology In conventional arithmetic units that process large amounts of data at high speed, a series of processing is divided into units (stages) that can be processed in one machine cycle, and intermediate results of each stage are not retained, so they are processed sequentially in each machine cycle. A pipeline method is used to advance the process, and data processing results are obtained at each machine cycle.

However, as the series of processing becomes more complex, it becomes necessary to insert more information into the process (the number of registers increases,
The amount of hardware increases more than necessary. Even if the machine cycle is set small to speed up processing, the number of pipe stages will increase, resulting in a similar result.

Furthermore, parity prediction and residue module are used to check whether the above data processing function is operating normally.

There are three methods, such as comparing the results by duplication, but whichever method is adopted, there is a drawback that, in addition to the circuit for the data processing function described above, hardware for function checking is required.

In the conventional pipeline method, when data is continuously supplied every machine cycle and operations are executed, each stage of the pipeline is used without wastage and the hardware is fully utilized, but when data is (If there is a machine cycle, a gap will occur in the data flow,
There is a stage where processing is not executed, and the disadvantage is that the hardware cannot be used effectively.

OBJECT OF THE INVENTION An object of the present invention is to provide an arithmetic processing device that enables continuous use of the arithmetic unit and also allows checking of arithmetic functions. A storage means for storing data, a plurality of data holding means for holding data read out from the storage means, and a plurality of data holding means for storing data held in the data holding means in one-to-one correspondence with each of these data holding means. Computing means includes the same number of computing units as the data holding means, which perform machine cycle processing.

a selection means for selecting a target operation result from the operation results of the plurality of arithmetic units; a comparison means for extracting a plurality of appropriate outputs from the plurality of operation results and checking whether they are the same; In the case of a process in which a continuous dance is performed, the plurality of arithmetic units are switched to 11th order and used, and when the arithmetic means are not used continuously, the vacant one of the plurality of arithmetic units is used. (-) control means for controlling each of the means to execute the same calculation in parallel using arithmetic units, and to compare and check the results with the comparison means;

Examples of the invention Next, the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention is an arithmetic unit having two systems of arithmetic circuits that complete one operation in two machine cycles, and a group of registers that can be read and written at any time. 11° There are two registers 12a and 12b that hold data from this register group 11 for a necessary time, in one-to-l correspondence with each of these registers 12a and 12b, and the data held in the registers is Arithmetic circuit 13 that processes over machine cycles
a and 13b, parity generation circuits 14a and 14b that correspond to each of these arithmetic circuits 13a and 13b in a one-to-l ratio and generate parity from the output of each arithmetic circuit, and select one from the two sets of arithmetic output and parity. Selection circuit 15. A data holding register 16 that temporarily holds the selected data until it is stored in an arbitrary one of the two V reflex groups 11. A comparator 17 that compares the parities generated by each of the parity generation circuits 14a and 14b corresponding to the two sets of arithmetic circuits 13a and 13b. A register 18 that can sample the comparison result of the comparator 17 at any time. At least each of the circuits 12al12b,
15, 16, and 18.

Next, the operation of the present invention will be explained using FIGS. 1, 2, and 3.

First, a case will be described in which the arithmetic unit is not used continuously.

In FIG. 2, when the operation η-I0 is activated at time T0, the registers 12a and 12b and the arithmetic circuits 13a and 13b in FIG. 12b, and calculations are executed independently in calculation circuits 13a and 13b. The result is held in the register 16 via the selection circuit P815, and the parity generation circuit 14
In a and 14b, respective parities are generated from each of the previous n12 operation results. The parity is compared and checked by the comparator 17, and the result is taken into the register 18.

Since it takes two machine cycles from the start of the operation until the check result is fetched, as shown in Figure 2, if there is a gap of one or more instructions between the instructions that use the above operation unit, It is possible to check the functionality of arithmetic circuits by using duplicate hardware.

Next, a case where instructions using the above-mentioned arithmetic unit are consecutive will be explained.

Machine cycle ゛J゛. When the operation I0 is activated, the necessary operand O0 is read from the register group 11 to the registers 12a and 12b, and the processing is started by the operation 11 circuits 13a and 13b. When operation 11 using the same operation unit is started in the next machine cycle T, both operation circuits 13a and 13b perform operations l. As a result, one of the processes (for example, Enji Kai 13b) is canceled and the corresponding operand θ is taken into the register 12b.Enshi Kai wJ1
The process starts at 6. Furthermore, the next machine cycle T! At the end of is operation I. processing is completed.

The selection circuit 15 selects the outputs of the performance circuit 13a and the parity generation circuit 14a. At the same time as the selection result is loaded into the data holding register 16 in the machine cycle T, the arithmetic circuit 13a is opened, so the operand O! for the operation 12 activated in the machine cycle T! are stored in the register 12a and processing is started in the arithmetic circuit 13a1.In this case, the parity comparison circuit is input with completely different parities of data, so Since W1 is insignificant, the register 18 is not strobed.

In the next machine cycle T4, the data held in the register 16 in the previous cycle 1° is transferred to the target register in the register group 11, and at the same time, at the end of the same cycle, the data is output from the arithmetic circuit 13b and the parity generation circuit 14b. The processed results are stored in the empty V raster 16.

A new operation 27do03 is loaded into register 12bK,
Processing is started in the performance circuit 13b.

Similarly, as shown in FIG. 3, the two systems of arithmetic circuits are used alternately, so that data is supplied every machine cycle and processing results can be obtained.

In the present invention, the amount of incidental hardware is reduced by eliminating the flip-flops that hold data at each stage, which were inserted in the middle of the arithmetic circuit in the conventional pipeline system. Therefore, it is not possible to process data continuously using only the arithmetic circuit system, so continuous data processing is possible by preparing multiple systems of arithmetic circuits and using them while switching between each machine cycle. There is.

Furthermore, in the present invention, if the arithmetic circuits placed in parallel are vacant, it is also possible to check the functionality of the arithmetic circuits by executing the same operations in parallel and comparing them in some way to see if the results are the same. I have to. In the comparison check method of this embodiment, parity pits are compared, but the check method is not used.

In this way, the present invention reduces the amount of hardware that is essentially unrelated to arithmetic operations, multiplexes the arithmetic circuits, and sequentially switches them for use, thereby making it possible to perform arithmetic operations in every machine cycle, while at the same time eliminating the need for empty circuits. - In some cases, these circuits can be used simultaneously to improve the reliability of the device.

Effects of the Invention The present invention includes a process that enables continuous use of the unit by providing a plurality of identical arithmetic circuits in the arithmetic unit, and also uses the arithmetic circuit when the arithmetic circuit is vacant. If hardware resources can be used flexibly and effectively according to the processing, such as executing the same operation in parallel and comparing the results, it is possible to check the functionality.
・It has 5 effects.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a time chart for explaining the operation in the embodiment shown in FIG. 1 when instructions using operation unit are not consecutive. FIG. 3 is a time chart for explaining the operation of the embodiment shown in FIG. 1 when instructions using the arithmetic unit are consecutive. 1 to 3, 11... register group, 12a, 12b... read data holding register % 13a t 13b... - performance circuit, 1
4a, 14b... Parity generation circuit, 15...
... Selection circuit, 16 ... Write data holding register, 17 ... Comparison circuit, 18 ...
... Comparison result holding register, 19... Control circuit. TaTr Tt Ts Tl Mashi, / Cycle III 1- It :W '4 k motion → ← ←→ LS'X'7fd 0a θl θshi θshimushijinyu 2b 74 Tv Tt 10,000 T4 Mashi; Reik! Shi5 Tora calculation power ←l and→−lヱ→−L−nerθ−←J]
1-θa 1) 1p L raster 12a L7-9i2b ----0, -12--11Zrj
jJ road ysa, ” 1←-θl θJ skin fungus mouth road 13b ----- Aa At /it /7s Shijista 16 Live 3 Figure

Claims (1)

[Scope of Claims] A storage means for storing data, a plurality of data holding means for holding data read from the storage means, and a plurality of data holding means corresponding to each of these data holding means on a one-to-l basis, the data holding means a calculation means having the same number of calculation units as the data holding means for processing the retained data of in a plurality of machine cycles; a selection unit for selecting a target calculation result from the calculation results of the plurality of calculation units; a comparison means for extracting a plurality of appropriate outputs and checking whether they are the same; and a comparison means for taking out a plurality of appropriate outputs and checking whether or not they are the same; and when the arithmetic means is not used continuously,
It is characterized by including a control means for controlling each of the means to perform the same calculation in parallel using a vacant arithmetic unit among the plurality of arithmetic units, and to compare and check the results with the comparison means. An arithmetic processing unit.