JPH0527949A - Exponential part arithmetic circuit for floating point multiplication - Google Patents

Abstract

PURPOSE:To reduce the subtracter of 13 bits, to reduce circuit scale and to shorten delay time concerning the exponential part calculating circuit for a floating point multiplying circuit which is related to the floating point multiplying circuit in an IEEE type and can be used especially while switching single- precision multiplication and double-precision multiplication. CONSTITUTION:Single-precision and double-precision conversion parts CNV1 and CNV3 convert data to the double-precision exponental data of 11 bits by adding the four bits of a first bit as the most significant bit of single-precision exponental data having the width of 8 bits and 2nd to 4th bits as the inverse of the most significant bit to the low-order 7 bits of the single-precision exponental data. The exponent data expressed with the double-precision of 11 bits are added and outputted by a 13-bit adder ADD1 as the 13-bit data of the sum +1 of the exponental part according to a carry input and since '111' is added to the high-order 3 bits by a 3-bit adder, a fixed bias value is subtracted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IEEE format floating point multiplication circuit, and more particularly to an exponent part arithmetic circuit of a floating point multiplication circuit which can be used by switching between single precision multiplication and double precision multiplication.

In the IEEE system, exponents in the range from negative to positive can be represented by positive integers, so that single precision is 12
7. For double precision, a displacement index is used that shifts the index toward the + side by the bias value of 1023.

[0003]

2. Description of the Related Art Conventionally, floating-point display data processing has been widely used. However, depending on the floating-point data representation, the bit width of the exponent part may differ depending on the precision. It is necessary to handle the exponent part of. FIG. 3 shows an IEEE format floating point display format to which the present invention is applied. This includes double-precision floating point (a) and 32
There is a single precision floating point (b) expressed in bits. In each of these, S is a positive / negative sign part, E is an exponent part, and F is a mantissa part. The data expressed in this way expresses the numerical values shown on the lower side. The exponent part E is defined to have an 8-bit width in single precision and an 11-bit width in double precision.

The processing of the exponent part in the multiplication of floating point numbers is the addition of two operands x and y. Actually, a predetermined bias value B is added to the exponent value which is an integer in the positive and negative ranges, and the exponent part of the floating point data is displaced so as to be a positive number.

Therefore, as the value E of the exponent part, E = e + B obtained by adding the constant B to the exponent e of the actual numerical value is used, and the addition of the two operands x and y is X = biased. Using x + B and Y = y + B, (x + y) + B =
It is performed as X + Y-B, and it is necessary to efficiently perform the addition of the two operands and the subtraction of the constant B.

In the IEEE standard, the bias value B is
In the double precision floating point, 1023 (= 2 ¹⁰ -1) is specified, and in the single precision floating point, 127 (= 2 ⁷ -1) is specified.
FIG. 4 is a diagram of a conventional exponent arithmetic circuit. SEL
1 and SEL2 are selectors provided for the multiplier X and the multiplicand Y, respectively, and select single precision or double precision by the precision selection signal SXD. ADD includes addition of double precision 11 bits and carry and sign. This is a 13-bit wide adder for enabling the lower 11 bits in the case of single precision. The SUB is a 13-bit subtractor, and the output of the ADD and the bias value 1023 (double precision) or 127 (single precision) selected according to the precision by the SEL3 are input to perform the subtraction of the bias value.

As the subtractor, an adder ADD is used.
A 13-bit subtractor was used because the input from was 13 bits.

[0008]

In the above-mentioned conventional exponential part arithmetic circuit, since the 13-bit subtractor is used for subtracting the bias value, the circuit scale of the subtractor becomes large and the delay becomes large and high-speed arithmetic is possible. There was a problem of difficulty.

The present invention has been made in view of the above problems, and it is an object of the present invention to reduce the circuit scale and delay time by reducing the 13-bit subtractor.

[0010]

FIG. 1 is a block diagram of an exponential part arithmetic circuit of the present invention. As shown in FIG. 1, the above problem is caused by an exponent part arithmetic circuit in a multiplication circuit for performing multiplication of single precision floating point numbers having an exponent part of 8 bit width or double precision floating point numbers having exponent part of 11 bit width. There is 8
The most significant bit of the single-precision exponent data having a bit width is set as the first bit, and the inversion of the most significant bit is made the second, third, and fourth bits, and 4 bits are added to the lower 7 bits of the single-precision exponent data. Single-precision double-precision conversion units CNV1 and CNV2 for converting into 11-bit double-precision exponent data, and input double-precision exponent data and the single-precision double-precision conversion units CNV1 and C
Two sets of selectors SEL1 and SEL2 that select the output of NV2 based on the precision selection signal SXD are provided corresponding to the multiplier and the multiplicand, and the two sets of selectors SEL1 and SEL2 are provided.
13-bit adder ADD1 for calculating the sum +1 of the exponents by adding the outputs of
"11" is added to the upper 3 bits of the output of the 3-bit adder ADD1.
1 "and a 3-bit adder ADD2
The lower 10 bits of the output of the bit adder ADD1 and the above 3
This is solved by the exponent arithmetic circuit in the floating point multiplication of the present invention, which outputs 13 bits with the output of the bit adder ADD2 as the exponent arithmetic result.

[0011]

In the case of single precision multiplication, the 8-bit exponent part of the multiplier and multiplicand is converted to double precision through the single precision double precision conversion part and represented by 11 bits as in the double precision operation. By adding this, the bias value to be subtracted from the addition result is fixed to 1023 for both single precision and double precision operations. This conversion unit divides the value of the higher-order 1 bit into the 11th bit as it is, and divides it into 3 through the inverter for 10 to 8 bits.
Since it is the bit, it can be realized with a simple circuit configuration.

The carry signal input to the adder causes the output of the adder to be the sum of the exponents + 1, so that the bias value + 1 = 1024 may be subtracted. By the way-
1024 is “11100” when expressed in binary 13 bits.
Since the lower 10 bits are all "0", the subtraction of -1024 can be realized only by adding the upper 3 bits to the output of the adder.

Therefore, the bias value can be subtracted by the 3-bit adder instead of the 13-bit subtractor in the prior art, which reduces the circuit scale and the operation delay.

[0014]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram of an exponential part arithmetic circuit of the present invention, and FIG. 2 is a block diagram of a single-precision double-precision converter.

In FIG. 1, CNV1 and CNV2 are single-precision double-precision converters, and 8-bit single-precision exponent data to which a single-precision bias value 127 is added is added to a double-precision bias value 1023. Convert to double-precision exponential data of bits.

The structure and operation of the single-precision / double-precision converter will be described with reference to FIG. The conversion from single precision to double precision means increasing the bias value of data from 127 to 1023, and it is necessary to add the increment of bias value 1023−127 = 896 to 8-bit data. In binary representation, 896 has a 10-bit width of "1110000000", and the lower 7 bits are "0" and the upper 3 bits are "1".

Therefore, in the addition result of 896, the result obtained by adding 111 to the most significant 1 bit of the 8-bit input is set as the upper 4 bits and added to the lower 7 bits of the 8-bit input.
It is 1 bit. When the most significant bit is "1", the addition result is "1000", and when it is "0", it is "0111". The above operation is performed with the value E of the most significant bit of the 8-bit input.
₇ is a first bit and inverting the second E ₇ via the inverter, a third, a 4-bit to the fourth bit, in addition to lower 7 bits E ₀ to E ₆ the input is output as it It can be realized by the circuit of FIG.

In FIG. 1, 8-bit single precision exponent data X30-23, Y30- input as a multiplier X and a multiplicand Y.
Reference numeral 23 is passed through a single-precision double-precision conversion circuit as 11-bit double-precision representation exponent data, and 11-bit double-precision exponent data X62 to 52 and Y62 to 52 are input to selectors SEL1 and SEL2, respectively.

The selectors SEL1 and SEL2 are controlled by the precision selection signal SXD to switch between the single precision input and the double precision input and input the output to the adder ADD1. Adder ADD1
Is a 13-bit wide adder that adds the 11-bit exponent part of the input multiplier and multiplicand.
"1" is input to, and the value obtained by adding 1 to the sum of the exponents of the multiplier and the multiplicand is output in 13 bits.

The adder ADD2 has a width of 3 bits, and the adder A
"111" is added to the upper 3 bits of the 13 bits of the addition result output by DD1. 13-bit adder AD
D1 and the 3-bit adder ADD2 perform a process of subtracting the double precision bias value 1023 from the addition result of the exponent data to obtain the double precision expression of the exponent data. That is, the exponent of the multiplier + the exponent of the multiplicand-1023 = the exponent of the multiplier + the exponent of the multiplicand + 1-1024, and −1024 is 2 ¹³ −1024.
= 7168 = 1 * 2 ¹² + 1 * 2 ¹¹ + 1 * 2 ¹⁰ , the ADD1 outputs the 13-bit operation result (= multiplier exponent + multiplicand exponent + 1) with the ADD in the upper 3 bits.
This is because 2 corresponds to adding "111".

The output of the 3-bit adder ADD2 is set to the upper 3 bits, and the lower 1 of the 13-bit adder ADD1 is set.
13-bit exponent data in which 0 bit is the lower 10 bits is output as the exponent operation result.

[0022]

As described above, according to the present invention, the bias value is fixed to 1023 which is common to the double precision even in the single precision operation by the single precision / double precision conversion. Can be used as a substitute, and the circuit scale of the arithmetic circuit can be reduced, and the delay time can be shortened.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an exponential part arithmetic circuit of the present invention.

FIG. 2 is a block diagram of a single-precision double-precision conversion unit.

[Fig. 3] Floating-point display format according to the IEEE standard

FIG. 4 is a diagram of a conventional exponent arithmetic circuit.

[Explanation of symbols]

CNV1, CNV2-single-precision double-precision conversion unit, SEL1,
SEL2-selector, ADD1- 13-bit adder, A
DD2-3 bit adder

Claims (1)

Claims: What is claimed is: 1. An exponent arithmetic circuit in a multiplication circuit for performing multiplication of single precision floating point numbers having exponents of 8 bits width or double precision floating point numbers having exponents of 11 bits width. Then, the most significant bit of the 8-bit width single precision exponent data is the first bit, and the inversion of the most significant bit is the second, third, and fourth bits, and the four bits are the lower 7 bits of the single precision exponent data. Single-precision double-precision conversion unit (CNV1, CNV2) that adds to bits and converts to double-precision exponent data of 11-bit width, input double-precision exponent data and output of the single-precision double-precision conversion unit (CNV1, CNV2) Precision selection signal SXD
Selector based on (SEL1, SEL2)
And 2 are provided corresponding to the multiplier and the multiplicand, and the outputs of the selectors (SEL1, SEL2) of the two sets are added and a carry input is added to obtain the sum +1 of the exponent part (ADD1). ) And a 3-bit adder (ADD2) that adds “111” to the upper 3 bits of the output of the 13-bit adder (ADD1), and the lower 10 bits of the output of the 13-bit adder (ADD1) An exponent arithmetic circuit in floating-point multiplication according to the present invention, which outputs 13 bits from the output of the 3-bit adder (ADD2) as an exponent arithmetic result.