JPS6359170B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to a floating point multiplication device, particularly to a floating point multiplication device that performs high-speed calculations on the exponent part in floating point multiplication conforming to the IEEE standard format, and quickly obtains overflow and underflow detection signals. The present invention relates to a floating point multiplication device.

Conventional configuration and its problems In the exponent operation of a floating-point multiplier,
Generally, the exponent parts are added, and then the addition is performed again after the shift signal for normalization generated by the mantissa part calculation arrives, and then overflow and underflow detection is performed.

The exponent part arithmetic unit of a conventional floating point multiplication device will be explained below with reference to FIG. In Figure 1, 1 is the exponent part of the multiplier E _X and the exponent part E _Y of the multiplicand.
2 is the mantissa part of the multiplier
+1 addition signal line for normalizing the exponent part generated by multiplying M _X by the mantissa part My of the multiplicand;
3 is a +1 adder that adds +1 or +0 to the output of exponent adder 1 according to the signal on +1 addition signal line 2, and 4 is an overflow of the multiplication result by comparing the output of +1 adder 3 with a predetermined value. Alternatively, it is a detector for detecting an underflow, and 5 and 6 are an underflow detection signal line and an overflow detection signal line output from the detector 4, respectively. A conventional exponent part calculation unit as shown in Fig. 1 performs addition of Ex and Ey, and then waits for the arrival of a +1 addition signal for normalization obtained by mantissa part calculation to complete the exponent part calculation. . Detection of overflow and underflow is performed after the exponent part calculation is completely completed. In general, in floating-point multiplication, the exponent operation is performed after the mantissa operation is completed, so
By shortening the exponent calculation time, the entire multiplication time can be shortened.

However, in the above example, after the exponent normalized signal (corresponding to the +1 addition signal) arrives, +1
Since addition is performed and overflow and underflow detection is performed using this output, a relatively long time is required from the end of the mantissa operation to obtaining the full multiplication result, which is difficult to perform in high-speed floating point multiplication. I didn't like it.

Purpose of the Invention In view of these conventional problems, the present invention provides a floating method that can minimize the time required from the arrival of an exponent normalized signal obtained by mantissa calculation to the end of exponent processing. The purpose is to provide a decimal point multiplication device.

Structure of the Invention The present invention provides a first sum of an exponent part of a multiplier, an exponent part of a multiplicand, and a predetermined constant, a second sum obtained by adding 1 to this sum, and a specific value of the two sums. By preparing a detection signal for detecting the exponent part, the exponent part calculation result can be obtained immediately after the exponent part normalized signal arrives.

DESCRIPTION OF EMBODIMENTS FIG. 2 shows the configuration of an exponent unit of a multiplier that performs floating point multiplication based on the IEEE standard format in an embodiment of the present invention. It is assumed that the exponent part has a data width of 8 bits. In Figure 2, 11 is the exponent part Ex of the multiplier, the exponent part Ey of the multiplicand, and 16
A 10-bit width adder that adds 81 (hereinafter referred to as _81H ) in base notation, 12 is a 10-bit width adder that adds 1 to the output of adder 11, and 13 is the exponent part normalized as a result of mantissa multiplication. The signal line 14, which becomes a high logic level (hereinafter abbreviated as "H") when necessary, is set when the signal line 13 is at a low logic level (hereinafter abbreviated as "L") and the output of the adder 11 is _100H or the upper 2 bit is 00
an underflow detector that outputs an underflow detection signal to the signal line 16 when 15 is the adder 1;
The most significant bit of 2 is 1, or the signal line 13 is “H” and the lower 9 bits of the adder are 1FF _H
16 is an underflow detection signal line, 17 is an overflow detection signal line, and 18 is an output of the adder 12 when the signal line 13 is "H". This is a selector that outputs the output of the adder 11 when is "L".

Single-precision floating point data in the IEEE standard format has the following format: (-1) ^S・2 ^E-127・(1・F) ……(1). In this formula, S is the sign bit, E is 8-bit exponent data shifted in the positive direction by 127 (7F _H ), F is 23-bit mantissa data, and overflow is 128≦( E-127) ...(2) Underflow is defined as a range of (E-127)≦-127 ...(3). Here, the multiplier X and the multiplicand ^{Y are as} follows ^: ...(5) Then, the multiplication result P is expressed as the following equation.

P=X・Y = (-1) ^Sx+Sy・2 ^{(Ex+Ey-127)-127}・(1・Fx)・
(1.Fy) = (-1) ^S P.2 ^EP-127 .(1.F _P )...(6) Equation (6) represents exclusive OR. Since the mantissa (1・F) is in the range of 1≦(1・F)<2, the product of the mantissas of X and Y is in the range of 1≦(1・Fx)・(1・Fy)<4 2 In the range ≦(1・Fx)・(1・Fy)<4, it is necessary to perform normalization and add 1 to the exponent part. A signal line 13 is a signal line that propagates this signal. On the other hand, E _P is calculated in the adder 11 by representing -127 as a complement and adding 129 (81 _H ) to Ex+Ey. Depending on the result of the multiplication of the mantissas, it is necessary to further add 1 as described above, and this result is obtained in the adder 12. The calculation result of the exponent part is outputted from the adder 12 when the signal on the signal line 13 is "H", and from the adder 11 via the selector 18 when it is "L".

From equations (2) and (6), the overflow is in the range E _P ≧128 + 2.127 + 129 = 511 (1FF _H ) ... (7). That is, if _EP is a number with a width of 10 bits, an overflow will occur if _EP is _1FFH or the most significant bit of _EP is 1. This is equivalent to the following two items a and b: (a) When the signal on the signal line 13 is “L”, the adder 12
output is 512 (200 _H ) or more. That is, adder 12
The most significant bit of the output is 1.

(b) Adder 12 when the signal on signal line 13 is “H”
output is 511 (1FF _H ) or more. That is, adder 1
The most significant bit of the output of 2 is 1, or the lower 9 bits are _1FFH .

It is detected by the detector 15.

From equations (3) and (6), the underflow is in the range E _P ≦-127 + 2.127 + 129 = 256 (100 _H ). That is, if E _P is 100 _H or the upper two bits of E _P are 00, an underflow will occur.
This is equivalent to the following two items (c) and (d). (c) When the signal on the signal line 13 is “H”, the adder 11
output is 255 (FF _H ) or less. That is, adder 11
The upper two bits of the output are 00.

(d) Adder 11 when the signal on signal line 14 is “L”
The output is 256 (100 _H ) or less. That is, adder 11
output is _100H or the upper 2 bits are
00.

It is detected by the detector 14. The detector 14 and the detector 15 can be realized, for example, by a logic circuit as shown in FIG.

As described above, according to this embodiment, the adder 11 and the adder 12 are each provided with a width of 10 bits, and the signals of the upper two bits of each are effectively utilized.
Exponent data, overflow, and underflow can be detected immediately after the normalization signal arrives.

Note that in this example, the predetermined constant for multiplication in the IEEE standard format is _81H ;
It is clear that a configuration similar to this embodiment can be realized by defining a predetermined constant for multiplication of a format other than the format.

In addition, in this example, two sum outputs are obtained by the adder and incrementer that add Ex, Ey, and 81 _H , but the adder and decrementer that add ExEy and 82 _H are used to obtain two sum outputs. It is clear that it is possible to obtain two summed outputs that are identical even when

Effects of the Invention As described above, the present invention provides two outputs that can be the solution of the exponent part of the multiplication result in a floating-point multiplication device, and provides a detector for detecting a specific value for each output. An improved floating point multiplier can be realized which can obtain the exponential part output and the overflow and underflow detection signals quickly after the arrival of the resulting normalized signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional exponent part calculator, and FIG. 2 is a block diagram of an exponent part calculator in an embodiment of the present invention. 11, 12... Adder, 13... Normalization signal line, 14... Underflow detector, 15... Overflow detector.

Claims (1)

[Claims] 1 n-bit length exponent part of the multiplier and n bits of the multiplicand
A first sum of n+2 bits, which is the sum of the exponent part of the multiplier, the exponent part of the multiplicand, and a predetermined constant, and an a first means for outputting a second sum; and the first means for outputting a second sum is 00, or the most significant bit of the multiplication result of the mantissa part of the multiplier and the multiplicand is 0. a first detector that generates an underflow detection signal when the upper two bits of the first sum output are 01 and the lower n bits are all 0; and multiplication of the multiplier and the mantissa part of the multiplicand. Generates an overflow detection signal when the most significant bit of the result is 1 and the lower n+1 bits of the second sum output are all 1, or when the most significant bit of the second sum output is 1. and a second detector that calculates the lower n of the first sum output when the most significant bit of the multiplication result of the mantissa part of the multiplier and the multiplicand is 0.
1. A floating point multiplication device comprising: a selector that outputs the lower n bits of the second sum output as the result of the exponent part when the bit is 1. 2. The floating point multiplication device according to claim 1, wherein the first means comprises an adder and an incrementer that receives the output of the adder as input. 3. The floating-point multiplication device according to claim 1, wherein the first means comprises an adder and a decrementer whose input is the output of the adder. 4. The floating point multiplication device according to claim 2 or 3, wherein the predetermined constant is (2 ^n-1 +1).