JP2556171B2 - Arithmetic circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic circuit for performing arithmetic processing such as addition and multiplication in a redundant binary format, and particularly to an arithmetic circuit suitable for integration into an integrated circuit.

[Prior Art] Conventionally, in order to improve the calculation processing speed, the normal 2
An arithmetic circuit for converting a binary expression into data of a redundant binary expression and performing an arithmetic process is known (for example, "a high-speed multiplier for VLSI using a redundant binary addition tree" Takagi et al., IEICE Transactions ( D), J66-D6, pp.683-690, June 1983).

In the redundant binary representation, 1-bit data is represented by three values of 0, 1 and -1, whereby an adder circuit without carry propagation can be realized. For example, bit data [-
1] is represented as [], for example, 6-bit 2
In the case of a decimal number, the most significant bit is the sign bit, so the maximum value is 0111112 ₂ (63 ₁₀ ) and the minimum value is 100000 ₂ (-
64 ₁₀ ), but in the redundant binary representation, the maximum value is [11111
1] ₂ (127 ₁₀ ), minimum value is _[2] (-127 ₁₀ )
Becomes Here, the subscript 2 indicates a binary number, 10 indicates a decimal number, and [2] indicates a redundant binary number expression.
In the redundant binary representation, one numerical value can be represented by several kinds of data. For example, if 5 ₁₀ is represented by a 4-digit redundant binary number, 0101 _[2] , 011 _[2] , 10 _[2] , 101
_There are five possible expressions, _[2] and 11 _[2] .

When adding redundant binary numbers, 0 _[2] and 0 _[2] and 1
_[2] and not carry the addition of _[2], 1 _[2] and 1 performs a carry of 1 _[2] is the addition of _[2], the addition of _[2] and _{[2]
Carry [2]} , carry 1 _[2] and 0 _[2] , and carry 1 _[2] if there is a carry of 1 _[2] from the bottom, _[2]
And 0 _[2] addition, if there is a carry of _[2] from the bottom
_{Carry [2]} . Therefore, for example, when adding 1 ₁₀ +1 ₁₀ , adding 1 01 _[2] +01 _[2]
By adding _[2] +01 _[2] , it is possible to perform addition without carry propagation. If there is no carry propagation, then a carry of one digit will always be absorbed by its upper digit. Therefore, in this case, the addition process is performed in two steps by the procedure of obtaining the intermediate sum of each digit and the carry signal in the first step and obtaining the sum of the intermediate sum and the carry signal from the lower order in the second step. finish. Therefore, it is possible to significantly reduce the operation processing time as compared with the normal binary operation in which the carry signal propagates by 2 bits or more.

Conversion from a redundant binary number to a binary number is performed by normal subtraction of a binary number that collects only the digits with 1 _[2] and a binary number that collects only the digits with _[2]. You can

[Problems to be Solved by the Invention] However, in the above-described conventional arithmetic circuit, when the most significant bits of the addend and the augend are 1 _[2] and 1 _[2] , or
_{In the case of [2]} and _[2] , a carry always occurs, so even if the overflow does not actually occur, it may be erroneously determined that an overflow has occurred.

For example, 11111 _[2] (-1 ₁₀ ) and 11111 _[2] (-1 ₁₀ )
The calculation with and is as follows.

In this case, (−1 ₁₀ ) + (− 1 ₁₀ ) = (− 2 ₁₀ ), so that the carry signal is output from the most significant bit even though the overflow does not actually occur. It will be judged.

Therefore, in order to prevent this, the number of bits of the redundant binary adder circuit and the circuit for converting the redundant binary number to the binary number is extended to the upper side to provide a protection bit.
In this case, there are problems that the circuit scale increases and the calculation speed decreases. In particular, if a protection bit is provided in each of a large number of adder circuits that form an integrated multiplier, an increase in circuit scale and a decrease in operation speed will not be negligible.

The present invention has been made in view of the above problems, and it is possible to improve the calculation accuracy by detecting the occurrence of a true overflow without increasing the circuit scale and decreasing the calculation speed. The purpose is to provide a circuit.

[Means for Solving the Problems] An arithmetic circuit according to the present invention includes: a redundant binary arithmetic circuit for performing arithmetic operation on redundant binary format data and outputting a redundant binary format arithmetic result and a carry signal; A redundant binary / binary conversion circuit for converting the operation result in the redundant binary format output from this redundant binary operation circuit into binary data, and the carry signal and the highest rank of the operation result in the redundant binary format. An overflow detection circuit for detecting an overflow in the redundant binary operation circuit by referring to a bit and a sign bit of the operation result converted into the binary data.

[Operation] According to the present invention, not only the carry signal of the operation result, but also the carry signal, the most significant bit of the operation result in the redundant binary format, and the sign bit of the operation result converted into binary data. By referring to and, it is possible to accurately determine whether or not the operation result has truly overflowed.

Therefore, according to the present invention, overflow can be detected without expanding the number of bits of the redundant binary operation circuit and the redundant binary / binary conversion circuit, and the circuit scale can be reduced and the operation speed can be improved. Can be achieved.

Embodiments Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of the adder circuit according to the first embodiment of the present invention.

Addend data x and addend data y to be added are
The data is input to the redundant binary adder 1 in a data format represented by redundant binary numbers. The redundant binary adder 1 adds both data x and y and outputs the addition result z and the carry signal C in the redundant binary number representation. The addition result z is the redundant binary / binary conversion circuit 2
Has been entered in. The redundant binary / binary conversion circuit 2 converts the addition result z into a binary expression addition result zz and outputs it. The addition result zz is input to one input terminal of the 3-input selection circuit 3.

On the other hand, the carry signal C output from the redundant binary adder 1
And the most significant bit z _MSB of the addition result z, and redundant binary /
The sign bit zz _sign, which is the most significant bit of the addition result zz output from the binary conversion circuit 2, is input to the overflow detection circuit 4. The overflow detection circuit 4
The presence or absence of overflow is determined based on these data, and overflow detection information OF is output. This information OF
Is composed of a signal indicating the presence or absence of overflow and a signal indicating its sign, and is supplied to the selection circuit 3 as its selection control signal. The maximum value data zz _MAX from the maximum value output circuit 5 and the minimum value data zz _MIN from the minimum value output circuit 6 are input to the remaining two input terminals of the selection circuit 3, respectively. The selection circuit 3 selects these input data based on the overflow information OF, and outputs the selected data as the addition result s.

Next, the overflow detection circuit 4 will be described in more detail.

The overflow detection circuit 4 basically has the following first
As shown in the table, carry signal C, most significant bit z of operation result z
_{Based on the MSB} and the sign bit zz _sign of the operation result zz,
Output overflow information OF.

Here, in the redundant binary representation, since three values of (, 0,1) are taken, the sign bit (SB) and the value bit (V
It is represented by 2 bits of B). The overflow detection information OF is composed of the overflow detection signal OD and the positive / negative determination signal OS. Therefore, the actual truth table of the overflow detection circuit 4 is as shown in Table 2 below.

Next, the operation of the adder circuit thus configured will be described.

Now, assume that the following augend data x and augend data y are input to the redundant binary adder 1.

x = 0111 1 _[2] (11 ₁₀ ) y = 1000 _[2] (20 ₁₀ ) The redundant binary adder 1 performs the following operation.

As a result, the addition result z = 0001 _[2] is obtained.

Next, the redundant binary / binary conversion circuit 2 performs the following subtraction.

As a result, a binary expression addition result zz = 0111111 ₂ is obtained.

In this case, the overflow detection circuit 4, C = 01 _2,
Since z _MSB = 11 ₂ and zz _sign = 0 ₂ are input, the overflow detection signal OD = 0 and the positive / negative determination signal OS = 0. That is, in this case, no overflow occurs, and the selection circuit 3 selects the addition result zz output from the redundant binary / binary conversion circuit 2 and outputs it as the addition result s.

Next, a case where the following augend data x and augend data y are input to the redundant binary adder 1 will be described.

x = 0111 _[2] (11 ₁₀ ) y = _{10 10 [2]} (22 ₁₀ ) The redundant binary adder 1 performs the following operation.

As a result, the addition result z = 000001 _[2] is obtained.

Next, the redundant binary / binary conversion circuit 2 performs the following subtraction.

As a result, the binary addition result zz = 100001 ₂ is obtained.

In this case, the overflow detection circuit 4, C = 01 _2,
Since z _MSB = 11 ₂ and zz _sign = 1 ₂ are input, the overflow detection signal OD = 1 and the positive / negative determination signal OS = 0. That is, in this case, a positive overflow has occurred, and the selection circuit 3 selects the maximum value zz _MAX output from the maximum value output circuit 5, and outputs this as the addition result s.

Similarly, when a negative overflow occurs, the selection circuit 2 outputs the minimum value zz output from the minimum value output circuit 6.
_MIN is selected and this is output as the addition result s.

As a result, when overflow occurs, the limited addition result s is output.

As described above, according to the adder circuit of the present embodiment, the overflow can be correctly detected by the carry signal C, the most significant bit z _MSB of the addition result z, and the sign bit zz _sign of the addition result zz. In the binary adder 1 and the redundant binary / binary conversion circuit 2, it is not necessary to provide a protection bit or the like, and it is possible to reduce the lower scale and improve the operation speed.

FIG. 2 is a block diagram showing the configuration of the multiplication circuit according to the second embodiment of the present invention.

In FIG. 2, the same parts as those of the circuit of FIG. 1 are designated by the same reference numerals, and the description of the overlapping parts will be omitted.

In the circuit of this embodiment, the redundant binary adder 1 in FIG. 1 is replaced with a redundant binary multiplier 11.

That is, the multiplicand data a and the multiplier data b are input to the redundant binary multiplier 11 where they are multiplied. The redundant binary multiplier 11 is composed of a large number of redundant binary adders that add a large number of partial products. The multiplication result m by the multiplier 11 is input to the redundant binary / binary conversion circuit 2 and converted into a binary number. The multiplication result mm converted into a binary number is input to one input terminal of the 3-input selection circuit 3.

On the other hand, the carry signal C from the adder at the final stage of the redundant binary multiplier 11, the most significant bit m _MSB of the multiplication result m and the sign bit mm _sign of the multiplication result mm are input to the overflow detection circuit 4, where An overflow is detected at. The overflow information OF is supplied to the selection circuit 3 as a selection control signal. The selection circuit 3 selects one of the multiplication result mm, the maximum value mm _MAX from the maximum value output circuit 15 and the minimum value mm _MIN from the minimum value output circuit 16 according to the overflow information OF, and outputs it as the multiplication result M.

In the addition using the redundant binary number, since the propagation of the carry signal can be suppressed to one digit as described above, the effect is particularly great when applied to a multiplication circuit that adds a large number of partial products. However, since the multiplication circuit repeats redundant binary number additions many times, the necessity of overflow determination is greater than that of a normal addition circuit. In this respect, according to the present embodiment, since the overflow can be detected correctly, a high-speed and accurate multiplication circuit can be provided.

Further, according to the multiplication circuit of this embodiment, the overflow determination of the addition result of each stage is not performed, but the overflow determination is performed only by referring to the addition result of the final stage. It can be further increased.

[Effects of the Invention] As described above, according to the present invention, not only the carry signal of the operation result but also the most significant bit of the operation result and the sign bit of the operation result converted into binary data are referred to. ,
Since the overflow of the calculation result is determined,
It is not necessary to expand the number of bits of the arithmetic circuit and the redundant binary / binary conversion circuit. Therefore, it is possible to improve the calculation accuracy while reducing the circuit scale and the calculation speed.

[Brief description of drawings]

FIG. 1 is a block diagram of an adder circuit according to the first embodiment of the present invention, and FIG. 2 is a block diagram of a multiplier circuit according to the second embodiment of the present invention. 1; redundant binary adder, 2; redundant binary / binary conversion circuit, 3; selection circuit, 4; overflow detection circuit, 5, 15; maximum value detection circuit, 6, 16; minimum value detection circuit, 11; Redundant binary multiplier

Claims (4)

(57) [Claims] Claim: What is claimed is: 1. A redundant binary operation circuit for performing an operation of redundant binary format data and outputting a redundant binary format operation result and a carry signal, and a redundant binary operation circuit output from this redundant binary operation circuit. Redundant binary / 2 that converts the operation result in binary format to binary data
An overflow in the redundant binary operation circuit is detected by referring to a binary conversion circuit, the carry signal, the most significant bit of the operation result in the redundant binary format, and the sign bit of the operation result converted into the binary data. And an overflow detection circuit that operates. 2. The overflow detection circuit, wherein the carry signal is "1" and the most significant bit of the operation result is "0".
Alternatively, when it is "1", or when the carry signal is "1", the most significant bit of the operation result is "-1", and the sign bit is "1", it is determined that the overflow has occurred, When the carry signal is "-1" and the most significant bit of the operation result is "0" or "-1", or when the carry signal is "-1" and the most significant bit of the operation result is "1". The arithmetic circuit according to claim 1, wherein when the sign bit is "1" and the sign bit is "0", it is determined that the overflow is negative. 3. The arithmetic circuit according to claim 1, wherein the redundant binary arithmetic circuit is a redundant binary adder circuit. 4. The arithmetic circuit according to claim 1, wherein the redundant binary arithmetic circuit is a redundant binary multiplication circuit.