JPH0431925A - Arithmetic circuit - Google Patents

Abstract

PURPOSE:To reduce a scale and to improve the computing speed for an arithmetic circuit of a redundant binary form by detecting an overflow based on a carrying signal, the highest-order bit, and a sign bit of the binary data on a redundant binary/binary conversion circuit. CONSTITUTION:A redundant binary adder 1 and a redundant binary/binary conversion circuit 2 are provided with an overflow detecting circuit 4 and a selective circuit 3. The adder 1 outputs a carry C of the addition result and the highest-order bit ZMSB to the circuit 4. Meanwhile the circuit 2 outputs the sign bit ZZsgn of the conversion result to the circuit 4 respectively. The circuit 4 detects a real overflow based on three data C, ZMSB and ZZsgn and outputs the detection result OF to the circuit 3. The circuit 3 selects and outputs an output (s) based on the result OF, the output ZZMAX of a maximum value output circuit 5, the output ZZMIN of a minimum value output circuit 6, and the binary conversion data ZZ.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an arithmetic circuit that performs arithmetic processing such as addition and multiplication in a redundant binary format, and particularly to an arithmetic circuit suitable for integration into an integrated circuit.

[Prior Art] In order to improve the processing speed, arithmetic circuits have been known that perform arithmetic processing by converting normal binary representation into data in redundant binary representation (for example, "redundant binary representation"). "High-speed multiplier for VLSI using addition trees" by Noh Takagi, IEICE Transactions CD), JBEi-08゜pp, 683-69
0. June 1983).

In redundant binary representation, 1 bit of data is expressed as 3 of 0, 1°-1.
Expressed as a value, it is possible to realize an adder circuit without carry propagation. For example, now bit data [-
If we represent 1 piece as [1 piece, for example, 2 bits of 6 bits.
In the case of a base number, the most significant bit is the sign bit, so the maximum value is 011111□ (63□.) and the minimum value is 100000□ (-64□.), but in redundant binary representation, the maximum The value is [:111111ko2 (127
□o), the minimum value is 111111C2, (-127□.)
becomes. Note that the subscript 2 is a binary number, and 10 is a 10
The base number [2 indicates redundant binary representation.

Furthermore, in redundant binary representation, one numerical value can be expressed using several types of data. For example, 5□. When expressed as a 4-digit redundant binary number, 0101+2+, 1111□2. 5
It is possible to express the street.

When performing addition of redundant binary numbers, ot2+ and 0,2° and 1[2co and 1,2 . There is no carry in the addition of 1c2.
and 1, 2. In the addition of 1, 2. carry up, 1c2
．． and 1c2. In the addition of 1, 2. 1.
2. and 0,2. In the addition of 1, 2, etc. from the lowest order. If there is a carry, 1゜2. Carry up 1c2. and 0.2. In the addition of 1, 2, etc. from the lowest order. If there is a carry of IC2, carry is carried out. Therefore, for example 1. .

+1. When adding o, OL2+ +OIc2>
By performing the addition of 11c2z +01ra+ without performing the addition of , it is possible to perform addition without carry propagation. If there is no carry propagation, a carry of a certain digit will always be absorbed by its higher-order digit. Therefore, in this case, the addition process is performed in two steps by calculating the intermediate sum of each digit and the carry signal in the first step, and calculating the sum of the intermediate sum and the carry signal from the lower order in the second step. finish. Therefore, the calculation processing time can be significantly reduced compared to normal binary calculation in which a carry signal propagates over two bits or more.

Conversion from a redundant binary number to a binary number can be performed by normal subtraction between a binary number that collects only the digits where 1 [2] is set and a binary number that collects only the digits where lc2+ stands. .

[Problems to be Solved by the Invention] However, in the conventional arithmetic circuit described above, the most significant bits of the addend and the summand are 1+2]11°. .

or IC2] + L2+,
Because a carry always occurs, it may be mistakenly determined that an overflow has occurred even when there is actually no overflow.

For example, 111111c2+ (-1+o) and 111
When we perform the operation with 111[2+(1□.), we get +
) 111111(2) arri In this case, (-1+o)+(1+o)=(-2+.), so even though there is no actual overflow,
When a carry signal is input from the most significant bit, an overflow is determined.

Therefore, in order to prevent this, the number of bits of the redundant binary addition circuit and the redundant binary number to binary number conversion circuit is extended to the upper side to provide a protection bit, but in this case, There are problems such as an increase in circuit scale and a decrease in calculation speed.

In particular, if a protection bit is provided for each of a large number of adder circuits constituting an integrated multiplier, the increase in circuit scale and the decrease in calculation speed will become non-negligible.

The present invention has been made in view of such problems, and includes:
without increasing circuit scale or reducing calculation speed.
It is an object of the present invention to provide an arithmetic circuit that can detect the occurrence of a true overflow and improve arithmetic accuracy.

[Means for Solving the Problems] An arithmetic circuit according to the present invention includes a redundant binary arithmetic circuit that performs arithmetic operations on data in a redundant binary format and outputs an arithmetic result in a redundant binary format and a carry signal; a redundant binary/binary conversion circuit that converts the redundant binary format operation result outputted from the redundant binary operation circuit into binary data; The present invention is characterized by comprising an overflow detection circuit that detects an overflow in the redundant binary arithmetic circuit by referring to the bit and the sign bit of the operation result converted to the binary data.

[Operation] According to the present invention, not only the carry signal of the operation result, but also the carry signal, the most significant bit of the operation result in redundant binary format, and the sign bit of the operation result converted to binary data. By referring to this, it is possible to accurately determine whether the operation result truly overflows.

Therefore, according to the present invention, a redundant binary arithmetic circuit and a redundant binary arithmetic circuit are provided.
Overflow detection can be performed without expanding the number of bits of the hex/binary conversion circuit, and it is possible to reduce the circuit scale and improve the calculation speed.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of an adder circuit according to a first embodiment of the present invention.

Addend data X and addend data y to be added are input to the redundant binary adder 1 in a data format expressed in redundant binary numbers. A redundant binary adder 1 adds both data X and y, and outputs an addition result 2 expressed in redundant binary numbers and a carry signal C. The addition result 2 is input to a redundant binary/binary conversion circuit 2. The redundant binary/binary conversion circuit 2 converts the addition result 2 into an addition result 22 in binary representation and outputs it.

This addition result zz is input to one input terminal of the three-man-powered selection circuit 3.

On the other hand, the carry signal C output from the redundant binary adder 1 and the most significant bit zMs13 of the addition result 2, and the redundant 2
Sign bit ZZ*Ign, which is the most significant bit of the addition result 22 output from the decimal/binary conversion circuit 2, is input to the overflow detection circuit 4. The overflow detection circuit 4 determines the presence or absence of overflow based on these data and outputs overflow detection information OF. This information OF consists of a signal indicating the presence or absence of overflow and a signal indicating its sign, and is supplied to the selection circuit 3 as its selection control signal. Maximum value data ZZMAX from the maximum value output circuit 5 and minimum value data ZZxrs from the minimum value output circuit 6 are input to the remaining two input terminals of the selection circuit 3, respectively. The selection circuit 3 selects these input data based on the overflow information OF, and outputs the selected data as the addition result S.

Next, the overflow detection circuit 4 will be explained in more detail.

Basically, the overflow detection circuit 4 detects the most significant bit of the carry signal C1 calculation result 2 as shown in Table 1 below.
Based on SB and the sign bit ZZsign of the calculation result 22, overflow information OF is output.

Table 1 Here, since the redundant binary representation takes three values (1, 0, 1), it is actually represented by two bits: a sign bit (SB) and a value bit (VB).

Further, the overflow detection information OF is composed of an overflow detection signal OD and a positive/negative determination signal O8. Therefore, the actual truth table of the overflow detection circuit 4 is as shown in Table 2 below.

Table 2 Next, the operation of the adder circuit configured as described above will be explained.

Now, assume that the following summand data X and addend data y are input to the redundant binary adder 1.

X”011111(2) (1110)Y=1011
00t2> (20to) The redundant binary adder 1 performs the following operation.

01J111. c2+ +) 101100 (11 arri) The addition result z=100011t2+ is obtained.

Next, the redundant binary/binary conversion circuit 2 performs the following subtraction.

011111□ 1gn As a result, the addition result in binary representation z z=01111
1□ is required.

In this case, the overflow detection circuit 4 has C"OL□
l ZMSB = 112 + Z Zsrl&n
=02 is input, so the overflow detection signal 0D
=0, positive/negative determination signal 0S=O. That is, in this case, no overflow occurs, and the selection circuit 3 selects the addition result 22 output from the redundant binary/binary conversion circuit 2 and outputs it as the addition result S.

Next, a case will be described in which the following summand data X and addend data y are input to the redundant binary adder.

x=011111c2> (11+o)y=101
110 (2+ (22□.) In the redundant binary adder 1,
Perform the following calculations.

011111[2] +) 101110(2) arry As a result, the addition result Z = 100001 c2r is obtained.

Next, the redundant binary/binary conversion circuit 2 performs the following subtraction.

oooooi ign As a result, the addition result in binary representation zz=10ooooi
. is required.

In this case, in the overflow detection circuit 4, c=Q 1
2 + ZMSB = I L + Z Z*+g
Since n=12 is input, the overflow detection signal 0D=1 and the positive/negative determination signal 08=0. That is, in this case, a positive overflow has occurred, and the selection circuit 3 selects the maximum value ZZ output from the maximum value output circuit 5.
MAX is selected and output as the addition result S.

Similarly, when a negative overflow occurs, the selection circuit 2 selects the minimum value ZZ output from the minimum value output circuit 6.
Select MIN and output it as the addition result S.

As a result, when an overflow occurs, the limited addition result S is output.

As described above, according to the addition circuit according to the present embodiment, overflow can be correctly detected using the most significant bit ZMSB of the carry signal C1 addition result 2 and the sign bit zzs1gn of the addition result 22. In the adder 1 and the redundant binary/binary conversion circuit 2, there is no need to provide a protection bit or the like, and the circuit scale can be reduced and the calculation speed can be improved.

FIG. 2 is a block diagram showing the configuration of a multiplication circuit according to a second embodiment of the present invention.

Note that in FIG. 2, the same parts as those in the circuit of FIG. 1 are given the same reference numerals, and explanations of the overlapping parts will be omitted.

The circuit of this embodiment is a redundant binary adder 1 in FIG.
is replaced with a redundant binary multiplier 11.

That is, multiplicand data a and multiplier data b are input to redundant binary multiplier 11 and multiplied there.

The redundant binary multiplier 11 is composed of a large number of redundant binary adders that perform addition of a large number of partial products.

The multiplication result m by the multiplier 11 is input to the redundant binary/binary conversion circuit 2 and converted into a binary number.

The multiplication result mm converted into a binary number is input to one input terminal of a three-man-powered selection circuit 3.

On the other hand, the most significant bit mmss of the carry signal 01 multiplication result m from the adder at the final stage of the redundant binary multiplier 11 and the sign bit mm1 of the multiplication result mm.

is input to the overflow detection circuit 4, where overflow is detected. Its overflow information OF
is supplied to the selection circuit 3 as a selection control signal.

The selection circuit 3 selects one of the maximum value mmMAx from the maximum value output circuit 15 and the minimum value mmM□8 from the minimum value output circuit 16 as the multiplication result according to the overflow information OF, and outputs it as the multiplication result M.

Addition using redundant binary numbers can suppress the propagation of carry signals to one digit as described above, and is particularly effective when applied to a multiplication circuit that adds a large number of partial products. However, in a multiplication circuit, since the addition of redundant binary numbers is repeated many times, the need for automatic flow determination is greater than in a normal addition circuit. In this regard, according to the present embodiment, since O/NJ-flow can be detected correctly, a high-speed and accurate multiplication circuit can be provided.

In addition, according to the multiplication circuit according to this embodiment, overflow is determined by referring only to the addition result of the final stage without making an overflow determination of the addition result of each stage, so that the effect of reducing the circuit scale is reduced. It can be further increased.

[Effects of the Invention] As described above, according to the present invention, not only the carry signal of the operation result but also the most significant bit of the operation result and the sign bit of the operation result converted to binary data are referred to. Since the overflow of the operation result is determined, there is no need to expand the number of bits of the operation circuit and the redundant binary/binary conversion circuit.

Therefore, it is possible to improve the calculation accuracy while reducing the circuit scale and improving the calculation speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an adder circuit according to a first embodiment of the invention, and FIG. 2 is a block diagram of a multiplication circuit according to a second embodiment of the invention. 1; Redundant binary adder, 2; Redundant binary/binary conversion circuit, 3
; Selection circuit, 4; Overflow detection circuit, 5, 15;
Maximum value detection circuit, e, is; Minimum value detection circuit, 11; Redundant binary multiplier

Claims (4)

[Claims] (1) A redundant binary arithmetic circuit that performs arithmetic operations on data in redundant binary format and outputs a redundant binary arithmetic result and a carry signal, and a redundant binary format that is output from this redundant binary arithmetic circuit. a redundant binary/binary conversion circuit for converting the operation result into binary data, the carry signal, the most significant bit of the operation result in the redundant binary format, and a sign of the operation result converted to the binary data; and an overflow detection circuit that detects an overflow in the redundant binary arithmetic circuit by referring to the bits. (2) The overflow detection circuit detects when the carry signal is "1" and the most significant bit of the operation result is "0" or "1", or when the carry signal is "1" and the operation result is When the most significant bit of is "-1" and the sign bit is "1", it is determined that there is a positive overflow, and the carry signal is "-1" and the most significant bit of the operation result is "0" or "-1", or when the carry signal is "-1", the most significant bit of the operation result is "1", and the sign bit is "0", a negative overflow occurs. 2. The arithmetic circuit according to claim 1, wherein the arithmetic circuit makes a determination. (3) The arithmetic circuit according to claim 1 or 2, wherein the redundant binary arithmetic circuit is a redundant binary adder circuit. (4) The arithmetic circuit according to claim 1 or 2, wherein the redundant binary arithmetic circuit is a redundant binary multiplier circuit.