JPH06243194A - Method and device for automatic logic circuit design - Google Patents

Abstract

PURPOSE:To provide a method and a device for automatic logic circuit design, which generate a circuit having a small number of logic elements and that of logic stages at the time of generating both a multiplier which performs multiplication with a multiplier or a multiplicand being a constant and a circuit including the multiplier, and the multiplier which performs multiplication with a multiplier or a multiplicand being a constant. CONSTITUTION:It is retrieved whether the constant of a binary expressed number being the multiplicand continuously has digits whose values are '1' or not (S201); and if it continuously has them, the constant is converted to a redundant binary where the value of the digit one higher than the highest digit of them, the value of the lowest digit, and values of digits between them are '1', and '0' respectively (S202). Next, it is retrieved whether the constant has two adjacent two of digits whose values are '-1' and '0' or not ($204); and when it has them, they are converted to '0' and '-1' respectively (S205). When the number of digits whose values are not '0' of the multiplicand is reduced in this manner, a circuit to obtain partial products of only values which are not '0' is generated by a processing omitted in the figure.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit, and more particularly to a multiplier for multiplying an input variable by a predetermined constant, or a method and apparatus for automatically designing a logic circuit including such a multiplier. It is about.

[0002]

2. Description of the Related Art A multiplier for multiplying digital data is
In addition to being used as a stand-alone LSI, DSP (digital
It is also often used for built-in LSI such as signal processor). In many cases, a multiplier or a logic circuit including the multiplier is designed by using an automatic design device.
When the function description information in which the function required for the circuit is represented by a hardware description language or the like is input, the automatic designing apparatus outputs the function description information mainly to a circuit including a virtual functional element in which only the function is defined. Express the function circuit information in the internal representation format, and then convert it to the logic circuit information that indicates the circuit that actually consists of the logic element, and then indicate the circuit to which the mounting element to be mounted by the specific technology is assigned. It is designed to generate mounted circuit information. When the function indicated by the function description information includes multiplication, for example, a predetermined bit width (4, 8, 17, 3) previously registered in the library as a hardware macro is used.
If a general-purpose multiplier (such as 2 bits) is applicable,
When it is allocated or a multiplier that is not registered in the library is required, a logic circuit that constitutes an addition shift type multiplier or the like is newly generated.

By the way, the above-mentioned multiplier is required to be further speeded up, the circuit scale and the chip area are reduced in accordance with the increase of the multiplication bit width and the diversification of applications, and the circuit system to which various multiplication methods are applied is required. Is proposed. For example, as a multiplication method for executing the multiplication at high speed, a multiplication method using the second-order modified Booth's recoding method is used. This method aims to increase the multiplication speed and reduce the circuit scale by reducing the number of partial products to about 1/2.

For example, when multiplying a binary number X having an m-bit width by a binary number Y having an n-bit width, the binary number X is expressed as follows. (However, m and n are positive integers, X and Y are unsigned integers) However, q is q = m / 2 when m is an even number and q when it is an odd number.
= (M-1) / 2, X _{m + 1} when m is an even number,
X _m, X _-1, and X _m, X _-1 when m is an odd number, the convenience of values, a _{X m + 1 = X m =} X -1 = 0.

Therefore, the product P of X and Y is Becomes

That is, the number of partial products is q = m / 2 + 1
(M is an even number), or q = (m-1) / 2 + 1 (m
Is an odd number), and the number of logic stages in the circuit for calculating the sum of partial products is l when two-input adders are connected in a binary tree shape.
og ₂ (m / 2 + 1) stages (m is an even number) or log
₂ ((m-1) / 2 + 1) stages (m is an odd number). However, although the number of partial products is reduced as described above, (-
2X _{2p + 1} + X _2p + X _2p-1 ) can take values of -2,-
1, 0, 1, or 2, of which -2 or 2
If it is, to obtain the partial product, it is necessary to shift the value of Y by 1 bit to the left. This becomes a factor of increasing the scale of the circuit for obtaining the partial product and the processing time.

On the other hand, the speeding up of the multiplication speed and the reduction of the circuit scale are not limited to the improvement of the performance of the multiplication algorithm as described above, but are also achieved by the optimization of the circuit at the logic element level. More specifically, when developing the circuit information at the logic element level into the circuit information at the mounting element level to be mounted on the chip, a part of the circuit is replaced with an equivalent circuit with a smaller number of logic elements or logic stages. The redundant circuit portion is deleted.

That is, for example, when the multiplier is a constant that is not a power of 2, the value of all bits of the partial product corresponding to a bit whose value is 0 in the multiplier becomes 0. Therefore, a circuit for generating such a partial product is used. , The adding circuit always has a constant signal state. Therefore, in the conventional automatic design device,
A multiplication circuit in which the multiplier and the multiplicand are variables, that is, a multiplication circuit in which the number of partial products and the number of partial product addition logic stages are constant,
After generating a circuit that generates a constant as a multiplier, by optimizing the circuit at the logic element level as described above,
For example, deletion of a logic element whose signal level is always constant has been performed.

[0009]

However, in the conventional automatic design apparatus, the circuit optimization at the logic element level is performed only when the circuit portion matching the predetermined pattern set in advance has more logic elements or logic elements. Since it is performed by replacing with an equivalent circuit with a small number of logic stages,
Even if such optimization is performed when the multiplier or the multiplicand is a constant, there is a problem that it is not always possible to generate a circuit that minimizes the number of logic elements in the entire circuit. In particular, when two-input adders are connected in a binary tree form to add partial products, if a part related to the partial product adder circuit in which all the bit values are 0 is omitted, the binary tree is normally used. Since the balance is lost, it is difficult to minimize the number of logic elements and the number of logic stages by partially replacing the circuits.

In view of the above points, the present invention is a logic capable of generating a circuit having a small number of logic elements and a low number of logic stages when generating a multiplier or a logic circuit including a multiplier for performing multiplication with a constant multiplier or multiplicand. It is intended to provide an automatic circuit design method and an apparatus therefor.

[0011]

In order to achieve the above object, the present invention is an automatic design method of a logic circuit for generating information indicating a logic circuit for obtaining a product of a constant multiplier and a multiplicand. A second constant represented by a redundant binary representation having a first constant represented by a binary representation and a value equal to the first constant and having a non-zero number of digits smaller than the first constant. A constant conversion step for converting into a constant and a partial product calculation circuit information generation step for generating information indicating a partial product calculation circuit for calculating a partial product with the multiplicand only for a digit whose value in the second constant is non-zero. , A partial product-sum operation circuit information generating step of generating information indicating a partial product-sum operation circuit for obtaining a partial product sum of partial products obtained by the partial product operation circuit.

Further, there is provided an automatic design device of a logic circuit for generating information indicating a logic circuit for obtaining a product of a multiplier which is a constant and a multiplicand, wherein a first constant represented by a binary expression is converted into a first constant. Constant conversion means for converting into a second constant represented by redundant binary representation, which has a value equal to the constant of, and has a number of non-zero digits smaller than that of the first constant; A partial product arithmetic circuit information generating means for generating information indicating a partial product arithmetic circuit for obtaining a partial product with a multiplicand, and a partial product sum of partial products obtained by the partial product arithmetic circuit only for a digit whose value is non-zero. And a partial product-sum operation circuit information generating means for generating information indicating the partial product-sum operation circuit to be obtained.

Here, when the partial product arithmetic circuit information and the information indicating the partial product sum arithmetic circuit are generated, the non-zero digit number, which is the number of digits whose value is non-zero, is obtained. When the number is 2 or more, the constant may be divided so that the non-zero digit number is approximately equal.

[0014]

With the above configuration, a circuit for multiplying a multiplicand by a constant having a small number of non-zero digits, and
Circuit information indicating a circuit including a partial product arithmetic circuit for obtaining a partial product with the multiplicand is generated only for a digit whose value is non-zero. Further, when the constant is divided so that the non-zero digit number becomes substantially equal, the partial product-sum operation circuit has a good balance of 2
It is connected like a branch tree.

[0015]

【Example】

(First Embodiment) A first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram showing the configuration of an automatic logic circuit designing apparatus. In the figure, a central processing unit (CPU) 601 is for performing circuit design processing and the like. The storage unit 602 stores programs and data relating to design processing. The input / output device 603 is composed of, for example, a keyboard and a CRT, and inputs information about a circuit to be designed by the automatic design system, circuit information as a design processing result of the central processing unit 601, and various information about processing. Is output. The above-mentioned means are connected via a bus line.

The central processing unit 601 carries out a design process as shown in FIG. First, information about the multiplication module to be designed is input from the input / output device 603, and the storage unit 6
02 (S101). The information regarding the multiplication module is, for example, information for identifying the multiplication module, information indicating a binary expression constant A input / output to / from the multiplication module, a variable X, and a product P. , Information indicating the bit width (number of digits) m, n, and the value of the constant A. In the following description, the term “multiplying module” is also used to indicate information about the multiplying module such as the above information to the extent that it is not confused.

Next, the constant A is represented by a redundant binary expression, is equal to the constant A, and has a value of 1 or -1 (non-zero).
Is converted into a constant A1 having a small number of bits (digits) (S102). After that, circuit information indicating the circuit of the multiplication module that multiplies the constant A1 and the variable X is generated and stored in the storage unit 602 (S103). In this process,
As will be described later, since the partial product is generated only for the digit whose value in the constant A1 is non-zero, the number of partial products and the circuit for calculating the partial product sum are combined with the conversion in (S102). The number of logic stages can be kept small.

The circuit information stored in the storage means 602 is
It is output to the input / output device 603 (S104). Hereinafter, the constant conversion process of (S102) and the circuit information generation process of (S103) will be described in detail. In the constant conversion process of (S102), the process as shown in FIG. 3 is performed.

First, the constant A is searched for a portion having a value of 1 continuously for two digits or more (S201), and if there is no such portion, the number of digits having a non-zero value cannot be reduced. Since it cannot be done, simply convert the constant A into a redundant binary representation constant A1 in which the value of the sign bit of each digit is all 0 (positive) and the value of the absolute value bit of each digit is equal to the value of each digit of the constant A. (S20
6) Return to the main routine.

On the other hand, if there is a portion where the value is 1 continuously for two digits or more, the process proceeds to (S202), and for all such portions, the binary representation corresponding to the left side of the following equation (1). Is converted into a redundant binary representation corresponding to the right side to generate a constant α. Here, for integers k and l such that k ≧ 1 and l ≧ 0, it is assumed that the values at each digit from the digit of 2 ^{k + l to} the digit of 2 ^l in the constant A are all 1.

(2 ^k +2 ^k-1 + ... +2 ¹ +2 ⁰ ) · 2 ^l = (2 ^{k + 1} + (− 2 ⁰ )) · 2 ^l (1) Specifically, for example, k = 5 In the case of, the above equation (1) becomes like the equation (2). 111111 · 2 ^l = 100000T · 2 ^l (2) Here, in the redundant binary representation, the symbol T is both the sign bit and the absolute value bit of that digit are 1 (that is, the value of that digit is −1. ) Is shown. That is, the sequence of numerical values "111111" in binary representation is converted into the sequence of numerical values "100000T" in redundant binary representation.

By this conversion processing, the sequence B of k + 1 digit numerical values in which the numerical value 1 is continuous is converted into the sequence B'of 1 digit numerical value 1, the continuous k digit numerical value 0, and the 1 digit numerical value T. And the number of digits whose values before and after conversion are non-zero NZ (B), NZ
(B ') is as shown in equation (3) regardless of the value of k. NZ (B) ≧ NZ (B ′) = 2 (3) Next, the part where the numerical value sequence in the constant α is “11” (note that the numerical value 1 is continuous for 3 or more digits). No.) is searched for (S203), and if such a location does not exist (S204), the process proceeds to (S204).
After returning to 202), the above conversion is repeated until it does not exist to generate a new constant α, and then (S204).
Move to.

In (S204), the constant α generated as described above is searched for a place where the numerical sequence is "T1", and if there is no such place, the constant α is left as it is. As the constant A1 (S207), the process returns to the main routine. On the other hand, if there is such a place, (S2
Moving to 05), a constant A1 is generated by converting the above sequence of numerical values "T1" into "0T" as shown in the following expression (4). That is, if the sequence of the numerical values of the 2 ^{l + 1} digit and the 2 ^l digit in the constant α is “T1”, the numerical sequence “T1” is generally (−2 ¹ +2 ⁰ ) · 2 ^l . Since it is expressed, (-2 ¹ +2 ⁰ ) · 2 ^l = (− 2 ⁰ ) · 2 ^l (4) When the above expression (4) is expressed by the same expression as the expression (2), (5) It becomes like a formula.

T1 · 2 ^l = 0T · 2 ^l (5) By this conversion process, the number of digits NZ (A1) in which the value of the constant A1 is non-zero is further reduced, and the following formula (6) Like NZ (A1) ≤ m / 2 + 1 (m is an even number) ≤ (m-1) / 2 + 1 (m is an odd number) (6) Hereinafter, it will be described that NZ (A1) is as in the equation (6). . (1) When the number of digits m is an even number (for example, m = 8) (1a) When NZ (A) = m / 2, that is, when half of the constant A is the numerical value 1 and half is the numerical value 0 NZ (A
1) becomes maximum, for example, (7-1), (7-
This is a case where the numerical value 0 and the numerical value 1 appear alternately as in the formula (2), and there is no arrangement of the numerical value 1 having two or more consecutive digits. In this case, since the processes of (S202) and (S205) are not performed, NZ (A) = NZ (A1) = m / 2.

01010101 ...... (7-1) 10101010 ...... (7-2) (1b) When NZ (A) = m / 2 + 1 NZ (A1) is maximized, for example, in two digits at one location. The above is a case where there is a continuous sequence of numerical values 1 and the other numerical values 0 and 1 appear alternately.

11010101 (8-1) 101011 (8-2) Equation (8-1) is obtained by substituting the numerical value 0 at the top of the equation (7-1) with the numerical value 1, (8 The formula -2) is (7-2)
The numerical value 0 at the bottom of the expression is replaced with the numerical value 1. Converting these as above, (9-1),
It becomes like the formula (9-2). Therefore, at this time NZ
(A1) = m / 2 + 1.

10T010101 (9-1) 0101110T (9-2) When replacing one of the numerical values 0 with the numerical value 1 in the equations (7-1) and (7-2), To (8-
In the case of substituting it differently from the equations (1) and (8-2), a sequence of numerical values 1 of three consecutive digits always occurs. Therefore, among the m / 2 + 1 number 1s, the sequence (111) of the number 1 consecutive 3 digits at one place is (100T).
Is converted to, and the number of non-zero values is reduced by one, so N
Z (A1) = m / 2 + 1-1 = m / 2. (1c) When NZ (A) = m / 2 + 2 or more In this case, the sequence of consecutive numerical values 1 is further increased, and the sequence of numerical values 1 is replaced with one numerical value 1 and one numerical value T. You can only be

Therefore, if m is an even number, NZ (A
1) never exceeds m / 2 + 1. (2) When the number of digits m is an odd number (for example, m = 7) (2a) When NZ (A) = (m + 1) / 2 The maximum value of NZ (A1) is, for example, (10-1)
As in the formula, there is a sequence of numerical values 1 that are continuous in two digits or more, and in other cases, numerical value 0 and numerical value 1 appear alternately, or as in formula (10-2), numerical value 0 and numerical value 1 This is the case when appears alternately.

[0101] (10-1) 1010101 (10-2) In the formula (10-2), since there is no continuous sequence of the numerical value 1, the processes of (S202) and (S205) are performed. Absent. Therefore, NZ (A) = NZ (A1) = (m +
1) / 2. Further, in (10-1), (S2
By the processing of 02), the sequence shown in the equation (11) is obtained, and again NZ (A) = NZ (A1) = (m + 1) /
It becomes 2.

010110T (11) (2b) In the case of NZ (A) = (m + 1) / 2 + 1 NZ (A1) is maximized when, for example, two consecutive 2-digit numerical values 1 are arranged. The other case is that the numerical value 0 and the numerical value 1 appear alternately. As a more specific example, as shown in the expression (12), the numerical value 0 at the top of the expression (10-1) is replaced by the numerical value 1.

1101011 (12) In the equation (12), the processing of (S202) is performed twice to obtain equations (13) and (13 '), and further by the processing of (S205), 13T) is expressed as follows: 10T0110T (13) 10T10T0T (13 ') 100T0T0T (13 ") Therefore, NZ (A1) at this time is NZ (A1).
= (M-1) / 2 + 1. (2c) In the case of NZ (A) = m / 2 + 2 or more In this case, the sequence of consecutive numerical values 1 is further increased, and the sequence of numerical values 1 is replaced with one numerical value 1 and one numerical value T. You can only be

Therefore, if m is an odd number, NZ (A
1) never exceeds (m-1) / 2 + 1. Therefore, the number NZ of digits whose value in the constant A1 is non-zero, which is converted by the processing of (S202) and (S205)
When the number of digits m of the constant A is an even number and an odd number, (A1) is expressed by the equation (6).

Further, in the circuit information generation processing of (S103), the processing shown in FIG. 4 is performed. First, the constant A1 is set to be a multiplicand and the variable is set to be a multiplier (S4).
01). Here, the distinction between the multiplier and the multiplicand is for convenience in the following processing. Next, the multiplication module stored in the storage unit 602 is selected (S402).
At first, since there is only one multiplication module, it is selected, but when the multiplication module is divided by the processing described later, a plurality of multiplication modules are stored in the storage unit 602.
One of them is selected.

For the selected multiplication module, the number of digits NZ (A1) whose value in the constant A1 is non-zero is counted (S403), and it is determined whether NZ (A1)> 1 (S404). More specifically, for example, NZ
The numerical value 2 is subtracted from (A1), and it is determined whether the subtraction result is not negative. If NZ (A1)> 1, (S40
5), for example, the multiplication module shown in FIG.
It replaces with the two multiplication modules shown in FIG. 6 and the addition circuit which adds the partial products output from them. In addition, in FIGS. 5 and 6 and the following description, for example, A1 (m-
1: 0) indicates the value from 2 ^m-1 digit in the constant A1 to 2 ⁰ digit.

More specifically, as shown in FIG. 7, first,
The maximum integer Q that does not exceed NZ (A1) / 2 is obtained (S701), and the Qth digit is obtained by counting the number of ^nonzero digits from 2 ⁰ (S702). If such a digit is, for example, a digit of 2 ^k , then the constant A1 (m−k: 0) is changed to the constant A1 (m− as shown in the following equation (14).
1: k + 1) and A1 (k: 0) (S70
3) Further, as shown in the equation (15), it is replaced with a circuit including a multiplication module for multiplying each constant and the variable X, and an addition circuit (S704). Here, as the addition circuit, for example, IEEE trans. On computer p
The redundant binary number addition circuit described in 165-170, 1984 can be applied.

[0036] A1 (m-1: 0) = A1 (m-1: k + 1) · 2 k + 1 + A1 (k: 0) · 2 0 ... (14) P = A1 (m-1: 0) · X = A1 (m−1: k + 1) · X · 2 ^{k + 1} + A1 (k: 0) · X (15) The value of Q is not limited to the above, and is a minimum integer of NZ (A1) / 2 or more. Or Q or NZ (A1) -Q is NZ (A
The minimum power of 2 may be 1) / 2 or more.

On the other hand, in the above (S404), NZ (A1) ≦
If it is determined to be 1, the process proceeds to (S406) and the multiplication module is replaced with the partial product generation circuit. Specifically, if a digit whose value in the multiplier A1 is non-zero is detected and, for example, that digit is a digit of 2 ^j and the value of that digit is A1 (j), as shown in the following equation (16), A1 (J) Replaced by a logic circuit including an XOR gate, etc., which calculates the product of 2 ^j and the variable X.

When A1 (j) = 1, X (n−1: 0) · 2 ^{j When} A1 (j) = − 1, −X (n−1: 0) · 2 ^j (16) After the processing of (S405) and (S406), the storage unit 60
It is determined whether or not the multiplication module is still stored in 2 (S407), and if so, the above (S407).
Returning to 402), the same processing is repeated. That is, the division processing of the multiplication module is recursively performed, and as shown in FIG. 8, it is converted into a circuit including a partial product generation circuit 1001 and an addition circuit 1002 connected in a binary tree shape.

As described above, after reducing the number of non-zero digits in the constant, only for the remaining non-zero digits, the partial product is generated while dividing the digits into about 1/2. Since the number of partial products and the number of logical stages of the circuit for obtaining the partial product sum are suppressed to be small, since the conversion is performed by the circuit and the adding circuit. Moreover, since there are only three digit values of -1, 0, and 1 in which the above value is non-zero, shift processing is not required to obtain a partial product for any value, so that the circuit scale is further increased. It is possible to reduce and speed up.

In the above example, the partial product generation circuit for obtaining the partial product of the redundant binary representation is applied.
As shown in the expression (17), a partial product generation circuit for obtaining a partial product in binary representation may be applied. Where n
ot indicates the logical inversion of each digit. When A1 (j) = 1, X (n−1: 0) · 2 ^j A1 (j) = − 1, not (X (n−1: 0) · 2 ^j ) +1 (17) ( Equation 17 is such that when A1 (j) = − 1, the multiplicand X
It is shown that the two's complement is taken by logically inverting each digit of, and adding the numerical value 1 to the least significant digit.
It is output as a decimal number.

In this case, the adder circuit for the partial products includes a Wallace
The addition method using a tree can be applied. This constitutes an adder circuit with four inputs and two outputs and carries out carry save addition, and can perform the same operation as the redundant binary adder circuit. The details are described in, for example, ICD89-128 of the Institute of Electronics, Information and Communication Engineers, and therefore omitted. (Second Embodiment) As a second embodiment of the present invention, another example of the constant conversion processing for converting the constant A into the constant A1 will be described with reference to FIGS.

In the constant conversion process shown in FIG. 9, the same result as the process of (S102) of FIG. 2 is obtained by performing a predetermined process for each digit without searching for consecutive digits of the value 1. Obtainable. First, in (S301), the value A (i) for each digit in the constant A is divided into an intermediate carry C (i) and an intermediate sum S (i) based on the following (Table 1). Here, the intermediate carry C (i) and the intermediate sum S (i) are values having a relationship shown in the following equation (18), and A (i)
And C (i) is a binary representation number, and S (i) is a redundant binary representation number.

[0043]

[Table 1]

A (i) = C (i) · 2 + S (i) (18) That is, the values of C (i) and S (i) above are the values A
(I) and its one digit higher value A (i + 1), and if A (i) is 0, then C (i) = 0,
S (i) = 0. On the other hand, if A (i) is 1, and if A (i + 1) = 0, then C (i) = 0, S
(I) = 1, and if A (i + 1) = 1, then C
(I) = 1 and S (i) = T.

Specifically, it is divided as shown in FIG. For example, for the numerical value 1 of the lowest digit of the constant A, since the numerical value of 1 digit higher is 1, (C (0), S (0)) = (1,
T). Next, in (S302), the intermediate sum S and the intermediate carry C are added to calculate the redundant binary representation constant α. Here, as shown in the above equation (18), C
Since (i) is weighted by 2 ¹ more than S (i), for example, the addition of the digit of 2 ⁱ is as in equation (19).

Α (i) = S (i) + C (i−1) (19) That is, each intermediate sum S (i) is one digit lower than the intermediate digit C (i−1). It is added to form a constant α (i). Note that this addition is performed by redundant binary addition. By the above-mentioned processing, the constant α in which the number of non-zero digits is reduced is obtained as in the processing of (S202) in FIG. The above process may be repeated as in the first embodiment.

In (S303), the value α (i) for each digit in the constant α is divided into an intermediate carry R (i) and an intermediate sum B (i), as in (S301). However, the following (Table 2) is used as a rule for division, and (α
If (i + 1), α (i)) = (T, 1), then (B
(I), R (i)) = (1, T), otherwise,
(B (i), R (i)) = (0, α (i)).

[0048]

[Table 2]

Further, in (S304), the above (S30
Similar to 2), add intermediate carry R and intermediate sum B,
As shown in FIG. 11, as in the process of (S205), the redundant binary representation constant A1 in which the numerical sequence “T1” is converted to “0T” is calculated.

[0050]

As described above, according to the present invention,
Since there are few circuits for obtaining partial products, and a circuit in which adder circuits for obtaining partial product sums are connected in a well-balanced binary tree is formed, it is possible to easily reduce the circuit area and increase the multiplication speed. There is an effect that can be.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an automatic logic circuit designing apparatus according to a first exemplary embodiment.

FIG. 2 is a flowchart showing a main routine of the designing process.

FIG. 3 is a flowchart showing constant conversion processing of the same.

FIG. 4 is a flowchart showing a circuit information generation process of the multiplication module.

FIG. 5 is an explanatory diagram showing an example of a multiplication module before division processing.

FIG. 6 is an explanatory diagram showing an example of a multiplication module after the same division processing.

FIG. 7 is a flowchart showing a multiplication module replacement process of the same.

FIG. 8 is a block diagram showing an example of a circuit to be generated.

FIG. 9 is a flowchart showing constant conversion processing in the second embodiment.

FIG. 10 is an explanatory diagram showing an example of first processing for dividing the multiplicand.

FIG. 11 is an explanatory diagram showing an example of second processing for dividing the multiplicand.

[Explanation of symbols]

 601 central processing unit 602 storage means 603 input / output device 1001 partial product generation circuit 1002 addition circuit

Claims (26)

[Claims] 1. A method of automatically designing a logic circuit for generating information indicating a logic circuit for obtaining a product of a multiplier, which is a constant, and a multiplicand, wherein a first constant expressed in binary representation is converted into a first constant. A constant conversion step of converting to a second constant represented in redundant binary representation, which has a value equal to the constant of and has a number of non-zero values smaller than that of the first constant; A partial product arithmetic circuit information generating step for generating information indicating a partial product arithmetic circuit for obtaining a partial product with a multiplicand, and a partial product sum of partial products obtained by the partial product arithmetic circuit only for a digit whose value is non-zero. A partial product-sum operation circuit information generating step of generating information indicating a desired partial product-sum operation circuit, and a logic circuit automatic designing method. 2. The method for automatically designing a logic circuit according to claim 1, wherein the constant converting step includes a continuous digit detecting step of detecting a continuous digit having a value of 1 continuously for two digits or more in the first constant. , Converts the value of the digit one digit higher than the most significant digit of the consecutive digits to 1, and converts the value of all digits except the least significant digit of consecutive digits to 0,
A continuous digit conversion step of converting the value of the least significant digit of continuous digits to -1, and a method for automatically designing a logic circuit. 3. The method for automatically designing a logic circuit according to claim 2, wherein the constant converting step further comprises: in the constant converted by the continuous digit converting step,
Adjacent digit detection step of detecting adjacent digits whose adjacent upper digits and lower digits are -1 and 1, respectively, and converting the value of the upper digits of the adjacent digits into 0 and changing the value of the lower digits to-.
An adjacent digit conversion step of converting into 1 is provided, and an automatic designing method of a logic circuit. 4. The method for automatically designing a logic circuit according to claim 3, wherein the consecutive digit conversion step is repeated until there are no consecutive digits having a value of 1 continuously for at least two digits, and then an adjacent digit detection step, And a method of automatically designing a logic circuit, which comprises performing an adjacent digit conversion step. 5. The method for automatically designing a logic circuit according to claim 1, wherein in the constant conversion step, the value of each digit in the first constant is a digit one digit higher than the digit in the intermediate carry. And a value division step of dividing into a value of the digit in the intermediate sum, an addition step of adding the intermediate carry and the intermediate sum, and an automatic designing method of a logic circuit. 6. The method for automatically designing a logic circuit according to claim 5, wherein in the value dividing step, the value of each digit in the first constant is 1.
And the value of the digit one digit higher than that digit is 1, the digit of the digit one digit higher than that digit in the intermediate carry is set to 1, and the value of that digit in the intermediate sum is -1. A method for automatically designing a logic circuit, characterized by: 7. The method for automatically designing a logic circuit according to claim 6, wherein the constant conversion step is carried out in such a manner that the digit of each digit is 1 and the digit of the digit one digit higher than the digit is 1. A method for automatically designing a logic circuit characterized by repeating until there is no more. 8. The method for automatically designing a logic circuit according to claim 5, wherein the constant conversion step further includes adding the result of the adding step to a value of a digit one digit higher than the digit in the intermediate carry. , A value re-dividing step of dividing the value into the value of the digit in the intermediate sum, an intermediate carry obtained by the re-dividing step, and a re-adding step of adding the intermediate sum. Automatic design method. 9. The method for automatically designing a logic circuit according to claim 8, wherein the value subdivision step has a value of 1 in each digit in the addition result of the addition step, and is a digit one digit higher than the digit. If the value of is -1, the value of the digit one digit higher than the digit in the intermediate carry is set to 1, and the value of the digit in the intermediate sum is set to -1. Design method. 10. The method for automatically designing a logic circuit according to claim 1, further comprising a non-zero digit number counting step of obtaining a non-zero digit number which is the number of digits in which the value in the second constant is non-zero. A determination step of determining whether the non-zero digit number is 1 or 2 or more, and a digit division step of dividing the second constant by a predetermined digit when the non-zero digit number is 2 or more In the partial product sum arithmetic circuit information generating step, information indicating a partial product sum arithmetic circuit that adds the product of each of the divided constants and the multiplicand is generated, and the partial product arithmetic circuit information generating step Then, when the number of non-zero digits is 1, information indicating a partial product arithmetic circuit for calculating the product of the value of non-zero digits and the multiplicand is generated, and the non-zero digit number counting step, the determination step, the digit Division step, partial product-sum operation circuit information generation step And partial product calculating circuit information generating step, the divided constants digits dividing step, the automatic design method of a logic circuit characterized in that it is performed recursively. 11. The method for automatically designing a logic circuit according to claim 10, wherein a predetermined digit dividing the second constant has a minimum absolute value of a difference of non-zero digits in each of the divided constants. A method for automatically designing a logic circuit, which is characterized in that 12. The method for automatically designing a logic circuit according to claim 1, wherein the partial product calculation circuit information generating step outputs the multiplicand as it is when the value of each digit in the second constant is 1. On the other hand, when the value is -1, the information indicating the circuit for outputting the signal by inverting the value of each digit in the multiplicand is generated, and the method for automatically designing the logic circuit. 13. The method for automatically designing a logic circuit according to claim 1, wherein the partial product arithmetic circuit information generating step outputs the multiplicand as it is when the value of each digit in the second constant is 1. On the other hand, when it is -1, the value of each digit in the multiplicand is logically inverted, and the information showing the circuit which outputs the value by adding 1 to the least significant digit is generated. A method of automatically designing a logic circuit characterized by. 14. An automatic design apparatus for a logic circuit, which generates information indicating a logic circuit for obtaining a product of a multiplier, which is a constant, and a multiplicand, wherein a first constant expressed in a binary representation is converted into a first constant. A constant conversion means for converting into a second constant represented by redundant binary representation, which has a value equal to the constant of, and has a number of non-zero digits smaller than that of the first constant; A partial product arithmetic circuit information generating means for generating information indicating a partial product arithmetic circuit for obtaining a partial product with a multiplicand, and a partial product sum of partial products obtained by the partial product arithmetic circuit An apparatus for automatically designing a logic circuit, comprising: partial-sum-of-sum arithmetic circuit information generating means for generating information indicating a partial-sum-of-sum arithmetic circuit to be obtained. 15. The logic circuit automatic designing device according to claim 14, wherein the constant conversion means is a continuous digit detecting means for detecting a continuous digit having a value of 1 continuously for two digits or more in the first constant. , Converts the value of the digit one digit higher than the most significant digit of the consecutive digits to 1, and converts the value of all digits except the least significant digit of consecutive digits to 0,
A continuous digit converting means for converting the value of the least significant digit of continuous digits into -1, and an automatic design device for a logic circuit, comprising: 16. The apparatus for automatically designing a logic circuit according to claim 15, wherein the constant converting means further comprises: a constant converted by the continuous digit converting means; Adjacent digit detection means for detecting 1 and adjacent digits that are 1, and converting the value of the upper digit of the adjacent digit into 0 and the value of the lower digit
An automatic design device for a logic circuit, comprising: an adjacent digit converting means for converting into 1; 17. The automatic logic circuit designing apparatus according to claim 16, wherein the continuous digit converting means repeats the above conversion until there are no continuous digits having a value of 1 continuously for two digits or more, and thereafter, the adjacent digits are adjacent to each other. An automatic design device for a logic circuit, characterized in that a digit detection means and an adjacent digit conversion means perform the detection and conversion. 18. The apparatus for automatically designing a logic circuit according to claim 14, wherein the constant conversion means sets the value of each digit in the first constant to a digit one digit higher than the digit in the intermediate carry. And an adder for adding the intermediate carry and the intermediate sum, and the value dividing means for dividing the value into the value of the digit in the intermediate sum. 19. The apparatus for automatically designing a logic circuit according to claim 18, wherein the value dividing means has a value of 1 for each digit in the first constant and a value of a digit one digit higher than the digit. When it is 1, the value of the digit one digit higher than the digit in the intermediate carry is set to 1, and the value of the digit in the intermediate sum is set to -1. 20. The automatic logic circuit designing device according to claim 19, wherein the constant converting means has a value of 1 in each digit and 1 more than that digit.
An automatic design apparatus for a logic circuit, characterized in that the above conversion is repeated until there is no digit whose upper digit is 1. 21. The logic circuit automatic design device according to claim 18, wherein the constant conversion means further sets the addition result of the addition means to a value of a digit one digit higher than the digit in the intermediate carry. , A value re-dividing means for dividing the value into the value of the digit in the intermediate sum, an intermediate carry obtained by the re-dividing means, and a re-adding means for adding the intermediate sum. Automatic design equipment. 22. The logic circuit automatic design device according to claim 21, wherein the value subdivision means has a value of 1 in each digit in the addition result of the addition means, and a digit one digit higher than the digit. Value of -1
, The value of the digit that is one digit higher than the digit in the intermediate carry is 1, and the value of that digit in the intermediate sum is -1.
A logic circuit automatic designing device characterized by the following. 23. The automatic logic circuit designing device according to claim 14, further comprising a non-zero digit number counting means for determining a non-zero digit number, which is the number of digits whose value in the second constant is non-zero. Determination means for determining whether the non-zero digit number is 1 or 2 or more, and digit dividing means for dividing the second constant by a predetermined digit when the non-zero digit number is 2 or more And the partial product-sum operation circuit information generating means generates information indicating a partial product-sum operation circuit for adding the product of each of the divided constants and the multiplicand, and the partial product operation circuit information generating means Generates information indicating a partial product arithmetic circuit that obtains the product of the non-zero digit value and the multiplicand when the non-zero digit number is 1, and the non-zero digit number counting means, the determination means, and the digit division. Means, partial product sum arithmetic circuit information generating means, and partial product arithmetic circuit information generating means The divided constants in means,
An automatic design device for a logic circuit, which has control means for starting recursively. 24. The logic circuit automatic designing apparatus according to claim 23, wherein the predetermined digit dividing the second constant has a minimum absolute value of a difference in the number of non-zero digits in each of the divided constants. An automatic design device for logic circuits, which is characterized by such a digit. 25. The automatic logic circuit designing apparatus according to claim 14, wherein the partial product arithmetic circuit information generating means outputs the multiplicand as it is when the value of each digit in the second constant is 1. An automatic logic circuit designing device is characterized in that when it is -1, information indicating a circuit to be output is generated by inverting the value of each digit in the multiplicand. 26. An automatic logic circuit designing apparatus according to claim 14, wherein the partial product calculation circuit information generating means outputs the multiplicand as it is when the value of each digit in the second constant is 1. On the other hand, when it is -1, while logically inverting the value of each digit in the multiplicand,
An automatic logic circuit designing device characterized by generating information indicating a circuit for adding a value 1 to the least significant digit and outputting the result.