JP3492638B2 - Floating point multiplier - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floating-point multiplier, and more particularly to a floating-point multiplier that speeds up operations.

[0002]

2. Description of the Related Art As a technique of this kind, "Japanese Patent Laid-Open No. 5-2"
No. 65714 ”. This technique is a multiplier that obtains a partial product of a multiplier and a multiplicand and adds the obtained partial products to obtain a product, and a partial product adder that obtains two intermediate products from the partial product and two From the predetermined digit to the higher digit of the intermediate product, assume the multiple possible carry values from the lower digit, add the above intermediate products, and obtain the multiple added values corresponding to the assumed values. A product adder, a carry look-ahead circuit that generates carry information from a lower digit than a predetermined digit of the intermediate product from the two intermediate products in parallel with the addition of the intermediate products, and the carry carry. And a selection circuit for selecting the added value of the intermediate product adder based on the output of the look-ahead circuit.

[0003]

The problem of the above-mentioned conventional technique is that the delay time is large.

The reason is that since the output of the intermediate product adder is input to the condition determining circuit, the delay time increases as much as it goes through the intermediate product adder.

Further, since the all-one predictor is provided inside the intermediate product adder, all the prediction signals from the first digit to the 51st digit of all the lower bits are generated when the all-one prediction signal is generated. This is because the delay time increases because it is generated using the result.

An object of the present invention is to use the output of the multiplication array as an input to the normalization judgment circuit after rounding, and to find only the exclusive OR of each bit, and by the total logical product, all 1's.
By generating the predicted signal (normalized signal after rounding),
It is to realize a floating point multiplier with a small delay time.

[0007]

[Means for Solving the Problems]

[0008]

The first floating-point multiplier of the present invention inputs a mantissa M0 and a mantissa M1 and performs multiplication to obtain a partial product A and a partial product B.
And a partial product A from the multiplication array.
Of an arbitrary number of bits of the upper part of the partial product B and an arbitrary number of bits of the upper part of the partial product B are input and addition is performed, an addition result C0, an addition result C1 obtained by adding 1 to the addition result C0, and A mantissa adder that outputs a carry X from the highest order, a lower bit of the multiplication array excluding the upper part of the upper part of the partial product A, and an upper part of the partial product B A carry generation circuit for inputting the lower bits excluding the number part of the number -1 and generating and outputting a carry F from the highest order, and the arbitrary number of bits above the partial product A from the multiplication array, The arbitrary number −1 bits above the partial product B and the carry F from the carry generation circuit are input, and the arbitrary number of bits above the partial product A from the multiplication array and the partial product B Of the above-mentioned arbitrary number -1 , The exclusive OR of each bit is calculated, and the total logical product F0 of the results is calculated. Further, the exclusive OR of each bit and the logical sum of the bits of the lower digits (only the least significant), Alternatively, the exclusive logical sum with the logical product of the bits of the lower digits is obtained, and the total logical product F of the results is obtained.
1 is calculated, and if carry F is '0', F0 is selected, and if carry F is '1', F1 is selected and the post-rounding normalization determination is output as post-rounding normalized signal G. A circuit, the lower bits of the multiplication array excluding the upper arbitrary number of parts of the partial product A, and the lower bits of the upper partial product B excluding the upper part of the arbitrary number-1 Is input, and if there is a bit that becomes 1 in the addition result, 1
A sticky generation circuit that generates and outputs a sticky bit S that becomes
The addition result C1 is input, and the addition result is obtained according to the carry X from the mantissa adder, the post-rounding normalized signal G from the post-rounding normalization determination circuit, and the sticky bit S from the sticky generating circuit. Select either C0, addition result C1, or 100 ... 00,
And a rounding digit matching circuit that outputs the result of mantissa multiplication.

The second floating-point multiplier of the present invention inputs the exponent E0 and the exponent E1 and performs addition to perform exponential part addition result D.
0, the exponent part addition result D1 which is obtained by adding 1 to the exponent part addition result D0, and the exponent part adder which inputs and outputs the mantissa M0 and the mantissa M1 and outputs the partial product A and partial product B An arbitrary number of upper bits of the partial product A and an arbitrary number of higher bits of the partial product B are input from the array and the multiplication array, and addition is performed to obtain an addition result C0 and an addition result C0. An addition result C1 obtained by adding 1 and a mantissa adder for outputting a carry X from the most significant bit; a lower bit obtained by removing the arbitrary number of upper bits of the partial product A from the multiplication array; , A carry generation circuit for inputting the lower bits excluding the number of the arbitrary number -1 of the upper part of the partial product B and generating and outputting a carry F from the uppermost part, and the partial product A from the multiplication array. Any number of bits, parts of the high order of The arbitrary number of bits higher than B-1 and the carry F from the carry generation circuit are input, and the arbitrary number of bits higher than the partial product A from the multiplication array and the higher order of the partial product B. The arbitrary number of
The exclusive OR of each bit of 1 is calculated, the total logical product F0 of the results is calculated, and the exclusive OR of each bit and the OR of the bits of the lower digits (only the lowest bit is calculated). ), Or exclusive OR with the logical product of the bits of the lower digits, and calculate the total logical product F1 of the results. If carry F is 0, select F0 and carry F is 1 If so, F1 is selected and the normalized signal G after rounding is selected.
Post-rounding normalization determination circuit, the lower bits of the multiplication array excluding the upper part of the upper part of the partial product A, and the arbitrary number of the upper part of the partial product B −
A sticky generation circuit for inputting the lower bits excluding the part of the number of 1 and generating and outputting a sticky bit S which becomes 1 when there is a bit which becomes 1 in the addition result;
The addition result C0 and the addition result C1 from the multiplication array are input, the carry X from the mantissa adder, the post-rounding normalized signal G from the post-rounding normalization determining circuit, and the sticky generating circuit. According to the sticky bit S of the addition result C0, the addition result C1, or 1
00 ... 00 is selected and output as the mantissa multiplication result, and the exponent addition result D0 and the exponent addition result D1 are input from the exponent adder, and the mantissa adder outputs Either the exponent part addition result D0 or the exponent part addition result D1 is selected according to the carry X, the post-rounding normalization signal G from the post-rounding normalization determination circuit, and the sticky bit S from the sticky generating circuit. Then
And a rounding digit matching circuit that outputs the result of exponential part multiplication.

The third floating-point multiplier of the present invention inputs a mantissa M0 and a mantissa M1 and performs multiplication to obtain a partial product A and a partial product B.
And a partial product A from the multiplication array.
Of an arbitrary number of bits of the upper part of the partial product B and an arbitrary number of bits of the upper part of the partial product B are input and addition is performed, an addition result C0, an addition result C1 obtained by adding 1 to the addition result C0, and A mantissa adder for outputting carry X0, X1 from the highest order, a lower bit excluding the arbitrary number of higher order parts of the partial product A from the multiplication array, and a higher order bit of the partial product B A carry generation circuit for inputting the lower bits excluding the arbitrary number-1 and generating and outputting a carry F from the highest order, and a partial product A from the multiplication array.
Of the upper part of the partial product A from the multiplication array, and the carry F from the carry generation circuit. An exclusive OR of each bit of the arbitrary number of bits and the above-mentioned arbitrary number-1 bit of the partial product B is obtained, and the total logical product F0 of the results is calculated. The exclusive OR of the exclusive OR and the bits of the lower digits (only the least significant) or the logical product of the bits of the lower digits is calculated, and the total logical product F1 of the results is calculated. , If carry F is 0, select F0, if carry F is 1, select F1 to output a rounded normalization signal G after rounding normalization determination circuit, and a portion from the multiplication array. Below excluding the arbitrary number of parts above the product A Bit, and, if you enter the lower bits except for the number of portions of said any number -1 upper partial product B, and there is 1 the bits in the addition result 1
A sticky generation circuit that generates and outputs a sticky bit S that becomes
When the addition result C1 is input and the carry X0 = 0 and X1 = 0, the addition result C0 and the addition result C1 are selected, and the carry X0 = 1 and X1 = 1 respectively,
“1, the rest after deleting the least significant bit of the addition result C0” =
Addition result C3, “1, remaining after removing the least significant bit of addition result C1” = addition result C4 is selected, and if sticky bit S is 0, addition result C3 is selected and sticky bit S is 1 and the normalized signal G after rounding
Is 0, the addition result C4 is selected, and if the sticky bit S is 1 and the post-rounding normalized signal G is 1,
And a rounding digit matching circuit for selecting 100 ... 00 and outputting as a mantissa multiplication result.

The fourth floating-point multiplier of the present invention inputs the exponent E0 and the exponent E1 and performs addition to perform exponent part addition result D.
0, the exponent part addition result D1 which is obtained by adding 1 to the exponent part addition result D0, and the exponent part adder which inputs and outputs the mantissa M0 and the mantissa M1 and outputs the partial product A and partial product B An arbitrary number of upper bits of the partial product A and an arbitrary number of higher bits of the partial product B are input from the array and the multiplication array, and addition is performed to obtain an addition result C0 and an addition result C0. Addition result C1 obtained by adding 1 and mantissa adder for outputting carry X0 and carry X1 from the most significant bit, and lower bits obtained by excluding the arbitrary number of higher parts of partial product A from the multiplication array , And a carry generation circuit for inputting the lower bits excluding the upper part of the arbitrary number −1 of the partial product B and generating and outputting a carry F from the uppermost part, and a part of the multiplication array. Any number of bits above the product A , The arbitrary number −1 bits of the upper part of the partial product B and the carry F from the carry generation circuit, and the arbitrary number of bits of the upper part of the partial product A from the multiplication array, and the partial product The exclusive OR of each bit of the arbitrary number of bits −1 above B is calculated, the total logical product F0 of the results is calculated, and the exclusive OR of each bit and the lower digit are calculated. The logical sum of the bits (only the least significant bit) or the exclusive OR of the bits of the lower digits is calculated, and the total logical product F of the results is obtained.
Calculate 1 and if carry F is 0, select F0,
If the carry F is 1, F1 is selected and the post-rounding normalization determination circuit that outputs the post-rounding normalization signal G and the arbitrary number of parts above the partial product A from the multiplication array are removed. Input the lower bits and the lower bits excluding the part of the arbitrary number -1 of the upper part of the partial product B,
When a sticky bit S that becomes 1 when the addition result has a bit of 1 is generated and output, and the addition result C0 and the addition result C1 from the multiplication array are input, carry X0 = 0, If X1 = 0,
When the addition result C0 and the addition result C1 are selected and carry X0 = 1 and X1 = 1, respectively, “1, the remaining of the least significant bit of the addition result C0 is deleted” = addition result C
3, "1, remaining after deleting the least significant bit of addition result C1" = addition result C4 is selected, and if sticky bit S is 0, addition result C3 is selected and sticky bit S is 1 , And if the normalized signal G after rounding is 0, the addition result C4 is selected and the sticky bit S is 1
And if the normalized signal G after rounding is 1, 100.
..00 is selected and output as the mantissa multiplication result, and the exponent addition result D0 and the exponent addition result D1 are input from the exponent adder, (carry X0 = 0) * (sticky bit S = 0) or (carry X1 =
0) * (sticky bit S = 1) * (normalized signal after rounding G = 0), the exponent part addition result D0 is selected,
Otherwise, it has a rounding digit matching circuit that selects the exponent part addition result D1 and outputs it as the exponent part multiplication result, selects the exponent part addition result D1, and outputs it as the exponent part multiplication result. .

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a floating point multiplier according to an embodiment of the present invention. Referring to FIG. 1, in the embodiment of the present invention, a multiplication array 11, a mantissa adder 12, a sticky generation circuit 14, a carry generation circuit 15, a post-rounding normalization determination circuit 16, and a rounding digit alignment. And the circuit 17.

The multiplication array 11 is connected to the mantissa adder 12, the sticky generation circuit 14, the carry generation circuit 15, and the post-rounding normalization determination circuit 16, and the floating-point data m ( Positive integers) [bit] mantissas M0 and M1 are input to perform multiplication to obtain two partial products A and B. Each of A and B is 2m-1 [bit]. The sum of the two partial products A and B output from the multiplication array 11 is the mantissa multiplication result.

The mantissa adder 12 is connected to the multiplication array 11, the carry generation circuit 15, and the rounding digit matching circuit 17, and outputs two partial products A which are the outputs of the multiplication array 11.
M + 1 [bits] of B, the upper m [bits] of B, and the carry F that is the output of the carry generation circuit 15 are added as inputs, and the addition result is incremented by 1 to obtain the addition result C0 and the addition result +1. C1 and carry X
0 and X1 are output to the rounding digit matching circuit 17.

The exponent part adder 13 is a rounding digit matching circuit 1
7 is added, exponent parts E0 and E1 of the floating point data cut out in the preprocessing stage are added, and the addition result is incremented by 1, and exponent part addition result D0 and exponent part addition result + 1 The partial addition result D1 is output to the rounding digit matching circuit 17.

FIG. 2 is a block diagram showing the sticky generating circuit 14.

Referring to FIG. 2, the sticky generating circuit 14 includes a multiplication array 11 and a rounding digit matching circuit 1.
7 and is the lower m-2 [bits] of the two partial products A and the lower m-1 of B which are the outputs of the multiplication array 11.
The sticky bit is obtained by calculating the exclusive OR of each bit by inputting [bit], calculating the exclusive OR of the result and the logical OR of the lower bits, and calculating the total OR of the results. Calculate S. This is a bit that indicates whether or not there is a bit that is at least 1 in the lower bits that are truncated.

FIG. 3 is a block diagram showing the carry generation circuit 15.

Referring to FIG. 3, carry generation circuit 15
Is connected to the multiplication array 11, the mantissa adder 12, and the post-rounding normalization determination circuit 16, and the lower m-2 [bits] and lower B of the two partial products A output from the multiplication array 11 are With m-1 [bit] as an input, a carry F is calculated by a BLC adder, and is output to the mantissa adder 12 and the rounded normalization determination circuit 16.

FIG. 4 is a block diagram showing the normalization determination circuit 16 after rounding.

Referring to FIG. 4, the post-rounding normalization determination circuit 16 is connected to the multiplication array 11, the carry generation circuit 15, and the rounding digit alignment circuit 17, and the multiplication array 11 is connected.
The upper m + 1 [bits] of the two partial products A that are the outputs of
Higher-order m [bit] of B and carry generation circuit 15
The carry F, which is the output of the carry, is calculated as an input, and the exclusive OR of each bit is calculated, the total logical product of the results is calculated, and the result is rounded and normalized according to the carry F that is the output of the carry generation circuit 15. The signal G is output to the rounding digit matching circuit 17.

FIG. 5 is a block diagram showing the rounding digit matching circuit 17.

Referring to FIG. 5, the rounding digit matching circuit 17
Is connected to the mantissa adder 12, the exponent adder 13, the sticky generation circuit 14, and the post-rounding normalization circuit 6, and the sticky bit S that is the output from the sticky generation circuit 14 and the post-rounding normalization determination circuit The rounded normalized signal G which is the output from 16 and the mantissa adder 12
The carry results X0 and X1 from C1 to C1 are used as control signals to output the output D0 of the exponent adder 13 and the output C0 of the mantissa adder 12 and C1 from the multiplication result H of the floating point multiplier.

Next, the operation of the embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a block diagram showing the internal configuration of the multiplication array 11. FIG. 7 is an explanatory diagram showing an outline of multiplication. FIG. 8 is an explanatory diagram showing a numerical example of multiplication.

Floating-point data is composed of a sign bit of 1 [bit], an exponent part E of n (positive integer) [bit], and a mantissa part M of m (positive integer) [bit]. It is cut out (not shown). Floating point data multiplication is done by adding exponent part and mantissa part, then rounding
And, the result can be obtained by performing digit alignment.

First, the exponent parts E0 and E1 of the floating point data cut out in the preprocessing stage are added by the exponent part adder 13 and the addition result is incremented by +1 to obtain the exponent part addition result D0. , +1 result of addition result of exponent part D
1 is output to the rounding digit matching circuit 17.

The m-bit mantissa parts M0 and M1 of the floating point data cut out in the preprocessing stage are input to the multiplication array 11.

The multiplication array 11 receives the input mantissa M0.
Is a multiplicand and M1 is a multiplier, and each bit of the multiplier is multiplied by the multiplicand (referred to as a partial product), arranged in the form of a binary number and added to obtain a product. For the addition of each partial product, an addition circuit configured by a full adder as shown in FIG. 6 is used to add m partial products to two, and finally obtain the two obtained products. The 2m-1 [bit] partial products A and B are converted to the mantissa adder 12, the sticky generating circuit 14, the carry generating circuit 15, and
It outputs to the normalization determination circuit 16 after rounding.

Next, the mantissa adder 12 operates in the multiplication array 1
The two outputs of 1, the upper m + 1 [bits] of A, the upper m [bits] of B, and the carry F from the carry generation circuit 15 are added (accurately, A [0: m] (bit 0 to m + 1 of bit m). Represents [bit]) and '0', B [0: m-1]
B is shifted 1 [bit] to the right as in (representing m [bit] of bit 0 to bit m−1), and the mantissa M
The product C0 of m + 1 [bits] is obtained as the multiplication result of 1 and M2. This product C0 is incremented by 1 to calculate C1. At this time, when the addition result C0 is carried to m + 2 [bits], the carry X0 from the most significant digit is set to “1” and C1 is carried to m + 2 [bits]. , The carry X1 from the top is set to '1'. m +
When it does not become 2 [bit], carry X is set to "0". Finally, C0 and C of m + 1 [bit]
There is 1 and a digit, and X is output to the rounding digit matching circuit 17.

In order to reduce the delay time of the mantissa adder 12, for example, the calculation circuit for C0 is set to A [0: m].
+ ('0', B [0: m-1]) and A [0:
m] + ('0', B [0: m-1]) + '1', and two addition circuits for carrying out the addition F
And a selection circuit switched by the above, and the calculation circuit of C1 is A [0: m] + ('0', B [0: m-1]) +
'1' and A [0: m] + ('0', B [0: m
−1]) + '2' and two addition circuits and a selection circuit that switches the addition results by the carry F may be used.

The sticky generating circuit 14 adds the lower m-2 [bits] and '0' of the two outputs A of the multiplication array 11 and the lower m-1 [bits] of B as shown in FIG. Then, the total logical sum is calculated and the sticky bit S is output to the rounding digit matching circuit 17.

The carry generation circuit 15 is, as shown in FIG.
The lower order m− of the two partial products A which are the outputs of the multiplication array 11
Carry F is calculated by inputting 2 [bits] and lower m-1 [bits] of B, and output to mantissa adder 12 and post-rounding normalization determination circuit 16.

As shown in FIG. 4, the post-rounding normalization determination circuit 16 includes the upper m + 1 [bits] of the two partial products A output from the multiplication array 11 and the upper m [bits] of B. The exclusive OR of the two is calculated, the total logical product F0 of the results is calculated, and the case where the addition results are all "1" is detected. Further, the exclusive OR of each bit and the bits of the lower digits are detected. Or the exclusive OR with the logical product of the bits of the lower digits, and the total logical product F1 of the results is calculated, and the addition result is only 0 at the lowest, The case where all others are '1' is detected. Next, if the carry F is "0", F0 is selected, and if the carry F is "1", F1 is selected and output as a rounded normalized signal G.

Referring to FIG. 6, the significant digit m + 1 obtained by adding the two outputs of the multiplication array 11 may exceed the representation range of the mantissa part (overflow) when rounding up due to rounding occurs. Effective digit m + 1 at this time
All the bits are "1" (111 ... 11).
In order to perform floating-point multiplication at high speed, it is necessary to detect whether digit alignment occurs after rounding as early as possible. However, in the present embodiment, since the output of the multiplication array 11 is used, the mantissa part is used. By calculating the total logical product of the outputs of the adder 12, the detection can be performed at a higher speed than the configuration in which the case where all the bits of the addition result are all 1 is detected. When a carry occurs from the addition result of the lower m-2 [bits] of the partial product A and the lower m-1 [bits] of B, the case where each bit of the addition result is 1110 (carry and The total is 111 ... 11)
Also, the carry F, which is the output of the carry generation circuit 15, is selected as a control signal. The selected result is a rounded digit matching circuit 17 as a normalized signal G after rounding.
Output to.

The rounding digit matching circuit 17 includes the exponent adder 1
3, the exponent part addition result D0 and the exponent part addition result + '1' result D1, and the mantissa part addition result C0 and the mantissa part addition result +, which are outputs from the mantissa part adder 12.
The result C1 of "1", the carry X, and the sticky bit S which is the output from the sticky generating circuit 14.
And the post-rounding normalization signal G output from the post-rounding normalization determination circuit 16 are input, and the sticky bit S, the post-rounding normalization signal G, and the carry X are used as control signals for the exponent part addition result D0, The multiplication result H is output from the exponent part addition result D1, the mantissa part addition result C0, and the mantissa part addition result result C1.

Referring to FIG. 5, regarding the exponent part,
(Carry X0 = 0) * (sticky bit S =
0) or (carry X1 = 0) * (sticky bit S = 1) * (normalized signal G after rounding G = 0), the exponent addition result D0 is selected; otherwise, the exponent The part addition result D1 is selected and output as the exponent part multiplication result H. Regarding the mantissa part, first, carry X0 = 0, X.
If 1 = 0, the mantissa part addition result C0 and the mantissa part addition result C1 are selected, respectively, and if carry X0 = 1 and X1 = 1, then “1, mantissa part addition result C0 [0: m
−1] ”= mantissa part addition result C3,“ 1, mantissa part addition result C1 [0: m−1] ”= mantissa part addition result C4, and
Next, if the sticky bit S = 0, the mantissa part addition result C3 is selected, and the sticky bit S = 1 and
If the normalized signal after rounding G = 0, the mantissa part addition result C4 is selected. If the sticky bit S = 1 and the normalized signal after rounding G = 1, rounding or normalization after rounding is performed. Since it occurs, the result of addition of exponent part D1 and rounding up by rounding is 111.
00 ... 00 is selected and output as the mantissa multiplication result H.

Next, an example in which actual numerical values are given will be described with reference to the drawings.

In FIG. 8, m = 6, M0 = 100001, M
The detailed multiplication processing operation when 1 = 111110 is shown. The partial products are arranged in the form of writing, and 4 bits of each bit string are input to the adder shown in FIG. 6 (first addition). In FIG. 8, the portion surrounded by each vertically long rectangle shows the bits input to the adder shown in FIG. In addition, 0 is input to the empty bit of the adder, which is an input of 4 bits or less among the 4-bit input. S, which is the result of the first addition
(Sum) and C (carry) are again input to the adder shown in FIG. 6 as inputs of 4 bits each (second addition), and A [0:10] = 00 as the result of the second addition.
000000000000 and B [0:10] = 111
Obtain 11111110. Of these, A [0: 6] and B
The addition of [0: 5] is the output C0 of the mantissa adder 12, C0 = 0111111. Also, C1 = 01111
11 + 1 = 1,000,000 and X = 0.

A [0: 6] and B [0: 5] are
It becomes an input to the post-rounding normalization determination circuit 16, and the post-rounding normalized signal G = 1. Furthermore, A [7:10], and
B [6:10] becomes an input to the sticky generation circuit 14 and the carry generation circuit 15, and the output of each circuit is a sticky bit S = 1 and a carry F = 0.
Becomes

Referring to FIG. 5, since S = 1 and G = 1, D1 is selected as the result of the exponent part and 100 ... 00 is selected as the result of the mantissa part, and output as the multiplication result H.

As described above, the effective digit m + of the partial products A and B is
Partial products A and B are obtained by obtaining the exclusive OR of each bit of 1 [bit] and calculating the total logical product of the results.
By detecting the case where all the bits of the addition result of the significant digit m + 1 [bit] of are all “1” (111 ... Detects cases where digit alignment occurs after rounding faster than floating-point multipliers configured to detect the case where all bits of the addition result are all "1" (111 ... 11) by calculating the product it can.

In the above, the significant digit is m + 1 [bit].
However, when the significant digit is m [bits], the input to the mantissa adder 12, carry generation circuit 15, post-rounding normalization determination circuit 16, and sticky generation circuit 14 is 1 [bits]. It can be easily realized by shifting. For example, the mantissa adder 12 receives the upper m [bits] of the partial product A and the upper m−1 [bits] of B.

[0045]

The effect of the present invention is that the operation speed of the floating point multiplier can be increased.

The reason is that the output of the multiplication array is used as an input to the post-rounding normalization determination circuit, and only the exclusive OR of each bit is obtained, and the post-rounding normalized signal is generated by the total logical product. This is because it has a configuration that does.

[Brief description of drawings]

FIG. 1 is a block diagram showing a floating point multiplier according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a sticky generating circuit.

FIG. 3 is a block diagram showing a carry generation circuit.

FIG. 4 is a block diagram showing a normalization determination circuit after rounding.

FIG. 5 is a block diagram showing a rounding digit matching circuit.

FIG. 6 is a block diagram showing an internal configuration of a multiplication array.

FIG. 7 is an explanatory diagram showing an outline of multiplication.

FIG. 8 is an explanatory diagram showing a numerical example of multiplication.

[Explanation of symbols]

11 Multiplication array 12 Mantissa adder 13 Exponent part adder 14 Sticky generation circuit 15 Carry generation circuit 16 Normalization judgment circuit after rounding 17 Rounding digit matching circuit

Claims (4)

(57) [Claims] 1. A multiplication array that inputs a mantissa M0 and a mantissa M1 and performs multiplication to output a partial product A and a partial product B; an arbitrary number of bits higher than the partial product A from the multiplication array; and a partial product. The above-mentioned arbitrary number -1 bit of B is input, addition is performed, and addition result C0, addition result C1 obtained by adding 1 to addition result C0, and mantissa addition for outputting carry X from the highest order are output. And a low-order bit of the multiplication array excluding the high-order arbitrary number part of the partial product A and a low-order bit excluding the high-order arbitrary number-1 part of the partial product B , A carry generation circuit for generating and outputting a carry F from the highest order, and an arbitrary number of the high order partial products A from the multiplication array.
, The arbitrary number of higher bits of the partial product B minus 1 bit,
And input carry F from the carry generation circuit,
A number of the top of the partial product A from the multiplication array
Bits, and the number of bits of the upper part of the partial product B minus 1
The exclusive OR of each bit of the
The total logical product F0 is calculated, and the exclusive
Logical sum and logical sum of bits of lower digits (least significant bit
Or the logical product of the bits of the lower digits.
Other logical OR is calculated, and the total logical product F1 of the results is calculated,
If carry F is '0', select F0 and carry
If F is '1', select F1 and use the normalized signal after rounding.
A post-rounding normalization determination circuit that outputs as a signal G, a lower bit obtained by removing the upper part of the upper part of the partial product A from the multiplication array, and the arbitrary number −1 of the upper part of the partial product B A low-order bit excluding the part of the number, and a sticky bit circuit that generates and outputs a sticky bit S that becomes 1 when there is a bit that becomes 1 in the addition result, and the addition result C0 from the multiplication array. , The addition result C1 is input, and addition is performed according to the carry X from the mantissa adder, the rounded normalized signal G from the rounded normalization determination circuit, and the sticky bit S from the sticky generation circuit. Result C0, addition result C1, or 1
And a rounding digit matching circuit that selects any one of 00 ... 00 and outputs it as a mantissa multiplication result. 2. An exponent part adder for generating and outputting an exponent part addition result D0 and an exponent part addition result D1 obtained by adding 1 to the exponent part addition result D0 and an exponent part addition result D1 and a mantissa M0. , A mantissa M1 is input and multiplication is performed to output a partial product A and a partial product B, an arbitrary number of bits higher than the partial product A from the multiplication array, and the arbitrary upper bit of the partial product B. A mantissa adder that inputs the bits of the number -1 and performs addition to output an addition result C0, an addition result C1 obtained by adding 1 to the addition result C0, and a carry X from the most significant digit; Input the lower bits excluding the upper part of the partial product A and the lower bits excluding the upper part of the partial product B of the arbitrary number -1 from the highest bit Carry generation times that generate and output the carry F of Path and the arbitrary number of high order partial products A from the multiplication array.
, The arbitrary number of higher bits of the partial product B minus 1 bit,
And input carry F from the carry generation circuit,
A number of the top of the partial product A from the multiplication array
Bits, and the number of bits of the upper part of the partial product B minus 1
The exclusive OR of each bit of the
The total logical product F0 is calculated, and the exclusive
Logical sum and logical sum of bits of lower digits (least significant bit
Or the logical product of the bits of the lower digits.
Other logical OR is calculated, and the total logical product F1 of the results is calculated,
If carry F is 0, select F0 and carry F
If it is 1, F1 is selected as the normalized signal G after rounding.
A rounded normalization determination circuit that outputs the above, a lower bit that is obtained by removing the upper part of the upper part of the partial product A from the multiplication array, and a number of the arbitrary number-1 that is higher than the partial product B The lower bit excluding the part is input, and a sticky bit circuit that generates and outputs a sticky bit S that becomes 1 when there is a bit that becomes 1 in the addition result, the addition result C0 from the multiplication array, and the addition The result C1 is input, and the addition result C0 is obtained according to the carry X from the mantissa adder, the post-rounding normalized signal G from the post-rounding normalization determination circuit, and the sticky bit S from the sticky generating circuit. , Addition result C1, or 1
00 ... 00 is selected and output as the mantissa multiplication result, and the exponent addition result D0 and the exponent addition result D1 are input from the exponent adder, and the mantissa adder outputs Either the exponent part addition result D0 or the exponent part addition result D1 is selected according to the carry X, the post-rounding normalization signal G from the post-rounding normalization determination circuit, and the sticky bit S from the sticky generating circuit. Then
And a rounding digit matching circuit that outputs a result of multiplication of exponent part, and a floating point multiplier. 3. A multiplication array which inputs a mantissa M0 and a mantissa M1 and performs multiplication to output a partial product A and a partial product B, an arbitrary number of bits higher than the partial product A from the multiplication array, and a partial product. A mantissa for inputting the bit of the arbitrary number -1 above B, performing addition, and outputting addition result C0, addition result C1 obtained by adding 1 to addition result C0, and carry X0, X1 from the most significant digit. A partial adder, a lower bit of the multiplication array excluding the upper part of the partial product A and a lower bit of the upper part of the partial product B excluding the part of the arbitrary number -1 A carry generation circuit that inputs and outputs the carry F from the most significant bit, and the arbitrary number of bits above the partial product A and the above arbitrary number above the partial product B from the multiplication array. 1 bit and the carry generation time Enter carry F from the road,
Exclusive OR of each of the arbitrary number of bits higher than the partial product A and the arbitrary number -1 bit higher of the partial product B from the multiplication array is calculated, and the total logical result is obtained. The product F0 is calculated, and the exclusive OR of each bit and the logical sum of the bits of the lower digits (only the least significant) or the logical product of the bits of the lower digits is calculated. Then, the total logical product F1 of the results is calculated,
If the carry F is 0, F0 is selected, and if the carry F is 1, F1 is selected and a post-rounding normalization determination circuit that outputs the post-rounding normalized signal G and a partial product from the multiplication array are selected. Input the lower bits excluding the arbitrary number of upper parts of A and the lower bits excluding the upper part of the arbitrary number −1 of partial products B, and add 1 to the addition result. The sticky bit S which becomes 1 when the bit is present, and the sticky bit generating circuit that outputs the sticky bit S and the addition result C0 and the addition result C1 from the multiplication array are input.
And carry X0 = 0 and X1 = 0, respectively
Select addition result C0 and addition result C1 and carry X0 =
If 1, and X1 = 1, then “1, addition result C0
Remaining after removal of the least significant bit of = "addition result C3,
"1, remaining after deleting the least significant bit of addition result C1" =
Select the addition result C4, then the sticky bit S
If it is 0, the addition result C3 is selected and the sticky bit is selected.
If S is 1 and the normalized signal G after rounding is 0,
Select the calculation result C4, and if the sticky bit S is 1,
If the normalized signal G after rounding is 1, 100 ... 0
A floating point multiplier comprising: a rounding digit matching circuit that selects 0 and outputs the result as a mantissa multiplication result . 4. An exponent part adder for generating and outputting an exponent part addition result D0 and an exponent part addition result D1 obtained by adding 1 to the exponent part addition result D0 and an exponent part addition result D0, and a mantissa M0. , A mantissa M1 is input and multiplication is performed to output a partial product A and a partial product B, an arbitrary number of bits higher than the partial product A from the multiplication array, and the arbitrary upper bit of the partial product B. A mantissa adder which inputs the bits of the number -1 and performs addition to output an addition result C0, an addition result C1 obtained by adding 1 to the addition result C0, and carry X0, X1 from the most significant digit; Input the lower bits of the array that exclude the upper part of the arbitrary number of partial products A and the lower bits of the upper part of the partial product B that exclude the upper part of the arbitrary number −1, Carry that generates and outputs carry F from the upper level A generation circuit, and inputs the arbitrary number of bits higher than the partial product A from the multiplication array, the arbitrary number −1 bits higher than the partial product B, and a carry F from the carry generation circuit;
Exclusive OR of each of the arbitrary number of bits higher than the partial product A and the arbitrary number -1 bit higher of the partial product B from the multiplication array is calculated, and the total logical result is obtained. The product F0 is calculated, and the exclusive OR of each bit and the logical sum of the bits of the lower digits (only the least significant) or the logical product of the bits of the lower digits is calculated. Then, the total logical product F1 of the results is calculated,
If the carry F is 0, F0 is selected, and if the carry F is 1, F1 is selected and a post-rounding normalization determination circuit that outputs the post-rounding normalized signal G and a partial product from the multiplication array are selected. Input the lower bits excluding the arbitrary number of upper parts of A and the lower bits excluding the upper part of the arbitrary number −1 of partial products B, and add 1 to the addition result. The sticky bit S which becomes 1 when the bit is present, and the sticky bit generating circuit that outputs the sticky bit S and the addition result C0 and the addition result C1 from the multiplication array are input.
Force and carry X0 = 0 and X1 = 0, respectively
Select addition result C0 and addition result C1 and carry X0 =
If 1, and X1 = 1, then “1, addition result C0
Remaining after removal of the least significant bit of = "addition result C3,
"1, remaining after deleting the least significant bit of addition result C1" =
Select the addition result C4, then the sticky bit S
If it is 0, the addition result C3 is selected and the sticky bit is selected.
If S is 1 and the normalized signal G after rounding is 0,
Select the calculation result C4, and if the sticky bit S is 1,
If the normalized signal G after rounding is 1, 100 ... 0
0 is selected and output as the mantissa multiplication result, and
Exponent part addition result D0, exponent part addition result from exponent part adder
Enter D1 (carry X0 = 0) * (sticky
Bit S = 0) or (carry X1 = 0) *
(Sticky bit S = 1) * (Rounded normalized signal G
= 0), select the exponent addition result D0, and
If not, the exponent part addition result D1 is selected and the exponent part multiplication result is selected.
Output as the result, select the exponent part addition result D1, and select the exponent part
A floating-point multiplier having: a rounding digit matching circuit that outputs a result of calculation ;