JPH05276043A - A/d converter - Google Patents

Abstract

PURPOSE:To reduce odd number order distortion generated in the track mode by providing a switch closed in the track mode of a track hold circuit and opened in the hold mode to the A/D converter. CONSTITUTION:Since a switch 6 is closed in the track mode, an input 22 of a programmable gain amplifier 2 is connected to a common potential point via the switch 6. In this case, a load impedance 3 of a track hold circuit 1 is RL+RS (RL is a resistance of a resistor 3 and RS is a resistance when the switch 6 is closed). That is, the load impedance in the track mode is always RL+RS in the output state of the circuit 1. Thus, even when the output resistor of the track hold circuit 1 is in existence, odd number order distortion caused in the track mode is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is used in a track and hold circuit of a subranging type analog-digital converter. In particular, the present invention relates to an analog-digital converter that can reduce odd-order harmonic distortion that occurs at the output of the track and hold circuit.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram of a conventional analog-digital converter. FIG. 8 is a diagram showing a change in the load impedance value in the track mode of the conventional analog-digital converter. FIG. 9 is a diagram for explaining generation of odd-order distortion in a conventional analog-digital converter. FIG. 10 is a block diagram of a programmable gain amplifier.

The operation of the three-step subranging type analog-digital converter will be briefly described with reference to FIGS. 7 and 10. The output (hold value) of the track hold circuit 1 is input to the input 21 of the programmable gain amplifier 2 and
/ 4 times [(1/32) × 8] (full scale of 6-bit analog-digital converter 7). The output of the programmable gain amplifier 2 is converted from analog to digital and latched by the gate array 8. The digital value of the 6-bit analog-digital converter 7 is input from the gate array 8 to the digital-analog converter 5 and converted into an analog value again. The residual signal between the output (hold value) of the track and hold circuit 1 and the output of the digital-analog converter 5 is input to the input 22 of the programmable gain amplifier 2 and multiplied by 8. The value obtained by multiplying the residual signal by 8 is again analog-digital converted by the 6-bit analog digital converter 7 and input to the digital-analog converter 5. To the input 22 of the programmable gain amplifier 2, the residual signal of the output of the track and hold circuit 1 and the value obtained by converting the analog-digital conversion value of two times into an analog value is input. This residual signal is multiplied by 256 (32 × 8) and again analog-digital converted.

As described above, the 6-bit analog-to-digital converter 7 performs 3-step analog-to-digital conversion to form a 16 (6 × 3-2) -bit analog-to-digital converter. Here, it is used twice to correct the overlap.

Conventionally, the analog-digital converter has a clamp circuit 4 for limiting the input voltage range of the programmable gain amplifier 2 between it and the programmable gain amplifier 2 connected to the track and hold circuit 1, as shown in FIG. Are connected. As shown in FIG. 8, in the track mode, the track hold circuit 1 operates as a normal non-inverting amplifier, but when the input amplitude becomes large, the load impedance 3 (impedance value RL) end is clamped and is not clamped. There are two states. From the viewpoint of the impedance of the load of the track and hold circuit 1, the load impedance value is RL in the clamped state, and the load impedance value is infinite in the unclamped state. In FIG. 8, the dotted line shows the output waveform of the track and hold circuit 1, and the solid line shows the input waveform of the input 22 of the programmable gain amplifier 2. As shown in FIG. 9A, when the output of the track and hold circuit 1 is provided with a resistor R ₀ (in the case of an IC or the like, it becomes about several Ω to several tens of Ω), the load impedance value changes and the result shown in FIG. Since the phase difference between the input and output fluctuates as shown in FIG. 9B and FIG. 9C, this difference in phase difference causes distortion (odd order). In FIG. 9B, the dotted line shows the output waveform of the track and hold circuit 1 when the load impedance value is infinite, and the alternate long and short dash line shows the load impedance value R.
The output waveform when L is shown.

[0006]

In such a conventional analog-digital converter, the load impedance value changes in the track mode and the phase difference between the input and the output fluctuates when the output has a resistor R _0. Then, there is a drawback that odd-order distortion is generated.

The present invention solves the above-mentioned drawbacks, and an object of the present invention is to provide an analog-digital converter capable of reducing the odd-order distortion generated in the track mode.

[0008]

SUMMARY OF THE INVENTION The present invention comprises a track and hold circuit for tracking and holding an input signal, and
A load impedance having one end connected to the output of the track-hold circuit, and a programmable gain having a first input connected to the output of the track-hold circuit and a second input connected to the other end of the load impedance. In an analog-digital converter including an amplifier, a clamp circuit connected to the other end of the load impedance, and a digital-analog circuit connected to the other end of the load impedance, the second of the programmable gain amplifier A switch that is inserted between the input and the common potential point and that is closed in the track mode of the track hold circuit and opened in the hold mode is provided.

[0009]

[Function] The switch is inserted between the second input of the programmable gain amplifier and the common potential point to open and close in synchronization with the switching timing of the track and hold modes of the track and hold circuit, and closed in the track mode. Connect the second input to the common potential point.

As described above, the odd-order distortion generated in the track mode can be reduced.

[0011]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an analog-digital converter according to an embodiment of the present invention.

In FIG. 1, the analog-digital converter includes a track-hold circuit 1 for tracking and holding an input signal, and a load impedance 3 (an impedance value of 625Ω) having one end connected to the output of the track-hold circuit 1. And an input 21 is connected as a first input to the output of the track and hold circuit 1 and an input 22 is connected as a second input to the other end of the load impedance 3.
Programmable gain amplifier 2 to which is connected, and a clamp circuit 4 connected to the other end of the load impedance 3.
A digital-analog converter 5 connected to the other end of the load impedance 3, a 6-bit analog-digital converter 7 for analog-digital converting the analog output of the programmable gain amplifier 2, and an analog-digital converter 7. A gate array 8 for latching and delaying the digital output.

A feature of the present invention is that the switch 6 is inserted between the input 22 of the programmable gain amplifier 2 and the common potential point, and is closed during the track mode of the track and hold circuit 1 and open during the hold mode.
(Using DMOS-SW as a switching element).

The operation of the analog-digital converter having such a configuration will be described. FIG. 2 is a diagram showing a simulation result of the analog-digital converter of the present invention. FIG. 3 is a diagram showing experimental results of the analog-digital converter of the present invention. FIG. 4 is a diagram showing the operation of the output section of the track and hold circuit of the analog-digital converter of the present invention. FIG. 5 is a diagram showing a voltage waveform of the input (21) of the programmable gain amplifier of the analog-digital converter. FIG. 6 is a diagram showing a voltage waveform of the input (22) of the programmable gain amplifier of the analog-digital converter of the present invention.

In FIG. 4, FIG. 4A shows the output waveform of the track and hold circuit 1 (the dotted line shows the input waveform). In the hold mode, the digital-analog converter 5 causes the current ID to flow so that the voltage across the load impedance 3 in FIG. 4B becomes VA. The potential of the input 22 of the programmable gain amplifier becomes almost equal to the common potential.
The digital-analog converter 5 keeps the current I until the next hold.
Since D is kept flowing, (VB-V
When A) exceeds the clamp voltage (0.8 V),
As shown in (c), the input 22 of the programmable gain amplifier 2 is clamped at about 0.8V. Note that IC = (VB-0.8) / RL-ID.

The states of the output waveforms of the track and hold circuit 1 are shown in FIGS. 5 (a) -5 (c) and 6 (a) -6.
There are three types shown in (c). 5 (a) and 6 (a)
Is the input 2 of the programmable gain amplifier 2 in the track mode when the input frequency is high (> 50 kHz).
2 is clamped to about 0.8V. At this time, the load impedance of the track hold circuit 1 is 62
It is about 5Ω. 5B and 6B show the case where the input frequency is low, and the input 22 of the programmable gain amplifier 2 is always in the unclamped state in the track mode. At this time, the load impedance of the track hold circuit 1 becomes infinite. FIG. 5C and FIG. 6C show the case where the input frequency is high and the same voltage as the previous time is held. As can be seen from FIG. 6C, the clamp state is switched to the non-clamp state during the track mode. In the conventional technique, a phase difference occurs with a change in the load impedance value, and odd-order harmonic distortion occurs in the track mode. Since this value is held as it is, it becomes waveform distortion after analog-digital conversion.

In the present invention, the switch S is turned "on" or "off" by the track hold switching signal. Since the switch 6 is turned “on” in the track mode, the input 22 of the programmable gain amplifier is connected to the common potential point via the switch 3. At this time, the load impedance 2 of the track hold circuit 1 becomes (RL + RS). Where RS
Is a resistance value when the switch 6 is “on”.

That is, the load impedance in the track mode is always (RL + RS) and is constant in all the states of FIGS. 5 (a) to 5 (c) and 6 (a) to 6 (c).

When the track and hold circuit is composed of an IC, the resistance R ₀ is several Ω to several tens Ω due to contact resistance and bonding wire resistance.

[0020] Figure 2 shows the result in the case of f _in = 400kHz V _in = spice simulation in 8V _pp (SPICE simulation). In this embodiment, the odd-order distortion does not occur regardless of the value of the resistor R ₀ . Even if the resistance R ₀ is about 5Ω, it is improved by about 13 dB, which is a great improvement effect.

[0021] FIG. _{3, R 0 = 200Ω, f in} = 470k
The results of experiments at Hz and V _in = 7.2 V _pp are shown. The experimental results are after analog-digital conversion. Although the resistance R ₀ is large as in the simulation result, the odd-order distortion due to the change in the load impedance value is almost completely removed.

[0022]

As described above, according to the present invention, the load impedance value is always (RL + R) in the track mode.
Therefore, even if the output resistance of the track hold circuit is present, there is an excellent effect that the odd-order distortion generated in the track mode can be reduced.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of an analog-digital converter according to an embodiment of the present invention.

FIG. 2 is a diagram showing a simulation result of the analog-digital converter of the present invention.

FIG. 3 is a diagram showing an experimental result of the analog-digital converter of the present invention.

FIG. 4 is a diagram for explaining the operation of the output section of the track and hold circuit of the analog-digital converter of the present invention.

FIG. 5 is a diagram showing a voltage waveform of an input (21) of the programmable gain amplifier of the analog-digital converter of the present invention.

FIG. 6 is a diagram showing a voltage waveform of an input (22) of the programmable gain amplifier of the analog-digital converter of the present invention.

FIG. 7 is a block configuration diagram of a conventional analog-digital converter.

FIG. 8 is a diagram showing changes in the load impedance value in the track mode of the analog-digital converter of the conventional example.

FIG. 9 is a diagram for explaining generation of odd-order distortion in a conventional analog-digital converter.

FIG. 10 is a block configuration diagram of a programmable gain amplifier of an analog-digital converter.

[Explanation of symbols]

 1 Track-hold circuit 2 Programmable gain amplifier 3 Load impedance 4 Clamp circuit 5 Digital-analog converter 6 Switch 7 6-bit analog-digital converter 8 Gate array 21, 22 Input of programmable gain amplifier

Claims (1)

[Claims] 1. A track-hold circuit for tracking and holding an input signal, and a load impedance whose one end is connected to an output of the track-hold circuit,
A programmable gain amplifier having a first input connected to the output of the track-hold circuit and a second input connected to the other end of the load impedance, and a clamp circuit connected to the other end of the load impedance, In an analog-digital converter including a digital-analog circuit connected to the other end of the load impedance, a track mode of the track-hold circuit inserted between the second input of the programmable gain amplifier and a common potential point. An analog-digital converter, which is equipped with a switch that is sometimes closed and opened in hold mode.