JPH05275714A - Nonvolatile memory and its write method - Google Patents

Abstract

PURPOSE:To obtain a nonvolatile memory wherein it is provided with memory cells whose area can be reduced by a method wherein a plurality of memory cells have second impurity diffusion layers and first impurity diffusion layers in common. CONSTITUTION:Auxiliary gates 24 are formed on a semiconductor substrate 23 via an SiO2 film 20; floating gates 26a are formed on their sidewalls via an SiO2 film 25; control gates 28 are arranged and installed on them via an SiO2 film 27. Thereby, one memory cell is constituted. The control gates 28 are formed continuously to each other; a source 21 and a drain 22 as one pair are formed in individual memory cell groups R1, R2,... Consequently, the source and the drain are formed respectively in each memory cell; the source 21 and the drain 22 as one pair are formed in one memory cell group; a second electrode is connected, in common, to each memory cell in the memory cell groups. As a result, the area of the memory cell can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a highly integrated non-volatile memory and a method for writing the same, and more specifically, to an auxiliary gate (AUXILIARY) as a first electrode formed on a semiconductor substrate via an insulating film. GATE: hereinafter referred to as AG)
And a floating gate (hereinafter referred to as FG) formed on the sidewall of the AG via an insulating film, and a control gate (hereinafter referred to as CG) serving as a second electrode disposed at least on the FG via the insulating film. A large capacity in which a plurality of memory cells are arranged in a matrix in the X and Y directions, and adjacent memory cells share a source and a drain in the memory cell group formed in the X direction. Stack type flash EE suitable for
The present invention relates to a nonvolatile memory which is a PROM and a writing method thereof.

[0002]

2. Description of the Related Art As a memory cell of a non-volatile memory, for example, as shown in FIGS. 5 and 6, Si having a source 41 and a drain 42 is used.
The auxiliary gate A is formed on the substrate 43 via the gate insulating film 44.
Some have G45 formed. This auxiliary gate AG4
A floating gate FG46 is formed on the side wall of No. 5 via an insulating film 49. In addition, the floating gate FG 46 and the auxiliary gate AG are interposed via the insulating film 47.
A control gate CG48 is provided on the 45. A plurality of memory cells 40 are arranged in the X direction and the Y direction.
Are arranged in a matrix in the direction. In the memory cell group arranged in this manner, each memory cell naturally has the source 41 and the drain 42 individually.

The write characteristic of this memory cell 40 is shown in FIG.
Shown in. In FIG. 7, the vertical axis represents writing (program)
Later floating gate FG46 threshold voltage V _t
(Volt), and the horizontal axis represents the auxiliary gate voltage V _AG (volt). Further, V _d represents the drain voltage, and V _CG represents the voltage applied to the control gate. FIG. 6 is an equivalent circuit diagram of the memory cell of FIG. The number of electrons injected into the floating gate FG depends on the strength of the electric field in the channel direction. When the voltage applied to the auxiliary gate AG is increased, the channel current exponentially increases, but becomes saturated at the threshold voltage of the auxiliary gate AG or higher. On the other hand, the electric field decreases as V _AG increases. Therefore, the write efficiency is highest when the threshold voltage is applied to the auxiliary gate AG.

The present invention provides a non-volatile memory having a memory cell capable of reducing the area of a memory cell group and a writing method of a non-volatile memory which can be written by utilizing the above-mentioned writing characteristics even if the area of the memory cell is reduced. To do.

[0005]

According to the present invention, the first electrode formed on the semiconductor substrate, the floating gate formed on the side wall of the first electrode via the insulating film, and the insulating film A memory cell that is disposed on at least the floating gate via the second electrode and that can control the potential of the floating gate thereby, and the memory cell is arranged in a matrix in the X direction and the Y direction. A pair of the first impurity diffusion layer and the second impurity diffusion layer is formed so as to be shared by each of the memory cell groups each including at least two memory cells arranged in the matrix in the X direction. A non-volatile memory is provided in which a second electrode is commonly connected to each memory cell of the memory cell group.

In addition, a voltage close to the threshold voltage is applied only to the first electrode of the memory cell in which writing is performed in the above-mentioned nonvolatile memory, and another voltage in the memory cell group including the memory cell in which writing is performed A non-volatile memory writing method is provided in which writing is performed in a desired memory cell by applying a voltage sufficiently higher than a threshold voltage to the first electrode of the memory cell.

The non-volatile memory of the present invention has, for example, as shown in FIG. 2, a memory cell C1, a memory cell C2,
The memory cell group has a memory cell C3 and a memory cell C4, and each memory cell has the above-described write characteristic as shown in FIG. A pair of a first impurity diffusion layer 21 and a second impurity diffusion layer 22 are formed at both ends of a memory cell group composed of parallel memory cells.

That is, a plurality of memory cells forming this memory cell group share the second impurity diffusion layer and the first impurity diffusion layer, and each memory cell individually has the first impurity diffusion layer and the second impurity diffusion layer. Since it has no impurity diffusion layer, the area of the memory cell can be further reduced. And
At the time of writing, the potentials of the second impurity diffusion layer and the first impurity diffusion layer are applied only to the diffusion layers located at both ends of the memory cell group. For example, when the memory cell group connected in the X direction is composed of four memory cells C1, C2, C3 and C4 as shown in FIGS. 2 and 3, the write potential is set to the first of the memory cell groups. Impurity diffusion layer 21
And writing to only the second impurity diffusion layer 22 realizes writing to an arbitrary memory cell. Therefore, in the nonvolatile memory of the present invention, one-eighth of one memory cell is formed as compared with the case where one memory cell 40 shown in FIGS. 5 and 6 is formed of one transistor. It is possible to write to one transistor in the area of. Moreover, writing to individual memory cells is possible.

[0009]

Embodiments of the nonvolatile memory of the present invention will be described below. The invention is not limited to this. As shown in FIGS. 1 to 3, the nonvolatile memory has a SiO ₂ film (insulating film) 2 on the semiconductor substrate 23.
Auxiliary gate AG (first electrode) 24 is formed via 0, and a floating gate FG 26a is formed on the side wall of this auxiliary gate AG24 via SiO ₂ film (insulating film) 25. Further, the SiO ₂ film (insulating film) 27 is formed on the auxiliary gate AG 24 and the floating gate FG 26 a.
A control gate (second electrode) CG28 is arranged through the above to form one memory cell. Then, n such memory cells are provided in the X direction to form a memory cell group R _1, R _2, ... R _n . Further, the control gates CG28 arranged in the memory cells forming one memory cell group are formed continuously with each other, and each memory cell group has a pair of sources (first impurity diffusion layers). 21 and drain (second impurity diffusion layer)
22 is formed. Further, these memory cell groups are sequentially arranged in the Y-axis direction and arranged in a matrix.

As shown in FIG. 2, a case where one memory cell group R ₁ is composed of four memory cells C1, C2, C3, C4 will be described. Source and drain are not formed respectively, and a pair of source 21 and drain 22 are formed in one memory cell group. As a result, the area of the memory cell group can be reduced.

The writing method of the nonvolatile memory of the present invention will be described below. Four memory cells C1, C2, C3,
Each C4 has a write characteristic as shown in FIG. Utilizing this, it is desired to apply a source / drain voltage only to both ends of n memory cells C1, C2, C3, C4, ... Cn arranged in parallel in the X direction under one CG 28 and perform writing. A voltage of 2 V is applied only to the AG of the memory cell, and a voltage of 6 V or more is applied to the rest.

For example, as shown in Table 1, the memory cell C
Applying a voltage of 2 volts to the AG of 1 and the AG of C2, C3, C4
6V to CG, 12V to CG and 5V to drain.

[0013]

[Table 1] By applying the voltage in this manner, the memory cell C1
You can write to Moreover, this writing is possible in each memory cell by applying a voltage close to the threshold voltage to AG of an arbitrary memory cell. Further, another embodiment is shown in FIG.

In the nonvolatile memory in this case, an auxiliary gate AG (first electrode) 24 is formed on a semiconductor substrate 23 with a SiO ₂ film (insulating film) 20 interposed therebetween.
A floating gate FG 26 is formed on the sidewall of 24 with a SiO ₂ film (insulating film) 25 interposed therebetween. In addition, on the auxiliary gate AG24 and the floating gate FG26,
A control gate (second electrode) CG 28 is arranged via a SiO ₂ film (insulating film) 27 to form one memory cell. Then, such a memory cell is n
They are individually provided and constitute a memory cell group. Further, the control gates CG28 arranged in the memory cells forming one memory cell group are formed continuously with each other, and each memory cell group has a pair of sources (first impurity diffusion layers). 21 and a drain (second impurity diffusion layer) 22 are formed. Further, these memory cell groups are sequentially arranged in the Y-axis direction and arranged in a matrix.

In such a non-volatile memory, for example, after forming the SiO ₂ film 20 on the semiconductor substrate 23, the auxiliary gate AG (first electrode) 24 is formed by a known method. Then, SiO is formed on the side wall of the auxiliary gate AG24.
_Two films (insulating film) 25 are formed. After that, auxiliary gate A
Between the G24 and the auxiliary gate AG24, for example, polysilicon having the same thickness as that of the auxiliary gate AG24 is embedded, and the entire surface is etched so that the polysilicon is left only between the auxiliary gate AG24 and the auxiliary gate AG24. As a result, the floating gate FG26 can be formed. After that, the non-volatile memory can be manufactured by the same method as the above-mentioned method for manufacturing the non-volatile memory.

[0016]

According to the nonvolatile memory of the present invention, the first electrode formed on the semiconductor substrate, the floating gate formed on the side wall of the first electrode via the insulating film, and the insulating film via the insulating film. And a second electrode capable of controlling the potential of the floating gate thereby disposed on at least the floating gate, the memory cells being arranged in a matrix in the X and Y directions to form a pair. Of the first impurity diffusion layer and the second impurity diffusion layer of at least 2 arranged in the matrix in the X direction.
The memory cell group is formed so as to be shared by each memory cell group including one or more memory cells, and the second electrode is commonly connected to each memory cell of the memory cell group, so that the area of the memory cell is further reduced. be able to.

Further, a voltage close to the threshold voltage is applied only to the first electrode of the memory cell in which writing is performed in the above-mentioned nonvolatile memory, and another voltage in the memory cell group including the memory cell in which writing is performed By writing a voltage in a desired memory cell by applying a voltage sufficiently higher than the threshold voltage to the first electrode of the memory cell, writing can be performed in each memory cell.

[Brief description of drawings]

FIG. 1 is a plan view showing the overall configuration of an embodiment of a non-volatile memory of the present invention.

FIG. 2 is a sectional view taken along line II-II in FIG.

FIG. 3 is an equivalent circuit diagram of FIG.

FIG. 4 is a schematic cross-sectional view of a main part showing another embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view of a main part showing an embodiment of a conventional nonvolatile memory.

FIG. 6 is an equivalent circuit diagram of FIG.

FIG. 7 is a diagram showing characteristics of a nonvolatile memory after writing.

[Description of Reference Signs] 21 source (first impurity diffusion layer) 22 drain (second impurity diffusion layer) 23 Si substrate 24 auxiliary gate (first electrode) 26a, 26b floating gate 28 control gate (second electrode)

Claims (2)

[Claims] 1. A first electrode formed on a semiconductor substrate,
A memory including a floating gate formed on the sidewall of the first electrode via an insulating film, and a second electrode disposed on the floating gate at least via the insulating film and capable of controlling the potential of the floating gate. At least two memory cells, the memory cells being arranged in a matrix in the X direction and the Y direction, and a pair of a first impurity diffusion layer and a second impurity diffusion layer being arranged in the matrix X direction. A non-volatile memory, which is formed so as to be shared by each of the memory cell groups including the above memory cells, and further has a second electrode commonly connected to each memory cell of the memory cell group. 2. A non-volatile memory according to claim 1, wherein a voltage close to a threshold voltage is applied only to a first electrode of a memory cell for writing, and a memory cell group including the memory cell for writing is applied. By applying a voltage sufficiently higher than the threshold voltage to the first electrode of the other memory cell of
A method for writing to a non-volatile memory, characterized by writing to a desired memory cell.