JPH05265748A - Integrated circuit microprocessor provided with plural controllers of different control systems - Google Patents

Abstract

PURPOSE:To control an integrated circuit microprocessor having an extremely large number of instructions, e.g. about 600 instructions or more by means of a control system accordant with each type of instructions. CONSTITUTION:This microprocessor is provided with a data path device 102 to store and process the data, and controllers which give the instructions of the arithmetic operations, the storage, etc., to the data path device 102 based on a prescribed procedure after decoding the machine word instructions. A 1st controller 203 applies the random logic and a 2nd controller 204 applies a PLA control system respectively. An internal address selecting device 202 gives selectively the control right of the supplied instructions to an instruction decoding device 104 and the controller 203 or 204. Then, an internal address multiplexer device 201 takes out the output of the device having the control right at the side of the device 102.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit microprocessor, and more particularly, it connects a data path device for storing and processing data in a microprocessor and a control device for controlling a processing procedure. It is about the part to do.

[0002]

2. Description of the Related Art A general integrated circuit microprocessor is a register, which is a means for storing and processing data.
A data path device in which storage and arithmetic circuit groups such as a file device and an ALU device are coupled by an internal bus, and a control device which decodes machine language instructions and gives instructions to the data path device such as arithmetic and storage according to a predetermined procedure. Includes two major devices.

Conventionally, as a control device for an integrated circuit microprocessor, a microcode control system, a random logic circuit system, a PLA control system, etc. have been proposed and put to practical use. However, it is widely accepted that each method has advantages and disadvantages.

For example, the microcode control method has an advantage that the hardware amount and complexity required for the control can be reduced by executing the complicated control by the firmware by the microprogramming, but generally the control takes time. It is said that there is. Further, the random logic circuit system is capable of high-speed control, but is suitable for simple control, and it is said that the hardware tends to become bulky and the speed thereof tends to decrease if complicated control is attempted.

On the other hand, in the PLA control system, the control device can be constructed very flexibly, and the hardware can be simplified. However, although it is fast in a small scale, the circuit speed is significantly reduced in a large scale. It is said that there is a drawback that the area per unit memory bit is large when compared with the microcode control method.

[0006]

Therefore, in an integrated circuit microprocessor having a large number of instruction groups, from an instruction that can be realized by simple control to an instruction that requires complicated control, a very large number of instructions are required. When the processing is performed by one data path device, there is a problem that the amount of hardware increases or the processing speed decreases, whichever control method is used.

In view of this point, an object of the present invention is to realize an integrated circuit microprocessor capable of processing a large number of instructions without causing the above-mentioned harmful effects.

[0008]

To achieve the above objects, the present invention in particular requires an integrated circuit microprocessor in which a very large number of instruction types must be processed for a single datapath device. In the above, a plurality of control devices suitable for each instruction are prepared, the control right is switched between the control devices according to the type of instruction to be executed, and the optimum control is performed by the hardware suitable for controlling each instruction. Trying to get.

That is, the present invention provides a data path device for storing and processing data, and a control device for decoding a machine language instruction and giving instructions such as calculation and storage to the data path device according to a predetermined procedure. In the integrated circuit microprocessor having the above-mentioned control device, at least first and second control devices having different control methods included in the control device, and a control right of the command according to the supplied machine language command are given to the first and second control devices. Control right granting means for selectively granting one of the second control devices, and control for supplying the output of the control device to which the control right is granted by the control right granting means to the data path device side. A configuration having output switching means is adopted.

Here, the control system of the first and second control devices may be any one of a microcode control system, a random logic circuit system and a PLA control system, for example.

Further, in implementing the present invention, an instruction decoding device and the above-mentioned first and second control devices are adopted as the control device, and based on the decoding result of the machine language instruction by the instruction decoding device, The command control right may be given to any one of these control devices.

As an example, when the first control device is a control device based on a random logic circuit system and the second control device is a control device based on a PLA control system, the instruction group of the integrated circuit microprocessor is provided. Of these, the control right of the instruction group that can perform high-speed processing by relatively simple sequence processing is given to the first control device, and the control right of the instruction group that requires complicated sequence processing that must be slowed down. May be configured to be applied to the second control device.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. The embodiment shown in the drawing is an integrated circuit that includes a 32-bit wide arithmetic unit manufactured by a CMOS process technology and a 32-bit wide internal data bus, and can exchange data with an external device by a 16-bit wide external data bus. The present invention is applied to a microprocessor.

Overall Configuration FIG. 1 is a block diagram showing an outline of the overall integrated circuit microprocessor 1.

A bus interface device 100 connects the integrated circuit microprocessor 1 on the integrated circuit to an external storage device and an I / O device (not shown). This device 100 has an external address bus S100 that can specify a storage device of 4 Gbytes and an I / O device of 64 Kbytes, and external data S103 that can read and write a maximum of 16 bits of data or read a machine language instruction at a time. An interface with an external device is provided by a control output bus S101 for notifying the external device of the bus, the type and timing of the bus operation, and a control input bus S102 for requesting the bus operation from the external device. The device 100 is a device that can operate independently of an instruction execution device 101 which is a main part of the integrated circuit microprocessor 1.

Reference numeral 101 denotes an integrated circuit microprocessor 1.
Is the central instruction execution device. Each of the components 102, 103, 104, and 105 described later is included as a main device inside. The present device 101 is different from the bus interface device 100 in that it has an internal 32-bit width memory address bus S104, an internal 32-bit width data bus S105, an internal control output bus S106, and S10.
They are connected by an internal control input bus 7 and an internal 32-bit wide machine language code dedicated bus S108.

Reference numeral 102 is an internal register address decoding device coupled to the data path device and each part of the data path device. Controlled by an internal address bus S109 coupled to an internal register address decode device. The internal details will be described later with reference to FIG.

Reference numeral 103 denotes an internal address multiplexer device and an internal address selection control device. The internal address multiplexer device is controlled by the control signal group S from other devices.
Only one set of the internal address information sent via 110 and the control signal group S113 is sent to the internal address bus S109. The internal address selection controller is
It controls the internal address multiplexer device,
Again, the control signal group S110 and the control signal group S113
It receives the control right information sent via the command line and instructs the internal address multiplexer device to make an appropriate selection, and uses the control signal groups S111 and S114 to inform the control right to another.

FIG. 2 shows the details of the main part centering on this device.
The selection logic of the internal address selection control device is shown in FIG.

Reference numeral 104 is a machine language instruction decoding device. The machine language instruction fetched from the storage device through the external data bus S103 is a machine language code dedicated bus S108.
It is input to this device via and decoded.

In the case of an instruction in which a register or the like is specified in the machine language instruction code, it is converted into an internal address in the decoding process of this apparatus and sent through the control signal group S110.
The decoded command converted into the fixed length format is transmitted to the control device 105 described below via the signal group S112.

Reference numeral 105 is a control device for controlling the execution of instructions. In the case of the present embodiment, the control device based on random logic and the control device based on PLA are included inside. The decoded instruction converted into the fixed length format sent from the machine language instruction decoding device 104 via the signal line S112 is supplied to both internal devices. Details of the configuration are shown in FIG. FIG. 4 shows the configuration of the control device using PLA.

Configuration of Devices 103, 104 and 105 FIG. 2 is a block diagram for explaining the details of the configuration of a portion corresponding to the devices 103, 104 and 105 of FIG.

The signal group collectively shown as the control signal group S113 in FIG. 1 is represented as two signal groups S201 and S203 corresponding to the output source in this figure. In addition, the signal group collectively shown as the control signal group S114 in FIG. 1 is represented as two signal groups S202 and S204 corresponding to the input destination in this figure.

Reference numeral 201 denotes an internal address multiplexer device of the device 103. S110, S201,
One set of internal addresses appears in each of the three signal groups in S203. The present device 201 is a multiplexer configured to select only one set of internal addresses among the three sets and connect the selected internal address to the internal address bus S109. The selection instruction is given by the signal S200 output from the internal address selection device 202 described below.

Reference numeral 202 denotes an internal address selection device of the device 103. The device 202 includes 104, 203,
S110, S201, S2 from each device of 204
The internal address and its additional information sent through each signal group of No. 03 are monitored, and the control right is given to one of them according to the logic shown in FIG. When changing the device to which the control right is given, the device 202 is
The transfer of the control right is notified to the device that loses the control right and the device that obtains the control right through the signal groups 11, S202 and S204.

Reference numeral 104 is a machine language instruction decoding device also shown in FIG. The device 104 generates an internal address from the decoded machine language instruction and transmits it to the internal address multiplexer device 201 via the control signal group S110. Very simple instructions are processed only on this path.

Reference numeral 203 denotes a first control device of the control device 105 which is realized by random logic. Signal group S
Upon receiving a fixed-length decoded command via 112, the signal group S
The internal address information is sent to 201. This device 203
Is responsible for only those instructions that require relatively simple sequence processing and are capable of high-speed processing.

Reference numeral 204 is a second control device of the control device 105, which is realized by the PLA. Signal group S112
The internal address information is sent to the signal group S203 upon receipt of the fixed length decoded command via. The device 204 is in charge of only instructions that require complicated sequence processing that must be relatively slow.

Configuration of Device 102 FIG. 3 is a block diagram illustrating in detail the internal configuration of the datapath device and the internal register address decode device represented as device 102 in FIG.

The data path device portion of device 102 is comprised of portions 300, 302, 304, 306, 308. Each part of the data path device is S300
And S301 or S307 and S308 are each coupled by an internal data bus having a width of 32 bits. From the memory / address calculation device 300 to S1
The internal memory address bus 04 is output. An internal data bus S105 is coupled to the bus coupler device 302.

On the other hand, internal registers in the device 102
The parts of the address decoding device correspond to the parts of the data path device 301, 303, 305, 307,
309 is composed of each part. Both parts are S10
9 to the internal register address bus and decodes the internal register address to control each part of the datapath device. The internal register address is not limited to simply specifying the register address, but operations such as reading and writing are also encoded and included in the address information.
The internal register address decoding device also generates control signals and timing signals necessary for these operations.

Next, the respective parts constituting the above-mentioned data path device and internal register address decoding device will be described.

Reference numeral 300 is a memory address calculation device which internally has a 32-bit width adder and a register file for memory address calculation. A bus coupler device 302 interconnects two sets of internal buses and internal data buses. A counter device 304 includes a 32-bit width incrementer / decrementer and a plurality of registers. Reference numeral 306 denotes an internal arithmetic logic operation unit having a width of 32 bits, a barrel shifter, and a serial
It is an arithmetic unit having a plurality of temporary registers including a shift register. A register file device 308 internally includes 34 general-purpose registers having a 32-bit width and a control register.

On the other hand, 301 is a first internal register address decoder for controlling the memory address calculation device. The decoding result is transmitted through the signal group S302. Reference numeral 303 denotes a second internal register address decoder for controlling the bus coupler device 302. The decoding result is transmitted through the signal group S303. 305 is a third internal register address decoder for controlling the counter device 304. The decoding result is transmitted through the signal group S304. 307
Is a fourth internal register address decoder for controlling the arithmetic unit 306. The decoding result is transmitted through the signal group S305. 309 is a fifth internal register address decoder for controlling the register file device 308. The decoding result is the signal group S
It is transmitted through 306.

Configuration of Second Controller 204 FIG. 4 shows a PL represented as second controller 204.
3 is a block diagram for explaining a control device realized as a finite state machine using A. FIG.

400 is a temporary storage device for latching the input to the PLA-and-plane. This device has S
A part of the fixed length decoded command 112, the control right selection information S204, and the PLA feedback S404 are input, and they are sent through the signal group S401.

Reference numeral 401 denotes a PLA-and-plane, which comprises NMOS transistors connected in series and a precharge / discharge circuit for controlling them. The output is sent through the signal group S403.

Reference numeral 402 denotes a PLA-or plane, which is composed of parallel-coupled NMOS transistors and a precharge / discharge circuit for controlling them. The output is sent through the signal group S402.

403 is a temporary storage device for latching the output of the PLA-or plane. Part of the stored content is sent to the signal group S404 as feedback,
A part of the signal group S20 is used as an internal register address.
Sent to 3.

Control Right Transfer Operation FIG. 5 is a state transition diagram for explaining a selection operation performed by the internal address selection device 202 for transferring the control right.

C1 shows a state in which the instruction decoding device 104 is selected in FIG. C2 indicates a state in which the first control device 203 is selected in FIG. C3 is shown in FIG.
Shows the state where the second control device 204 is selected.

T100 indicates the initialization of the logic under a special condition such as reset or interrupt, and under such a condition, the state is always started from the state of C1. T101 is
This is a case where the control is advanced only by the instruction decoding device 104. T102 is the case where the instruction decoding device 104 transfers the control right to the first control device 203 after decoding. T10
3 is a case where the first control unit 203 transfers the control right to the instruction decoding unit 104 to start a new instruction after executing the instruction control. T104 is a case where the first control device 203 holds the control right for realizing the instruction sequence. T105 is the case where the instruction decoding device 104 transfers the control right to the second control device 204 after the decoding.
T106 is a case where the second control device 204 executes the instruction control and then transfers the control right to the instruction decoding device to start a new instruction. T107 is the second control device 204
Holds the control right to realize the instruction sequence.

In the present embodiment, the instruction decoding unit 104 includes the control unit 105 (20) in terms of machine language instructions.
(3, 204), the control right is always returned from the control device that has transferred the control.
The following transitions of T108 and T109 are transitions that occur only when C2 is called from C3 by a subroutine in a complicated sequence.

At T108, after the second control unit 204 executes the command control, the first control unit 2 starts to start the routine processing.
In this case, the control right is temporarily transferred to 03. T109 is
After the control of the routine process by the first control device 203 is completed,
In this case, the control right is returned to the second control device 204.

[0046]

According to the present invention, in the integrated circuit microprocessor, a plurality of control devices of a system suitable for each instruction are prepared, and the control right is switched between the control devices according to the type of the instruction to be executed. Optimal control is obtained by hardware suitable for controlling each instruction.
Therefore, according to the present invention, a controller of an integrated circuit microprocessor having a very large number of instructions, for example, about 600 or more instructions can be configured by combining a plurality of relatively simple controllers. Further, since a control method suitable for the type of instruction can be used, there is an advantage that the processing speed can be prevented from lowering due to control overhead.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing an overall configuration of an integrated circuit microprocessor to which the present invention has been applied.

FIG. 2 is a block diagram showing a configuration of a part of devices 103, 104 and 105 in FIG.

3 is a block diagram showing a configuration of a part of a device 102 in FIG.

4 is a block diagram showing a configuration of a second control device 204 in FIG.

5 is a state transition diagram showing a control right transfer operation by the integrated circuit microprocessor of FIG. 1;

[Explanation of symbols]

1 ... Integrated Circuit Microprocessor 100 ... Bus Interface Device 101 ... Instruction Execution Device 102 ... Data Path Device / Internal Register Address Decoding Device 103 ... Internal Address Multiplexer Device / Internal Address Selection control device 104 ... Machine language instruction decoding device (control device) 105 ... Control device 201 ... Internal address multiplexer device 202 ... Internal address selection device 203 ... First control device 204. ..Second control device

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location G06F 15/78 510 Z 7530-5L

Claims (5)

[Claims] 1. An integrated circuit having a data path device for storing and processing data, and a control device for decoding a machine language instruction and giving instructions such as calculation and storage to the data path device according to a predetermined procedure. In the microprocessor, at least first and second control devices having different control methods included in the control device, and a control right of the command according to the supplied machine language command,
Control right granting means for selectively granting to either one of the first and second control devices, and the output of the control device to which the control right is granted by the control right granting means And a control output switching means for supplying to the integrated circuit microprocessor. 2. The method according to claim 1, wherein the first and second
The control system of the control device is any one of a microcode control system, a random logic circuit system and a PLA control system. 3. A machine language instruction according to claim 1, further comprising an instruction decoding device and the first and second control devices as a control device, wherein the control right giving means is a machine language instruction by the instruction decoding device. The integrated circuit is configured to select which of the instruction decoding device and the first and second control devices the control right of the instruction is given based on the decoding result of the integrated circuit. Microprocessor. 4. The control device according to claim 3, wherein the first control device is a control device according to a random logic circuit system, and the second control device is a control device according to a PLA control system.
The control right granting means grants the control right of the simplest instruction group among the instruction groups of the integrated circuit microprocessor to the instruction decoding device, and the instruction capable of high-speed processing by relatively simple sequence processing. Group control right to the first
Integrated circuit microprocessor for giving a control right to the second control device, which is given to the second control device and which requires a complicated sequence process that must be slowed down. .. 5. An integrated circuit microprocessor configured by CMOS circuit technology, comprising: a data path device including at least a general-purpose register file and an arithmetic logic unit; and a data path device connected to the data path device. Internal register address decoding device that specifies the desired register from among the plurality of registers in this, and connect to this internal register address decoding device,
An internal address multiplexer device for supplying only a predetermined internal address from a plurality of internal address generation sources to the internal register address decoding device, and an internal address multiplexer device connected to the internal address multiplexer device, and at least one internal address for each of the internal address multiplexer devices. A plurality of control devices that can be generated and each of which operates as an independent finite state machine and have different control schemes; the internal address multiplexer device; and at least one or more of the control devices, An internal address selection device for processing the internal address connection request signal supplied from the control device and for instructing the internal address multiplexer device to supply an appropriate internal address to the internal address decoding device. Featured integrated circuit micro pro Tsu support.