JPH05259903A - Frequency synthesizer - Google Patents

Abstract

PURPOSE:To keep the high precision of the frequency and also to simplify the hardware constitution by deviating the frequency of a reference frequency oscillator based on the data given from a controller and monitoring the varied frequency value. CONSTITUTION:The recognized data are sent to a data holder 8 from a controller 7 which recognizes a deviating extent DELTAf so that the frequency of a reference frequency oscillator 1 is deviated by DELTAf. The data outputted from the holder 8 are converted into the analog voltage by a D/A converter 9 and inputted to the frequency control terminal of the oscillator 1 via a higher harmonic component eliminating LPF 10. Meanwhile a loop circuit is formed to monitor a process where the oscillator 1 is correctly deviated by DELTAf under the control of a controller 7 and transmits an error to the controller 7 against the DELTAf to converge the error during the monitoring process. Then the controller 7 monitors the difference frequency data to check whether the desired difference frequency is secured or not. If not, the data given to the holder 8 are changed so that the output frequency of the oscillator 1 is set at a normal level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer used in a frequency division multiplex communication device.

[0002]

2. Description of the Related Art Generally, in a frequency division multiplex communication system in wireless communication, especially in satellite communication, a plurality of frequency-divided slot frequencies are defined within an IF frequency pass band. For example, if the IF frequency is 70 MHz, the communication band is ±
It is 18 MHz, and at 140 MHz, it is ± 36 MHz. The step of this slot frequency is 7
Centered at 0 and 140MHz, 22.5KH
It is a z step. However, 70MHz and 1
Since 40 MHz is not an integral multiple of 22.5 KHz, it is not possible to configure a frequency synthesizer with 22.5 KHz steps with one voltage controlled oscillator. Now, assuming that the frequency difference from 22.5 KHz is Δf, the characteristics are obtained by mixing these oscillation frequencies using another oscillator that eliminates this Δf.

A conventional frequency synthesizer of this type is shown in FIG.
Will be explained. The voltage controlled oscillator (VCO) 4 output is
Divided into two by the divider 5, one of which is input to the frequency divider 6,
Here, after the output frequency of the VCO 4 is 1 / N, it is input to the phase error detector 2 together with the reference frequency of 22.5 KHz from the reference frequency oscillator 1. Phase error detector 2
Detects the phase error of these frequencies, and this error signal is input to the VCO 4 through the loop filter 3.
The output frequency of VCO4 is (70M + Δf) ± N · 2
2.5 KHz frequency divider 6 by controller (CONT) 7
The output signal is taken out at an interval of 22.5 KHz around 70 MHz + Δf by changing the value of N of. The output of the VCO 4 obtained in this way passes through the distributor 5 and the mixer 22 cancels this Δf at a frequency (for example, 2).
It is mixed with the frequency of the oscillator 21 which generates 2.5 KHz-Δf). Therefore, at the mixer 22 output, I
22.5 as the center of F 70MHz or 140MHz
An output signal with frequencies in KHz intervals is obtained. However, since the output signal 30 of the mixer 22 generates an image frequency and spurious at intervals of the oscillation frequency of the oscillator 21, the second PLL circuit 29 is used to remove them.

Next, as the PLL circuit, the frequency divider 23
To the phase error detector (P
D) is input to 24. PD24 is VCO26
The output of is passed through the distributor 27 and is input through the frequency divider 28. The PD 24 detects the phase error between these two signals, and the error signal passes through the loop filter 25 and becomes VCO.
26 control voltage signal.

As described above, the output of the mixer 22 is
The image frequency and spurious are removed by the band of the loop filter 25 by the second PLL circuit 29 in the next stage, and the desired signal is obtained from the output of the distributor 27 as the frequency synthesizer output.

[0006]

The conventional frequency synthesizer described above has an IF of 70 MHz or 140 MHz.
In order to realize a frequency step of 22.5 KHz intervals at the center, a local oscillator is required in addition to the voltage controlled oscillator, and a second PLL circuit 29 is provided to remove unnecessary waves such as spurious generated from the mixer. Since it is necessary, there is a drawback that the circuit scale becomes large.

[0007]

A frequency synthesizer of the present invention is a frequency synthesizer which changes a desired output frequency fI in steps of a shift frequency f0, wherein the output frequency fI is 1 / N (N is an integer of 2 or more). ) F0 ± Δf (Δ which is the reference frequency when comparing the phase with the divided signal
f = | Nf0−fI | / N), reference frequency generating means, control means for controlling the reference frequency generating means so that the frequency signal is Δf, and output frequency of the reference frequency generating means is monitored. If there is a deviation from the frequency signal of Δf, a monitoring means for transmitting the deviation frequency to the control means and performing a control operation is provided.

[0008]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the frequency synthesizer of the present invention. 1, the same reference numerals as those in the conventional example of FIG. 2 have the same configurations and functions. In the present embodiment, the second PLL circuit 29 of the conventional example is eliminated, and a new data holder 8,
17, digital-analog converter 9, low-pass filter 1
0, 13, a reference frequency oscillator 11, a mixer 12, a gate 14, a frequency divider 15, and a counter 16 are provided.

In the present invention, the center I is set by setting the frequency of the reference frequency oscillator 1 to 22.5 KHz + Δf.
The F frequency of 70 MHz or 140 MHz is realized.
Next, the operation of this embodiment will be described. Reference frequency oscillator 1
In order to shift the frequency of
The data recognized by the controller 7 which recognizes the shift amount of the above is sent to and held by the data holder 8. Further, the output data of the data holder 8 is converted into an analog voltage by the digital-analog converter 9 and then passed through the low-pass filter 10 for removing the harmonic component to the frequency control terminal of the reference frequency oscillator 1. Is entered. On the other hand, the reference frequency oscillator 1
Under the control of the controller 7, a loop circuit is formed which monitors the process of properly shifting by Δf and transmits the deviation from Δf in that process to the controller 7 to make it converge. That is, from the output of the reference frequency oscillator 1, the mixer 12, the low-pass filter 13, the gate 14, the counter 1
6, a loop to the input of the latch circuit 17, the control circuit 7, the latch circuit 8, the digital-analog conversion circuit 9, the low-pass filter 10 and the reference frequency oscillator 1 is formed. Further, the output of the reference frequency oscillator 11 of 22.5 KHz is input to the mixer 12 and mixed with 22.5 KHz + Δf to output Δf, and the reference signal of 22.5 KHz is further divided by ½ to make the gate 14 A frequency divider 15 that opens in a cycle is provided. As the operation of this loop circuit,
The output of the reference frequency oscillator 1 and the output from the reference frequency oscillator 11 are input to the mixer 12, and when the output of the mixer 12 passes through the low pass filter 13, a difference frequency in the process of being converged to Δf is generated. .. This difference frequency is sent to the next counter 16 by the gate 14 at a period of a certain time interval of 22.5 KHz.1 / 2. The counter 16 counts the difference frequency only during the above-described period, and the count value is held by the data holder 17. The output signal of the frequency divider 15 is used as the hold control signal of the data holder 17. However, regarding the timing relationship between the gate 14 and the data holder 17, when the gate 14 is opened, the data holder 17 holds the previous data, and when the gate 14 is closed, the data holder 17 outputs the output data. The operation of outputting to control circuit 7 is performed. The controller 7 monitors the difference frequency data and checks whether or not the desired difference frequency is obtained. If the desired difference frequency is not obtained, it is considered that the output frequency of the reference frequency oscillator 1 is not set to a normal value, and the data to the latch circuit 8 is changed until it can be regarded as a normal value. When there is an error due to the non-linearity of the control data from the controller 7, an output error of the digital-analog conversion circuit 9 and an error with respect to the temperature change of the reference frequency oscillation circuit 1, there is a slight deviation in the desired Δf. Occurs.

[0010]

As described above, according to the present invention, the output frequency of the reference frequency oscillator is deviated by Δf according to the data from the controller, and the Δf is constantly monitored. There is an effect that the conversion oscillator and the second PLL circuit for removing spurious are not required, and the hardware configuration is very simple and the cost is reduced while maintaining high frequency accuracy.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional frequency synthesizer.

[Explanation of symbols]

 1 Reference frequency oscillator 2,24 Phase error detector 3,25 Loop filter 4,26 Voltage control oscillator 5,27 Distributor 6,15,23,28 Frequency divider 7 Controller 8,17 Data holder 9 Digital analog Converter 10,13 Low-pass filter 11 Reference frequency oscillator 12,22 Mixer 14 Gate 16 Counter 21 Oscillator

Claims (3)

[Claims] 1. A desired output frequency fI is set to a shift frequency f0.
In a frequency synthesizer that changes in steps of
F0 ± Δ, which is a reference frequency when phase-comparing with a signal obtained by dividing the output frequency fI by 1 / N (N is an integer of 2 or more)
f (Δf = | Nf0−fI | / N), reference frequency generating means, control means for controlling the reference frequency generating means so as to obtain the frequency signal of Δf, and output frequency of the reference frequency generating means. And a monitoring means for transmitting the deviation frequency to the control means and performing a control operation when the deviation frequency is deviated from the frequency signal of Δf. 2. A reference oscillator in which the monitoring means generates a reference frequency of the shift frequency f0, an output signal of the reference oscillator and an output signal of the reference frequency generation means are mixed, and a difference signal between them is output. 2. The frequency synthesizer according to claim 1, further comprising: a mixer for controlling the frequency difference, and a counter for periodically counting the frequency of the difference signal of the mixer output through a gate circuit. 3. The frequency synthesizer according to claim 2, wherein the gate circuit is opened / closed by a control signal obtained by dividing the frequency of the reference oscillator by a predetermined ratio.