JPH0342921A - Selective radio call receiver - Google Patents

Abstract

PURPOSE:To prevent characteristics from deteriorating by providing a local oscillation circuit part, a control part for reception, at least >=2 means for clock generation which differ in local oscillation frequency, and a clock switching part, and selecting a clock at every reception frequency. CONSTITUTION:When a frequency specification signal is sent from the control part 23, the frequency division number of an 1/N frequency division part 30 is specified so that a line frequency specified from the control part 23 can be received. Simultaneously with this operation, the control part 23 calculates whether or not a higher harmonic of the frequency of the clock 27 or higher harmonic of the frequency after frequency division decreases almost to a line. Here, the frequency of the clock 27 is determined optionally according to use. Then plural channels are received, so a channel where the disturbing signal of the higher harmonic and the line frequency are close to each other or overlap with each other is generated without fail. Here, a timing clock 20 is determined. For the purpose, the clock is selected according to the reception frequency to eliminate the influence of the clock.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a radio selective calling receiver that is equipped with a local oscillation circuit using XTL switching or a synthesizer method and is capable of single-channel or multi-channel reception.

[Prior Art] Conventionally, this type of radio selective calling receiver (hereinafter referred to as receiver) has one or more control or synchronization clock oscillators separate from the local oscillator of the radio section. This control clock is used for operating a control section represented by a decoder or CPU.

These clock frequencies are chosen independently of the line frequency or local oscillation frequency or intermediate frequency for synchronization or control purposes.

FIG. 2 shows a block diagram of a receiver according to the prior art.

In the figure, the radio section l has an antenna 4. High frequency amplification section 5.
Filter 6.8, 11. Mixer 7.9. IF amplifier section 12. Limiter 13. The logic section 2 includes a detection section 14, and the logic section 2 includes an analog/digital conversion section 15. IDRO
M section 16, decoder 17. Speaker drive section 18. Speaker 19. The synthesizer section 3 includes a control section 239 and a display section 22, and the synthesizer section 3 has a frequency dividing section 30. Low pass filter 29.
VC028, phase comparator 31. A frequency dividing section 32 is provided. In addition, 20 is a timing clock for a decoder, 2
1 is a CPU clock, and 33 is a synthesizer clock.

The oscillation frequency of these clocks ranges from several KHz to several 10 MHz.
The standard product for watches is 32°7, especially for decoders.
68KHz is common. Furthermore, for the CPU, self-excited oscillation using a CR is used for low frequencies, and an oscillation circuit using a vibrator is used for high frequencies.

Furthermore, this type of receiver is made compact, and the clock section and antenna or high frequency circuit are located very close to each other.

[Problems to be Solved by the Invention] Since the clock of the conventional receiver described above is selected regardless of the line frequency in the radio section 1, harmonic components of the clock frequency and the divided clock are used. There is a problem in that harmonic components after the clock frequency division from the circuit that is connected to the antenna mix into the antenna 4 or the radio section 1, causing a decrease in sensitivity, instability in sensitivity, or suppression of sensitivity.

In addition, in receivers that receive multiple radio frequencies, there is a problem that sensitivity differences occur depending on the receiving frequency, and in order to prevent clock harmonic components from affecting the line, it is necessary to separate the control unit and signal line. It is necessary to completely shield it, and moreover, it requires physical space, which is a very big problem in promoting miniaturization. Furthermore, when changing the line frequency at the customer's site, it is necessary to change not only the local oscillation circuit but also the clock depending on the case, which has the disadvantage of poor work efficiency.

SUMMARY OF THE INVENTION An object of the present invention is to provide a radio selective calling receiver that solves the above problems.

[Means to solve the problem]

In order to achieve the above object, the radio selective calling receiver according to the present invention includes a local oscillation circuit section using a vibrator switching or synthesizer method, a reception control section, and at least two or more components that operate the reception control section. The clock generation means has clock generation means having different oscillation frequencies, and a clock switching section.

Further, in the radio selective calling receiver, the two clocks having different oscillation frequencies are such that the harmonics of the divided clock frequencies are separated from each other by a predetermined frequency width or more at the reception line frequency, and the radio In the selective calling receiver, one of the harmonics of the divided clock frequency is always separated from the receiving line frequency by more than a predetermined frequency width and is not close to within the receiving bandwidth.

〔Example〕

The present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the synthesizer system according to the present invention.

In the figure, the radio section l has an antenna 4. High frequency amplification section 5.
Filter 6.8, 11. Mixer 7.9. IF amplification section +2. Limiter 13. Detection section 14. It has a second local oscillator 10 and performs code demodulation from the transmitted radio signal. The synthesizer section 3 serves as a first local oscillator of the radio section l, and the frequency dividing section 30, 32 . It has a VCO 28° low-pass filter 299 and a phase comparator 31.

The logic section 2 includes an analog/digital conversion section 15. ID
ROM section 16. Decoder 17. Speaker drive section 18
．． Speaker 19. Display section 22. Control unit 23. Buffer unit 24° clock switching unit 25. Channel specification ROM 2
6. The control section 23 converts the analog signal detected by the radio section l into a digital signal using the A/D conversion section 15, and sends the digital signal to the decoder 17. The decoder 17 compares this code with its own call code written in the IDROM section 16 to see if it is its own call code. here,
If they match, a sound is generated to notify the control section 23 that the call has been made, and if there is a message, the control section 23 displays the message on the display section 22. 20 is a timing clock that synchronizes with the detected code;
For 72 bit/s transmission, 32,768 KHz is generally selected.

The synthesizer section 3 creates a local oscillation signal for receiving an arbitrary frequency, and when a frequency designation signal is sent from the control section 23, the synthesizer section 3 sets the L/N so that the line frequency specified by the control section 23 can be received. The frequency division number of the frequency dividing unit 30 is specified. At the same time as this operation, the control section 23 starts the clock 27
Calculate whether harmonics of the frequency or harmonics of the frequency after division fall near the line.

Since all the signals in the control section 23 are operated by square wave pulses, the frequency components of the square wave can be calculated using a Fourier series, and the following equation is obtained. Also, since the actual square wave is further distorted, its components are more complex. In other words, this shows that many harmonic components are generated up to high orders.

However, in a real receiver, l/2"0 from the CLK original oscillation.
All you have to do is calculate the harmonic components up to. This is because the attenuation is large above that. Also, implementation method, processing speed, C
Since it also affects the LK frequency, all you have to do is consider the necessary harmonics. At this time, considering selectivity and sensitivity suppression, the frequency difference between the line and harmonics is several tens of thousands at the line frequency.
Worst condition (temperature) within KH2.

A frequency width that does not fall within even voltage fluctuations, etc. is required.

Here, the frequency of the clock 27 is arbitrarily determined according to the specifications. Then, since multi-channel reception is performed, there is always a channel whose line frequency is close to or overlaps with a harmonic interference signal. Here, the timing clock 20 is determined. In this example, line frequency and weight sensitivity are degraded. The frequency difference obtained by making the harmonic of the lowest frequency of CLK (maximum divided frequency) about 1/2 is the frequency obtained by the line.

A specific example is shown below.

Conditions are line frequency 150MHz, channel reception interval 2
5 KHz, the clock 27 is 2 Ml-1z, and the harmonics after frequency division affect the line up to 1/2' = 178 (higher-order 178 of 2 MHz affects the line).

Then, the harmonics of 118 of 2 MHz, or 250 KHz, affect the line, so 150 MHz near the line
÷0.25=600.600 times more harmonics can be received.

In other words, if the frequency is centered around 150 MHz, there is a channel whose characteristics deteriorate every ±250 KHz. Next, select clocks 21 that are separated by half the 250 KHz interval (125 KHz). In other words, 150MHz+1
25KHz=150.125MHz, 150,125
MHz÷600=250.208333KHz, 25
0,208333X8=2.001667MHz, CLK1=2.000000MHz, CLK2=2
．． 001667M1 (by using two z and selecting the clock according to the receiving frequency, the influence from the clock can be eliminated.

This sequence is performed by the control unit 23, but the third
This is shown in the flowchart in Figure.

Next, the manner in which the harmonics of the clock mentioned above affect the line frequency and the manner in which the influence disappears by switching between CLK 1 and CLK 2 will be explained using a spectrum on the frequency axis.

FIG. 4 shows a waveform 34 when the clock is viewed on the time axis.

In other words, it is a square wave. The frequency is 1/T.

FIG. 5 shows the square wave of FIG. 4 on the frequency axis, and is a frequency axis waveform 35 of the clock 27. In FIG.

As can be understood using the Fourier series, it can be seen that many harmonics appear at every frequency of 1/T and extend to higher orders.

Therefore, if these harmonics are near the line, the characteristics will deteriorate.

Figure 6 is a diagram of the frequency axis near the line frequency, and the received signal 36
This indicates that there is no interference. This signal is received.

FIG. 7 is a diagram in which harmonic components of the clock are generated near the same frequency as FIG. 6. 37 is an n-times harmonic of the clock 27, 38 is an n+1-times harmonic, 39 is an n+2-times harmonic, and 40 is an n+3-times harmonic.

FIG. 8 shows how the received signal in FIG. 6 and the harmonic components of the clock in FIG. 7 overlap.

41 is a waveform in which the received signal 36 and the clock 27 are overlapped by n+2 times. This shows that harmonics of the clock are superimposed on the received signal on the line, degrading the characteristics (f, +(n+2)).

Next, in FIG. 9, the harmonics of the clock CLK 1, which overlapped in FIG. 42 is n times higher harmonic of clock 21, 43 is n of clock 21
+1 times higher harmonic, 44 is n+2 times higher harmonic of clock 21, and 45 is n+3 times higher harmonic of clock 21.

By selecting the clock (CLK) for each receiving frequency in this way, the characteristics do not deteriorate.

Here, even in a crystal type receiver that is not a synthesizer type, the influence can be eliminated by freely selecting the clock by switching the clock or selecting the logic port to "H#" or "L".

Next, FIG. 1O shows an example of a clock switching section. Two transfer gates 47 and 48 are connected to two different oscillators 4
9.50 and one inverter 46, and its operation is shown in the timing chart of FIG. 51 is a control unit input terminal, and 52 is an output terminal of the control unit to the oscillation circuit. In this figure, one of the transfer gates 47 and 48 is turned on by a control signal from the control section, and one of the vibrators 49 and 50 can be selected.

〔Effect of the invention〕

As explained above, in the present invention, by selecting two different clocks corresponding to the receiving frequency, there is an effect of not deteriorating the characteristics of the receiver. Since there is no need to maintain a long distance between the wireless unit and the wireless unit, efficiency can be improved both in terms of cost and at the design stage, and miniaturization can be easily achieved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a receiver according to an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional receiver, FIG. 3 is an operation flow showing the operation of the control unit in the present invention, and FIG. Figure 4 is a clock waveform diagram on the time axis, Figure 5 is a clock waveform diagram on the frequency axis, and Figure 6 is a diagram showing a weak received signal on the frequency.
Figure 7 is a diagram of the high-order harmonics of the clock in terms of frequency.
FIG. 8 is a diagram in which the received signal and clock harmonics overlap, FIG. 9 is a diagram in which the received signal and clock harmonics do not overlap, and FIG. 1O is a block diagram showing an example of the clock switching section circuit.
FIG. 11 is a diagram showing the timing of the clock switching section. l...Radio section 2...Logic section 3.
...Synthesizer part 4...Antenna 5...Harmonic amplification part 6,8.11...Filter 7.9...
・Mixer 10...Second local oscillator 12・
...IF amplification section 13...Limiter 14...
・Detection section 15...Analog/digital conversion section 1
6... IDROM section 17... Decoder 18... Speaker drive section 19... Speaker 20
...Decoder timing clock 21...CPU
Clock 22...Display section 23...Control section
24...Buffer section 25...Clock switching section 26...Channel specification ROM27...Clock 28...vCO29...Low pass filter 30.32...Frequency division section 31...Phase comparison section 33... Synth clock 46... Inverter 47.48... Transfer gate 49
．． 50... Oscillator Figure 3: Glock on open glaze Figure 5: Liquid number on top) High-toned liquid〃-to person, Kotobukisen Fig. 9 51 JAllm Fig. 10 Fig. 11

Claims (3)

[Claims] (1) A local oscillation circuit section using a vibrator switching or synthesizer method, a reception control section, at least two or more clock generation means with different oscillation frequencies for operating the reception control section, and a clock switching section. A wireless selective call receiver comprising: (2) In the radio selective calling receiver, the two clocks having different oscillation frequencies are characterized in that the harmonics of the divided clock frequencies are separated from each other by a predetermined frequency width or more at the reception line frequency. ) Radio selective calling receiver described in paragraph 2. (3) In the radio selective calling receiver, the harmonics of the clock frequency after frequency division are always separated from the receiving line frequency by more than a predetermined frequency width and are not close to each other within the receiving bandwidth. The radio selective calling receiver according to claim (1).