JP2011014961A - Pll device and method of evading unneeded frequency - Google Patents

Abstract

PROBLEM TO BE SOLVED: To evade the influence of an unneeded frequency without affecting a radio performance in a PLL device.SOLUTION: The PLL device includes voltage controlled oscillators 3 and 4, a phase comparator 1 for comparing both phases of first signals based on reference signals and second signals based on the output signals of the voltage controlled oscillators and for outputting phase difference signals indicating a phase difference, and a loop filter 2 for applying a control voltage for synchronizing both phases to the voltage controlled oscillators on the basis of the phase difference signals, wherein the PLL device obtains a prescribed target frequency. The PLL device is provided with: a reference frequency change means 5 for changing the frequency of the reference signals in order to turn the unneeded frequency to the one out of a prescribed frequency range centering on the target frequency when the unneeded frequency is present within the frequency range; and a frequency dividing ratio change means 5 for changing a frequency dividing ratio when generating the first signals or the second signals so as to maintain the output of the target frequency regardless of the change of the frequency of the reference signals.

Description

  The present invention relates to a PLL device that obtains a signal of a predetermined frequency by phase synchronization, and an unnecessary frequency avoidance method in the PLL device.

  In general, in a PLL (phase synchronization circuit) synthesizer circuit, a temperature compensated crystal oscillator (hereinafter referred to as “TCXO”) is used to obtain a reference signal that is a reference for phase synchronization. However, the output of the TCXO includes an unnecessary frequency component (beat frequency) generated by oscillating at an unintended frequency due to harmonics or the like. Therefore, when the transmission / reception frequency is determined based on the frequency output from the PLL device and transmission / reception is performed, the spurious frequency corresponding to the unnecessary frequency component appears in the vicinity of the transmission frequency or the reception frequency, which adversely affects the quality of the transmission / reception signal. May cause effects. Therefore, when the spurious frequency is close to the transmission / reception frequency, conventionally, the spurious frequency is kept away from the transmission / reception frequency by shifting the oscillation frequency of the TCXO (clock shift), thereby preventing the adverse effect of the spurious frequency.

  As a technique for shifting the reference frequency and avoiding the influence of the spurious frequency in this way, for example, one described in Patent Document 1 is known. In this technique, a varicap diode is used as a correction capacitor in the reference signal generation circuit, and the reference frequency is shifted by changing the VT voltage applied to the varicap diode.

  On the other hand, as another technique for avoiding the effect of spurious frequencies, a replica signal having the same amplitude and opposite phase as the unnecessary AC signal component included in the reference signal is generated, and the unnecessary AC signal component is canceled by the replica signal. Also known are those which are removed (see, for example, Patent Document 2).

  In addition, a technique is also known in which an oscillating element that generates an unnecessary frequency component, a PLL-IC, or the like is surrounded by a shield cover to be coupled with an external circuit.

JP 2006-040554 A JP 2007-228444 A

  However, according to the technique of shifting the reference frequency by changing the VT voltage of the varicap in the above-described reference signal generation circuit, the transmission frequency and the heterodyne frequency of the reception system are also greatly shifted due to the shift of the reference frequency. When applied to a wireless device that requires a high degree of performance, the wireless performance is adversely affected that cannot be ignored.

  Further, according to the technique for canceling and removing the unnecessary AC signal component by the above-described antiphase replica signal, the circuit configuration for realizing the technique becomes complicated.

  In addition, according to the above-described technology for shielding with a shield cover, there are cases where it is not possible to perform sufficient decoupling with an external circuit due to structural restrictions for providing the shield cover, and application to a radio device At this time, it is not a good idea to reduce the size and weight of the radio and to reduce the cost.

  An object of the present invention is to provide a simple technique capable of avoiding the influence of an unnecessary frequency in a radio apparatus to which a PLL device is applied without affecting the radio performance in view of the problems of the related art. It is in.

  To achieve this object, a PLL device according to a first aspect of the present invention compares both phases of a voltage controlled oscillator, a first signal based on a reference signal, and a second signal based on an output signal of the voltage controlled oscillator. A phase comparator that outputs a phase difference signal indicating a phase difference; and a loop filter that applies a control voltage for synchronizing both phases to the voltage controlled oscillator based on the phase difference signal from the phase comparator. A PLL device that outputs a frequency, and when an unnecessary frequency exists within a predetermined frequency range centered on the target frequency, the frequency of the reference signal is changed to exclude the unnecessary frequency from the frequency range. And a frequency dividing ratio when generating the first signal or the second signal so that the output of the target frequency is maintained despite the change of the frequency of the reference signal. Characterized by comprising a frequency dividing ratio changing means for changing.

  According to a second aspect of the present invention, there is provided a PLL device according to the first aspect, wherein a detection unit that detects a deviation from a nominal value of a frequency being received in a reception device whose reception frequency is determined by the target frequency, and the detection unit Frequency division ratio correcting means for correcting the frequency division ratio when generating the first signal or the second signal so that the deviation from the detected nominal value is eliminated.

  A PLL device according to a third invention is the PLL device according to the second invention, wherein the PLL device is a delta Σ type PLL device, and the frequency division ratio correction means determines a frequency division ratio when generating the first signal. The frequency divider ratio is corrected by changing the frequency divider ratio of the reference divider or the reference counter.

  According to a fourth aspect of the present invention, there is provided a method for avoiding an unnecessary frequency, comprising: comparing a phase of a voltage controlled oscillator with a first signal based on a reference signal and a second signal based on an output signal of the voltage controlled oscillator; A phase comparator that outputs a signal, and a loop filter that applies a control voltage that synchronizes both phases to the voltage controlled oscillator based on the phase difference signal from the phase comparator, and outputs a target frequency. An unnecessary frequency avoiding method in the apparatus, wherein when the unnecessary frequency exists within a predetermined frequency range centered on the target frequency, the frequency of the reference signal is changed to exclude the unnecessary frequency from the frequency range. And generating the first signal or the second signal so that the output of the target frequency is maintained despite the change of the frequency of the reference signal. Characterized by comprising a frequency dividing ratio and the frequency dividing ratio changing step of changing the.

  ADVANTAGE OF THE INVENTION According to this invention, the influence of the unnecessary frequency in the radio apparatus with which a PLL apparatus is applied can be easily avoided, without affecting radio performance.

It is a block diagram which shows the structure of the PLL apparatus which concerns on one Embodiment of this invention. It is a table | surface which shows an example of the unnecessary frequency in the radio | wireless machine of 400 [MHz]-470 [MHz] band. It is a block diagram which shows the structure which concerns on the automatic frequency control by CPU of the apparatus of FIG.

  FIG. 1 is a block diagram showing a configuration of a PLL device according to an embodiment of the present invention. This PLL device is used in a radio device to determine a transmission frequency and a heterodyne frequency in a reception system. As shown in the figure, the PLL device includes a PLL-IC 1 functioning as a phase comparator, a loop filter 2 connected to the PLL-IC 1, and a reception and transmission VCO connected to the output side of the loop filter 2. (Voltage controlled oscillator) 3 and 4 are provided. The PLL-IC 1 compares the phase of the signal based on the predetermined reference signal with the phase of the signal based on the output signal of the VCO 3 or 4 and outputs a signal corresponding to the phase difference. This signal is converted into a direct current by the loop filter 2 and supplied to the VCO 3 or 4 as a voltage control signal. As a result, a signal having a frequency whose phase is synchronized with the reference signal is output from the VCO 3 or 4.

  In FIG. 1, 5 is a CPU for controlling the PLL-IC1, 6 is a TCXO (temperature compensated crystal oscillator) for supplying a reference signal to the PLL-IC1, 7 is interposed between the TCXO6 and the PLL-IC1, and the reference signal LPF (low-pass filter) for removing unnecessary high frequency components from 8, VCO buffer 8 connected to the output side of VCO 3 and 4, 9 buffer connected to the output side of buffer 8, 10 output side of VCO buffer 8 An amplifier 11 is connected to the amplifier 10 and an LPF (low-pass filter) interposed between the amplifier 10 and the PLL-IC 1.

  Reference numeral 12 in FIG. 1 denotes a DA converter for the CPU 5 to give signals to the TCXO 6 and the VCO 4. The Vout1 terminal and the Vout2 terminal of the DA converter 12 are connected to the CV terminal of the TCXO6 and the modulation terminal of the VCO4, respectively. The oscillation frequency of the TCXO 6 can be changed by the CV voltage applied from the DA converter 12 to the CV terminal of the TCXO 6. Further, the oscillation frequency of the VCO 4 can be modulated by a modulation signal applied from the DA converter 12 to the modulation terminal of the VCO 4.

  The PLL-IC 1 has an OSC terminal to which a reference signal is input from the TCXO 6 through the LPF 7, a CS / DATA / CLOCK terminal to which the PLL data is input from the CPU 5, and an output of the VCO buffer 8 is input through the amplifier 10 and the LPF 11. Fin terminal, C / P (charge pump) terminal that outputs a positive or negative pulse signal corresponding to the above-described phase difference, and LD that outputs a lock detection signal indicating whether the phase is locked or unlocked to the CPU 5 Provide terminals.

  In this configuration, the PLL-IC 1 generates the reference comparison frequency frc by dividing the reference signal from the OSC terminal by the division ratio R by the reference driver based on the PLL data for transmission or reception given from the CPU 5. Further, the feedback signal input from the Fin terminal is divided by the frequency division ratio N to generate the feedback comparison frequency fpc. Then, the phase of the reference comparison frequency frc and the phase of the feedback comparison frequency fpc are compared, and a positive or negative charge pulse corresponding to the phase difference is output from the C / P terminal. The loop filter 2 integrates this charge pulse to generate a tuning voltage, which is supplied to the VCO 3 during reception and supplied to the VCO 4 during transmission. Thus, the oscillation frequency of the VCO 3 or 4 is controlled so that the phase difference is constant (locked state). The frequency of the output signal of the VCO 3 or 4 in the locked state, that is, the target frequency fo is a frequency obtained by multiplying the reference frequency fref by N / R. The PLL-IC 1 outputs a lock detection signal indicating whether or not it is in a locked state to the CPU 5 via the lock detection output terminal LD.

  At the time of transmission of a radio device to which the PLL device is applied, as described above, when the VCO 4 oscillates at a transmission frequency according to the PLL data for transmission supplied from the CPU 5 to the PLL-IC 1 and becomes locked, the CPU 5 The modulation signal is supplied from Vout2 of the DAC 12 to the modulation signal terminal. A signal having a modulated transmission frequency is output from the buffer 9 and transmitted by the wireless device. At the time of reception, the VCO 3 oscillates at a frequency according to the reception PLL data supplied from the CPU 5 to the PLL-IC 1, and when in a locked state, the heterodyne frequency is output from the buffer 9. Based on this output, the wireless device converts the received wave from the antenna into an intermediate frequency and performs reception.

  However, the beat frequency, which is an unnecessary frequency component caused by the harmonics of the reference signal from the TCXO 6, appears as a spurious frequency in the vicinity of several kilohertz away from the transmission frequency or the reception frequency, and the SNR or ACR (adjacent channel interference) There is a risk that the resistance to waves), ACPR (adjacent channel power ratio), and the like may be deteriorated. Therefore, in the present embodiment, when the target VCO 3 or VCO 4 oscillation frequency (hereinafter referred to as “target frequency”) is set in the vicinity of the unnecessary frequency, the target frequency is changed as follows. In addition, the SN, ACR, and ACPR are prevented from deteriorating by keeping only the unnecessary frequency away from the target frequency.

That is, the beat frequency fb, which is an unnecessary frequency component, can be obtained by the following equation using the reference frequency fref output by the TCXO 6 and the frequency division ratio R of the reference driver.
[Equation 1]
fb = fref ÷ R × n
Where n is an integer

  Therefore, for example, when the reference frequency fref is 19.2 [MHz], the frequency division ratio R is 18, and the integer n is 396, the beat frequency fb is 422.4 [MHz] (= 19.2 [MHz] ÷ 18. × 396). In this case, if the target frequency is set to 422.41 [MHz], the difference between the target frequency and the beat frequency fb is 10 [kHz]. As shown in the table of FIG. 2, there are 66 unnecessary frequencies (beat frequencies) obtained by such calculation, as shown in the table of FIG.

  When any beat frequency exists within a predetermined frequency range centered on the target frequency, the CPU 5 changes the CV voltage of the TCXO 6 to exclude the beat frequency from the predetermined frequency range. The oscillation frequency of the TCXO 6 is shifted to keep the beat frequency away from the target frequency. For example, in the example in which the target frequency is 422.41 [MHz], the CV voltage is changed so that the reference frequency fref is changed from 19.2 [MHz] to 19.0 [MHz]. At this time, the beat frequency fb in the case of n = 396 is 418.0 [MHz] (= 19.0 [MHz] ÷ 18 × 396). As a result, the beat frequency fb (422.4 [MHz]) in the case of n = 396 in the vicinity of the target frequency (422.41 [MHz]) is shifted downward by about 4 [MHz].

  At this time, the beat frequency closest to the target frequency (422.41 [MHz]) is 422.222 [MHz] (= 19.0 [MHz] ÷ 18 × 400). Therefore, by changing the oscillation frequency of the TCXO 6 from 19.2 [MHz] to 19.0 [MHz], the beat frequency existing at 10 [kHz] away from the target frequency is about 190 [kHz] away. Therefore, it does not cause deterioration of SN, ACR, ACPR, and the like.

  The CPU 5 stores in advance the TCXO6 CV voltage at which the TCXO6 oscillation frequency (reference frequency) is 19.2 [MHz] and the TCXO6 CV voltage at which the oscillation frequency is 19.0 [MHz]. When the frequency is set to 422.41 [MHz], the CV voltage of the TCXO 6 is changed through the DAC 12 so that the oscillation frequency of the TCXO 6 becomes 19.0 [MHz]. However, the CPU 5 previously stores PLL data for maintaining the target frequency at 422.41 [MHz] when the oscillation frequency of the TCXO 6 is changed to 19.0 [MHz], and the oscillation frequency is 19.0. When changing to [MHz], the PLL data is sent to the PLL-IC 1 so that the target frequency (422.41 [MHz]) does not change, and the above-described frequency division ratio R or N is adjusted.

  At this time, if the oscillation frequency of the TCXO 6 deviates from 19.0 [MHz] after the change, the reception frequency also deviates by that amount, so it is configured by an ASIC (specific application IC) and a DSP (digital signal processor). Therefore, the second intermediate frequency input to the detection stage of the radio device is shifted from the nominal value in the case of the target reception frequency. Therefore, as shown in FIG. 3, a signal obtained by detecting the second intermediate frequency after passing through the BB (baseband) filter is converted into a DC proportional to the frequency deviation E from the nominal value by the AFC-LPF (automatic frequency control LPF) 31. Based on this, the AFC frequency shift determination unit 32 of the CPU 5 determines the amount of the frequency shift E. Based on the determination result, the CPU 5 corrects the oscillation frequency of the VCO 3 by supplying the PLL-IC 1 with “Modulation Data Control” (modulation data control) for correcting the frequency deviation E. Displacement E is eliminated.

At that time, by using a delta sigma type PLL-IC1, the oscillation frequency fo of the VCO 3 can be changed by a frequency step fs in units of several hertz. For example, the frequency step fs is expressed by the following equation using the oscillation frequency fref of the TCXO 6, the reference divider frequency division ratio Rd in the PLL-IC 1 and the frequency division ratio Rc of the reference counter.
[Equation 2]
fs = fref ÷ Rd ÷ Rc
In this case, for example, if the oscillation frequency fref is 19.2 [MHz], the reference divider frequency division ratio Rd is 2 ^ 18, and the frequency division ratio Rc of the reference counter is 18, the frequency step fs is about 4 [Hz] ( ≈4.096 [Hz] = 19.2 [MHz] ÷ 2 ^ 18 ÷ 18). Therefore, by controlling the “Modulation Data Control” data, the oscillation frequency of the VCO 3 can be corrected in about 4 [Hz] steps by changing the frequency division ratio of the reference divider or the reference counter in addition to this.

  According to this embodiment, the influence of unnecessary frequencies can be avoided without affecting the wireless performance. That is, according to the conventional technique for avoiding unnecessary frequencies only by changing the reference frequency, the transmission frequency and the heterodyne of the reception system are caused by the shift of the oscillation frequency (lock frequency) of the VCO due to the change of the reference frequency. According to the present embodiment, the reference frequency is changed to avoid unnecessary frequencies, while the frequency may be greatly displaced, which may adversely affect the performance of a radio device that requires good frequency stability. In this case, since the PLL-IC is controlled so that the oscillation frequency of the VCO does not change even if the reference frequency is changed, it is unnecessary in the vicinity of the transmission frequency and the heterodyne frequency without adversely affecting the performance of the radio. By eliminating the frequency, it is possible to prevent deterioration of the radio performance of SN, ACR, ACPR and the like. Further, since the control of the PLL-IC is based on an electrical signal, the present invention can be applied to the radio without being restricted by hardware.

  Further, since the deviation from the nominal value is detected for the frequency being received, and the division ratio R is corrected when the reference comparison frequency frc is generated so that the deviation is eliminated, the stability of the reception frequency Can be ensured, and deterioration of wireless performance can be prevented more reliably.

  Note that the present invention is not limited to the above-described embodiment, and can be implemented with appropriate modifications. For example, in the above description, the frequency division ratio R in generating the reference comparison frequency frc is corrected in order to eliminate the deviation from the nominal value of the frequency being received. In addition, the frequency division ratio N when generating the feedback comparison frequency fpc may be corrected.

  1: PLL-IC, 2: LPF (low pass filter), 3: reception VCO (voltage controlled oscillator), 4: transmission VCO, 5: CPU, 6: TCXO (temperature compensated crystal oscillator), 7: LPF ( Low-pass filter), 8: VCO buffer, 9: buffer, 10: amplifier, 11: LPF (low-pass filter), 12: DA converter, 31: AFC-LPF (automatic frequency control LPF), 32: frequency deviation determination unit.

Claims (4)

A voltage controlled oscillator;
A phase comparator that compares both phases of a first signal based on a reference signal and a second signal based on an output signal of the voltage controlled oscillator and outputs a phase difference signal indicating a phase difference;
A loop filter that applies a control voltage for synchronizing both phases to the voltage controlled oscillator based on the phase difference signal from the phase comparator;
A PLL device that outputs a target frequency,
Reference frequency changing means for changing the frequency of the reference signal in order to exclude the unnecessary frequency from the frequency range when the unnecessary frequency exists within a predetermined frequency range centered on the target frequency;
Frequency division ratio changing means for changing a frequency division ratio when generating the first signal or the second signal so that the output of the target frequency is maintained despite the change of the frequency of the reference signal. A PLL device characterized in that: Detecting means for detecting a deviation from a nominal value of a frequency being received in a receiving apparatus in which a reception frequency is determined by the target frequency;
Frequency division ratio correction means for correcting a frequency division ratio when generating the first signal or the second signal so that a deviation from the nominal value detected by the detection means is eliminated. The PLL device according to claim 1. Delta Σ type PLL device,
The frequency division ratio correcting means corrects the frequency division ratio by changing the frequency division ratio of a reference divider or a reference counter that determines the frequency division ratio when generating the first signal. The PLL device according to claim 2, wherein the PLL device is provided. A voltage controlled oscillator;
A phase comparator that compares both phases of a first signal based on a reference signal and a second signal based on an output signal of the voltage controlled oscillator and outputs a phase difference signal indicating a phase difference;
A loop filter that applies a control voltage for synchronizing both phases to the voltage controlled oscillator based on the phase difference signal from the phase comparator;
An unnecessary frequency avoidance method in a PLL device that outputs a target frequency,
A reference frequency changing step of changing the frequency of the reference signal in order to exclude the unnecessary frequency from the frequency range when the unnecessary frequency exists within a predetermined frequency range centered on the target frequency;
A frequency division ratio changing step of changing a frequency division ratio when generating the first signal or the second signal so that the output of the target frequency is maintained despite the change of the frequency of the reference signal. An unnecessary frequency avoidance method characterized by:

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