JPH05259761A - Differential amplifier circuit - Google Patents

Abstract

PURPOSE:To obtain the differential amplifier circuit of new configuration in which linearity of trans-conductance is improved. CONSTITUTION:The capability (gate width/gate length) of MOS transistors (TRs) (M1, M2), (M3, M4) driven by a constant current source I0 is selected to be M1:M2=M4:M3=K:1. The capability of MOS TRs (M5, M6) driven by a constant current source I0' is selected to be M5:M6=K':K'. Gates of the M1, M3, M5 and gates of the M2, M4, M6 are connected respectively in common to form a differential input pair. Drains of the M1, M3, M6 and drains of the M2, M4, M5 are respectively connected in common to form an output differential pair. The linearity of the trans-conductance is improved by the balanced differential pair of the TRs M5, M6, I0'.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier circuit,
In particular, it relates to a differential amplifier circuit composed of MOS transistors.

[0002]

2. Description of the Related Art When a differential amplifier circuit is composed of MOS transistors, the linearity of transconductance becomes a problem. As a differential amplifier circuit with improved linearity,
Conventionally, for example, those shown in FIGS. 4, 5, and 6 are known. These are referred to because they are described in detail in the following documents.

Figure 3: A. Nedungadi and TR Viswanathan
“Design of Linear CMOS Transco-nductance Element
s ”IEEE TRANSACTION ON CIRCUITS AND SYSTEMS, VOL, C
AS-31, NO.10, pp.891-894, OCTOBER 1984.

FIG. 5: Zhenhua Wang and Walter Guggenbu
hl “A Voltage-Controllable Line-ar MOS Transconduc
tor Using Bias Offset Technique ”IEEE JOURNAL OF
SOL-ID-STATE CIRCUITS, VOL.25, NO.1, PP.315-317, FEBRU
ARY 1990.

FIG. 6: Francois Krummenacher and Norber
t Joehl “A 4-MHz CMOS Continuo-us-Time Filter wit
h On-Chip Automatic Tuning ”IEEE JOURNAL OF SOLID-
STA-TE CIRCUITS, V0L.23, NO.3 pp.750-758, JUNE 1988.

[0006]

However, in the conventional differential amplifier circuit in which the linearity of these transconductances is improved, even if the output current value is the maximum, it is 1/3 or 1/1 of the drive current.
Since the current efficiency is less than 2 (Figs. 4 and 6), it is difficult to generate a stable offset voltage (Fig. 5).
Further, there is a problem that the manufacturing deviation and the temperature characteristic are weak as a whole.

It is an object of the present invention to provide a differential amplifier circuit having a new structure which has a high current efficiency, can reduce the influence of manufacturing deviation and temperature characteristics, and can improve the linearity of transconductance.

[0008]

In order to achieve the above object, the differential amplifier circuit of the present invention has the following configuration. That is,
The differential amplifier circuit of the present invention includes a balanced differential pair including two FETs having the same capability (ratio of gate width and gate length) and a first constant current source for driving these FETs; A first unbalanced differential pair comprising two FETs and a second constant current source driving them; two FETs having a capacity of 1: K and the second constant current source driving them A second unbalanced differential pair having a constant current source of the same value;
Of the FET whose unbalanced differential pair has a capacity of K and the FET whose second unbalanced differential pair has a capacity of 1 and the other FET of the balanced differential pair and the first unbalanced differential Pair ability is 1
F and the capacity of the second unbalanced differential pair is F
Gates with ET are commonly connected to each other;
The differential output pair includes drains of the other FET of the balanced differential pair, an FET in which the capability of the first unbalanced differential pair is K, and a FET in which the capability of the second unbalanced differential pair is 1. And a FET in which the capability of one of the balanced unbalanced differential pair and the first unbalanced differential pair is 1 and a capability of the second unbalanced differential pair is K
And the drains of and are commonly connected to each other; respectively.

[0009]

Next, the operation of the differential amplifier circuit of the present invention constructed as above will be described. In the present invention, two unbalanced differential pairs are so-called plucked and the balanced differential pair is reversely connected to this, so that the linearity of the transconductance of the differential amplifier circuit can be improved even if the current efficiency is set high. .. At this time, since each FET operates in the saturation region, the temperature characteristics are the same, and therefore the temperature can be easily compensated by the constant current source. Regarding the effect of manufacturing deviation, since it operates differentially, the threshold voltage that is most significantly affected is canceled out and it does not contribute to circuit operation, and the transconductance parameter moves in a similar form, so the manufacturing deviation as a whole is Can be unaffected.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a differential amplifier circuit according to an embodiment of the present invention. Regarding the FET (MOS transistor), the same reference numerals as those of the conventional one (FIGS. 4, 5, and 6) are used.
This does not mean that they are the same. Further, the same symbols may be used for convenience of explanation, but this does not mean that the contents are the same.

This differential amplifier circuit has a capability (gate width W /
Two transistors (M1, M2) whose gate length L) is M1: M2 = K: 1 and a constant current source I for driving them
Comprising a ₀ (first) and unbalanced differential pair, capacity, M3:
Two transistors with M4 = 1: K (M3, M4)
And a (second) unbalanced differential pair comprising a constant current source I ₀ for driving the same, two transistors (M5, M6) having a capability of M5: M6 = K ′: K ′, and driving the same. And a balanced differential pair including a constant current source I ₀ ′.

Between these three differential pairs, one of the transistors M5 of the balanced differential pair and the transistor M1 of which the capability of the first unbalanced differential pair is K and the second unbalanced differential pair are: The gates of the transistor M3 having the capability of 1 and the other transistors M6 of the balanced differential pair and the transistor M2 having the capability of the first unbalanced differential pair and the capability of the second unbalanced differential pair have the capability of 1. Gates of the transistor M4, which is K, are commonly connected to each other to form a differential input pair.

Further, the other transistor M of the balanced differential pair
6 and the transistor M1 in which the capability of the first unbalanced differential pair is K and the transistor M3 in which the capability of the second unbalanced differential pair is 1, and the transistor M5 of the balanced differential pair. The drains of the transistor M2 having the capability of the first unbalanced differential pair of 1 and the transistor M4 having the capability of the second unbalanced differential pair of K are commonly connected to each other to form a differential output pair. ing.

That is, in the two unbalanced differential pairs, the drains of the transistors having different abilities such as so-called plow marks are commonly connected, while in the balanced differential pair, the drains of the transistors on the opposite side in connection are connected. (Reverse connection)

In the above configuration, assuming that the device operates in the saturation region, the drain current I _{d1 of} M1 is given by the following equations (1) and (M2).
The drain current I _d2 of M3 is the drain current I _{d3 of} M2.
Is Equation 3, the drain current I _{d4 of} M4 is Equation 4, the drain current I _{d5 of} M5 is Equation 5, and the drain current I _{d6 of} M6 is Equation 6.

[0016]

## EQU1 ## I _d1 = Kβ (V _GS1 −V _T ) ²

[0017]

## EQU00002 ## I _d2 = β (V _GS2- V _T ) ²

[0018]

## _EQU00003 ## I _d3 = β (V _GS3 −V _T ) ²

[0019]

## EQU4 ## I _d4 = Kβ (V _GS4- V _T ) ²

[0020]

## EQU5 ## I _d5 = K'β (V _GS5 -V _T ) ²

[0021]

[6] _{I d6 = K'β (V GS6 -V} T) 2

Here, V _T is a threshold voltage, V _T
GSi is the gate-source voltage. Further, β is a transconductance parameter of the transistor, and can be expressed by Equation 7 using mobility μ, gate oxide film capacitance C _OX per unit area, gate width W and gate length L.

[0023]

[Equation 7] β = μC _OX (W / L) (1/2)

Then, the constant current source I ₀ is the equation 8, the constant current source I ₀ ′ is the equation 9, and the difference between the gate-source voltages between the transistors of each differential pair is the equation 10.

[0025]

[Equation 8] I ₀ = I _d1 + I _d2 = I _d3 + I _d4

[0026]

[Equation 9] I ₀ ′ = I _d5 + I _d6

[0027]

[Number 10] _{V GS1 -V GS2 = V GS3 -V} GS4 = V GS5 -V GS6

Therefore, from the equations 1 to 10, the difference current ΔI ₁ of the drain current in the first unbalanced differential pair is given by the equation 11,
The drain current difference current ΔI _{2 in the second} unbalanced differential pair is Equation 12, and the drain current difference current in the balanced differential pair is ΔI.
₃ is obtained as Expression 13. In addition, in Formula 13,
K'is represented by Equation 14, and I ₀ 'is represented by Equation 15.

[0029]

[Equation 11]

[0030]

[Equation 12]

[0031]

[Equation 13]

[0032]

[Equation 14]

[0033]

[Equation 15]

[0034] Now, the difference current ΔI of the differential output current of the differential amplifier circuit, the drain of the transistor of the balanced differential pair is called reverse connection, although the equation 16, inputs the voltage V _IN What is differentiated by is the transconductance of the differential amplifier circuit (Formula 17).

[0035]

## EQU16 ## ΔI = ΔI ₁ + ΔI ₂ −ΔI ₃

[0036]

[Equation 17]

Here, since the balanced differential pair is intended to improve the linearity of the transconductance of the differential amplifier circuit, in order to study the degree of its contribution, equations 18 and 19 are given.
Consider parameters a and b that satisfy

[0038]

[Equation 18] K ″ · I ₀ ″ = a ² · K ′ · I ₀ ′

[0039]

## EQU19 ## K ″ / I ₀ ″ = b · K ′ / I ₀ ′

Then, for example, when K = 4 and K = 2, the equations 11 to 13 for the respective values of a and b are differentiated by the input voltage V _IN , and the transconductance value is obtained according to the equation 17. Figure 2 (K = 4) and Figure 3 (K = 2)
Becomes In FIG. 2 and FIG. 3, the transconductance when there is no balanced differential pair when a = 0 and b = 0, and the curves for the values of a and b where a ≠ 0 and b ≠ 0 are balanced. The contribution of the differential pair is shown.

There is a great improvement effect, and in the range where the input voltage range is expressed by equation 20,

[0042]

[Equation 20] √ (I ₀ / (Kβ)) ≧ │V _IN │

That is, although the horizontal axis is normalized, it is almost -1.
It can be understood that the transconductance has a substantially constant value in the range of / √K to + 1 / √K.

Next, from Equations 18 and 19, K ″ is obtained as Equation 21 and I ₀ ″ is obtained as Equation 22, so that the transistor capacity (W / L) of the balanced differential pair and the constant current source are independent. Can be set. Therefore, even when the current efficiency is set higher than the conventional one, the transconductance of the differential amplifier circuit can be improved. 2 and 3 show this.

[0045]

[Equation 21]

[0046]

[Equation 22]

In the differential amplifier circuit, since each transistor operates in the saturation region, the temperature characteristics are the same, and therefore the temperature can be easily compensated by the constant current source. Regarding the influence of the manufacturing deviation, the threshold voltage V _T is most affected and the transconductance parameter β is also affected, but since the threshold voltage V _T is offset because it operates differentially, it does not contribute to the circuit operation. Since the characteristics of the transconductance parameters also move in a similar manner, it is possible to prevent the effects of manufacturing deviations as a whole.

[0048]

As described above, according to the differential amplifier circuit of the present invention, two unbalanced differential pairs are so-called plucked and the balanced differential pair is reversely connected to this, so that the current efficiency is improved. Even if it is set high, the linearity of the transconductance of the differential amplifier circuit can be improved. At this time, since each FET operates in the saturation region, the temperature characteristics are the same, and therefore the temperature can be easily compensated by the constant current source. Regarding the influence of manufacturing deviation, since it operates differentially, the threshold voltage that is most significantly affected is canceled out and does not contribute to the circuit operation, and the transconductance parameter moves in a similar form, so the manufacturing deviation as a whole is There is an effect that it can be prevented from being affected.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a differential amplifier circuit according to an embodiment of the present invention.

FIG. 2 is a transconductance characteristic diagram (K = 4) of the differential amplifier circuit of the present invention.

FIG. 3 is a transconductance characteristic diagram (K = 2) of the differential amplifier circuit of the present invention.

FIG. 4 is a circuit diagram of a conventional differential amplifier circuit.

FIG. 5 is a circuit diagram of a conventional differential amplifier circuit.

FIG. 6 is a circuit diagram of a conventional differential amplifier circuit.

[Explanation of symbols]

M1 to M6 MOS transistor I ₀ constant current source I ₀ ′ constant current source V _IN input voltage K capability (gate width / gate length) K ′ capability (gate width / gate length)

Claims (1)

[Claims] 1. A balanced differential pair comprising two FETs having the same capability (ratio of gate width to gate length) and a first constant current source for driving them; two FEs having a capability of 1: K.
A first unbalanced differential pair comprising T and a second constant current source for driving them; two FETs having a capability of 1: K and the second constant current source for driving them, and a value A second unbalanced differential pair having an equal constant current source; and a differential input pair having one FET of the balanced differential pair and the first unbalanced differential pair having a capability of K And a second unbalanced differential pair with the FET having a capability of 1 and the other FET of the balanced differential pair with the first unbalanced differential pair with a capability of 1
The gates of T and the FET of which the capacity of the second unbalanced differential pair is K are commonly connected to each other; and the differential output pair is the first unbalanced with the other FET of the balanced differential pair. The FET of which the capacity of the differential pair is K and the capacity of the second unbalanced differential pair are 1
Between the drains of the first FET and the FET of the balanced differential pair, the FET of which the first unbalanced differential pair has an ability of 1 and the FET of which the second unbalanced differential pair has an ability of K. A drain and a drain are commonly connected to each other;