JPH05259344A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05259344A JPH05259344A JP5242492A JP5242492A JPH05259344A JP H05259344 A JPH05259344 A JP H05259344A JP 5242492 A JP5242492 A JP 5242492A JP 5242492 A JP5242492 A JP 5242492A JP H05259344 A JPH05259344 A JP H05259344A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- die pad
- hole
- semiconductor device
- moisture
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関する。さ
らに詳しくは半導体チップを樹脂で封入したパッケージ
のクラック発生を防止した半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device. More specifically, the present invention relates to a semiconductor device in which a package in which a semiconductor chip is sealed with a resin is prevented from cracking.
【０００２】[0002]
【従来の技術】半導体装置の製造工程において、実装用
のため、リードにハンダのリフローを行なったり、また
半導体装置を実装するため、ハンダ付けを行うが、その
ときにパッケージ全体が200 ℃以上に加熱される。その
ため、半導体チップを封入している樹脂が吸湿している
と、水分が気化膨張し、その圧力で樹脂にクラックが発
生することがある。2. Description of the Related Art In a semiconductor device manufacturing process, leads are soldered for soldering for mounting, and soldering is performed for mounting semiconductor devices. At that time, the entire package is heated to 200 ° C. or more. Be heated. Therefore, if the resin encapsulating the semiconductor chip absorbs moisture, the water vaporizes and expands, and the pressure may cause cracks in the resin.
【０００３】このクラックの入った様子を図３に示す。
図３において、１はダイパッド、２はリード、３は半導
体チップ、４は半導体チップ３をダイパッド１にダイボ
ンディングする接着剤であるプリフォーム材、５は半導
体チップ３の電極パッドとリード２とを電気的接続する
ための金線、６は半導体チップ３およびその周辺のワイ
ヤボンディング部分を封入した樹脂である。７はダイパ
ッド１の下面と樹脂６とのあいだの剥離により生じた空
隙で、８は樹脂６に入ったクラックである。FIG. 3 shows the appearance of the cracks.
In FIG. 3, 1 is a die pad, 2 is a lead, 3 is a semiconductor chip, 4 is a preform material that is an adhesive for die-bonding the semiconductor chip 3 to the die pad 1, and 5 is an electrode pad of the semiconductor chip 3 and the lead 2. Gold wire 6 for electrical connection is a resin that encapsulates the semiconductor chip 3 and the wire bonding portion around it. Reference numeral 7 is a void generated by peeling between the lower surface of the die pad 1 and the resin 6, and 8 is a crack in the resin 6.
【０００４】このクラック８の発生する理由は、つぎの
ように考えられている。すなわち、樹脂６はエポキシ樹
脂で、ダイパッド１はＦｅ- Ｎｉ系の42合金などで形成
されており、材料の相違による熱膨張率の差のため、ま
ずダイパッド１の周囲の側壁部分でダイパッド１と樹脂
６のあいだに浮きが生じ、樹脂６が吸湿した水分がその
浮きの生じた部分に入り、温度上昇により水蒸気となっ
て膨張し、さらに浮きを大きくして空隙７を形成する。
吸湿した水分は一層多くダイパッドの裏の空隙７に拡散
し、これがハンダのリフロー時などのときの200 ℃以上
への上昇により水蒸気となって膨張し、応力が発生し、
樹脂６の曲げ強度を超えたとき樹脂６にクラック８が入
ると考えられている（たとえば「エポキシ封止材の技術
動向」（エレクトロニクス 実装技術、1991年11月号、
65〜72頁）を参照）。The reason why the crack 8 is generated is considered as follows. That is, the resin 6 is an epoxy resin, and the die pad 1 is formed of a Fe-Ni-based 42 alloy or the like. Due to the difference in the coefficient of thermal expansion due to the difference in material, first, the die pad 1 is formed on the side wall portion around the die pad 1. Floating occurs between the resins 6, moisture absorbed by the resin 6 enters the floating portions, expands as water vapor due to temperature rise, and further increases the floating to form the void 7.
The absorbed moisture diffuses more into the void 7 on the back of the die pad, and when it rises to over 200 ° C when reflowing the solder, it becomes water vapor and expands, causing stress.
It is believed that cracks 8 will occur in the resin 6 when the bending strength of the resin 6 is exceeded (for example, "Technical trends of epoxy encapsulation materials" (Electronics mounting technology, November 1991,
See pages 65-72)).
【０００５】この樹脂６のクラック８を防止するため、
ダイパッドの裏面にディンプル（凹凸）を設けて表面積
を広げ力の分散を図ったり、ダイパッドの裏面まで貫通
する孔を樹脂にあけたベントを形成し、たまった水分の
蒸気を外部に放散させたり、ダイパッドの裏面にポリイ
ミドコートやガラスマットを入れて応力の緩和を図るな
どの対策が前述の文献にも示されている。In order to prevent the crack 8 of the resin 6,
By providing dimples (concavities and convexities) on the back surface of the die pad to spread the surface area and disperse the force, or by forming vents in the resin with holes penetrating to the back surface of the die pad, the vapor of accumulated moisture is diffused to the outside, Countermeasures such as putting a polyimide coat or a glass mat on the back surface of the die pad to relieve stress are also shown in the above-mentioned literature.
【０００６】[0006]
【発明が解決しようとする課題】しかし前述のような対
策が施されても、樹脂のクラックを完全には防止できな
い。その原因として文献「パッケージの半田クラックの
発生過程をＸ線観察」（日経マイクロデバイス、1991年
12月、145 〜150 頁）にも記載されているように、半導
体チップを接着するプリフォーム材の吸湿性によりプリ
フォーム材の水分が蒸気になって剥離を生じ、その蒸気
がダイパッドの裏側にも廻り込み、ダイパッドの裏側か
らクラックが入るのを助長するためと考えられる。However, even if the above measures are taken, the cracking of the resin cannot be completely prevented. As a cause of this, the document “X-ray observation of the process of solder crack generation in packages” (Nikkei Microdevice, 1991)
As described in December, pp. 145-150), the hygroscopicity of the preform material to which the semiconductor chip is bonded causes the moisture of the preform material to turn into steam, causing peeling. It is thought that this is because it also wraps around and promotes cracking from the back side of the die pad.
【０００７】本発明はこのような状況に鑑み、従来の樹
脂の吸湿性による水分に基づくダイパッド裏面の剥離を
防止すると共に、ダイパッドの表側のプリフォーム材の
吸湿性による水分に基づく剥離も防止して樹脂にクラッ
クが生じない半導体装置を提供することを目的とする。In view of such circumstances, the present invention prevents peeling of the back surface of the die pad due to moisture due to the hygroscopicity of the conventional resin, and also prevents peeling due to moisture due to the hygroscopicity of the front side preform material of the die pad. It is an object of the present invention to provide a semiconductor device in which resin does not crack.
【０００８】[0008]
【課題を解決するための手段】本発明による半導体装置
は、ダイパッドに半導体チップがプリフォーム材でダイ
ボンディングされ、該半導体チップおよびその周囲のワ
イヤボンディング部が樹脂で封入されてなる半導体装置
であって、前記ダイパッドに貫通孔が形成され、前記プ
リフォーム材が前記樹脂の外部に連通するように前記樹
脂が形成されていることを特徴とするものである。A semiconductor device according to the present invention is a semiconductor device in which a semiconductor chip is die-bonded to a die pad with a preform material, and the wire bonding portion around the semiconductor chip is sealed with a resin. A through hole is formed in the die pad, and the resin is formed so that the preform material communicates with the outside of the resin.
【０００９】[0009]
【作用】本発明によれば、ダイパッド裏面に連通する孔
を樹脂に形成すると共に、ダイパッドにも貫通孔を形成
しているため、ダイパッド表面のプリフォーム材の吸湿
性による水分の蒸気もダイパッドの貫通孔および樹脂の
孔を経由して外部に放出され、蒸気の膨張による樹脂と
の剥離の助長を防止し、樹脂のクラックも発生しない。According to the present invention, since the holes communicating with the back surface of the die pad are formed in the resin and the through holes are also formed in the die pad, moisture vapor due to the hygroscopicity of the preform material on the surface of the die pad is also formed in the die pad. It is released to the outside through the through hole and the resin hole, prevents the peeling from the resin due to the expansion of vapor, and prevents the resin from cracking.
【００１０】ダイパッドの貫通孔と樹脂の孔とが連続し
て形成されていれば、ダイパッド表面での蒸気を容易に
外部に放出できるが、樹脂の孔がダイパッドの貫通孔の
場所とは異なる所に形成されていても、ダイパッドと樹
脂とのあいだは剥離までは至らないが界面が形成されて
外部に連通しており、その界面を経由してダイパッドの
貫通孔および樹脂の孔を介して外部に放出され、樹脂の
剥離は生じない。If the through hole of the die pad and the resin hole are continuously formed, the vapor on the surface of the die pad can be easily discharged to the outside, but the resin hole is different from the place of the through hole of the die pad. Although it is not formed, the interface between the die pad and the resin does not occur until it is separated from the die pad and the resin communicates with the outside. The resin is not peeled off.
【００１１】[0011]
【実施例】つぎに、図面を参照しながら本発明について
詳細に説明する。図１は本発明の一実施例である半導体
装置の断面構造を示す説明図である。同図において、ダ
イパッド１の表面に半導体チップ３がＡｇペーストなど
のプリフォーム材４で接着され、ダイパッド１の周囲に
配置されたリード２と前記半導体チップ３の各電極パッ
ドが金線５で接続され、その周囲が樹脂６で封入されて
いる。本実施例ではこのダイパッド１に貫通孔11が設け
られると共に、樹脂６のダイパッド１の裏面側に孔61が
形成され、この実施例ではダイパッド１の貫通孔11と樹
脂の孔61が連続するように形成されている。The present invention will be described in detail with reference to the drawings. FIG. 1 is an explanatory diagram showing a cross-sectional structure of a semiconductor device which is an embodiment of the present invention. In the figure, the semiconductor chip 3 is adhered to the surface of the die pad 1 with a preform material 4 such as Ag paste, and the leads 2 arranged around the die pad 1 and the respective electrode pads of the semiconductor chip 3 are connected by gold wires 5. Then, the periphery thereof is sealed with resin 6. In this embodiment, a through hole 11 is provided in the die pad 1, and a hole 61 is formed on the back surface side of the die pad 1 of the resin 6. In this embodiment, the through hole 11 of the die pad 1 and the resin hole 61 are continuous. Is formed in.
【００１２】このダイパッド１の貫通孔11はダイパッド
１や各リード２をリードフレームでパンチングまたはエ
ッチングにより形成するときに同時に形成し、樹脂６の
孔61は半導体チップ３などを樹脂６で封入するとき、樹
脂成形の金型に突起を設けておくことにより容易に形成
できる。この貫通孔11および孔61の大きさはチップの大
きさ、プリフォーム材の材料や量などにより自由に選定
できるが、たとえば10mm角の半導体チップでＡｇペース
トのプリフォーム材を５〜30μｍ厚位で接着するばあ
い、直径４mmφ位の貫通孔が好ましい。また半導体チッ
プ３をダイパッド１にダイボンディングするとき、プリ
フォーム材４はダイパッド１の中心１箇所に塗布するの
ではなく、貫通孔11の周囲に散在させ、プリフォーム材
が接着面に拡がるように塗布する。The through hole 11 of the die pad 1 is formed simultaneously when the die pad 1 and each lead 2 are formed by punching or etching with a lead frame, and the hole 61 of the resin 6 is used when the semiconductor chip 3 and the like are sealed with the resin 6. It can be easily formed by providing protrusions on the resin molding die. The size of the through hole 11 and the hole 61 can be freely selected according to the size of the chip, the material and amount of the preform material, and for example, in a 10 mm square semiconductor chip, the preform material of Ag paste is 5 to 30 μm thick. In the case of adhering with, a through hole having a diameter of about 4 mmφ is preferable. Also, when the semiconductor chip 3 is die-bonded to the die pad 1, the preform material 4 is not applied to one central portion of the die pad 1, but is scattered around the through holes 11 so that the preform material spreads on the bonding surface. Apply.
【００１３】この貫通孔11および孔61を形成することに
よりプリフォーム材４の部分が直接外気に露出すること
となる。その結果、プリフォーム材４の吸湿性による水
分の蒸気が発生しても、貫通孔11および孔61を経由して
外部に逃げ、ダイパッド１と樹脂６とのあいだの剥離力
としては作用しない。また樹脂６の吸湿性による水分の
蒸気も、ダイパッド１の下面と樹脂６との界面を経て孔
61より外部に放出されるため、樹脂６を剥離する力とし
ては作用しない。そのため、ダイパッド１と樹脂６の剥
離には至らず、樹脂６のクラックも発生しない。By forming the through hole 11 and the hole 61, the portion of the preform material 4 is directly exposed to the outside air. As a result, even if moisture vapor is generated due to the hygroscopicity of the preform material 4, it escapes to the outside through the through hole 11 and the hole 61 and does not act as a peeling force between the die pad 1 and the resin 6. In addition, moisture vapor due to the hygroscopicity of the resin 6 also penetrates through the interface between the lower surface of the die pad 1 and the resin 6 to form holes.
Since it is released to the outside from 61, it does not act as a force for peeling the resin 6. Therefore, the die pad 1 and the resin 6 are not separated from each other, and the resin 6 is not cracked.
【００１４】前述の実施例ではダイパッド１の貫通孔11
と樹脂６の孔61とを連続して形成する例で説明したが、
この構成では内部の水分の蒸気を放出する効果は大きい
反面、半導体装置を使用する雰囲気が多湿雰囲気である
ばあいには、逆に外部の水蒸気がプリフォーム材の方に
容易に侵入し易くなる。最近の樹脂で封入する技術の向
上によりワイヤボンディング部の樹脂の密着性は向上
し、プリフォーム材に侵入した水分が直接ワイヤボンデ
ィング部分に侵入して腐蝕による特性劣化などは起り難
いが、その懸念を防止して内部の水分蒸気は容易に外部
に放出し、外部の水分は内部に侵入しにくい構造として
図２のような構造を採用することもできる。In the above embodiment, the through hole 11 of the die pad 1 is used.
Although the example in which the and the holes 61 of the resin 6 are continuously formed has been described,
With this configuration, the effect of releasing the vapor of the internal moisture is great, but on the contrary, when the atmosphere in which the semiconductor device is used is a humid atmosphere, on the contrary, external water vapor easily penetrates into the preform material. .. Due to the recent improvement in resin encapsulation technology, the resin adhesion at the wire bonding part is improved, and moisture that has entered the preform material does not directly enter the wire bonding part and is less likely to cause characteristic deterioration due to corrosion. It is also possible to employ a structure as shown in FIG. 2 as a structure in which the moisture vapor inside is easily released to the outside and moisture does not easily penetrate inside.
【００１５】図２は本発明の他の実施例である半導体装
置の断面構造の説明図である。同図において62、63は樹
脂６に設けた孔で、他の符号は図１と同じ部分を示し、
製造方法も図１と同様である。本実施例では、樹脂６に
設けた孔62、63がダイパッド１に形成した貫通孔11と連
続しないようにずらせて形成したものである。その結果
ダイパッド１の貫通孔11には樹脂６が充填されるが、ダ
イパッド１の材料はたとえば、Ｆｅ- Ｎｉ系42合金など
の金属材料で、樹脂とは材料が異なり、両者のあいだに
は界面が形成されており、プリフォーム材４と孔62、63
とは界面を介して連通している。そのため、内部の水分
が蒸気化して圧力が高くなるとこの界面を経由して蒸気
が外部に放出されるが、圧力がかからないときはこの面
を通過せず、外部からの水分は内部に侵入しにくい。す
なわちプリフォーム材４は貫通孔11と孔62、63および樹
脂６とダイパッド１の界面を経由して外部に連通してお
り、プリフォーム材４の水分蒸気の蒸気圧が大きくなる
と外部に放出され易くなるように構成されている。FIG. 2 is an explanatory view of a sectional structure of a semiconductor device according to another embodiment of the present invention. In the figure, 62 and 63 are holes provided in the resin 6, and other reference numerals indicate the same parts as in FIG.
The manufacturing method is the same as in FIG. In this embodiment, the holes 62 and 63 formed in the resin 6 are formed so as not to be continuous with the through holes 11 formed in the die pad 1. As a result, the resin 6 is filled in the through holes 11 of the die pad 1, but the material of the die pad 1 is, for example, a metallic material such as Fe-Ni-based 42 alloy, which is different from the resin and has an interface between them. Are formed, and the preform material 4 and the holes 62 and 63 are formed.
And are in communication via the interface. Therefore, when the internal moisture vaporizes and the pressure rises, the vapor is released to the outside via this interface, but when pressure is not applied, it does not pass through this surface, and moisture from the outside does not easily enter the inside. .. That is, the preform material 4 communicates with the outside through the through holes 11, the holes 62, 63 and the interface between the resin 6 and the die pad 1, and is released to the outside when the vapor pressure of the moisture vapor of the preform material 4 increases. It is configured to be easy.
【００１６】前述の第２の実施例では、樹脂６に形成し
た孔を２個の例で説明したが、これを貫通孔11の外側を
とりまくようなリング状の孔で形成することもでき、ま
た２個以上の多数個の孔で形成することもできる。さら
に第１の実施例も共に、ダイパッドに形成する貫通孔も
１個でなく多数個形成することもできる。また前述の第
２の実施例で貫通孔11に樹脂６を充填する例で説明した
が、プリフォーム材４で貫通孔11を充填しても同様であ
ることはいうまでもない。In the above-mentioned second embodiment, the two holes formed in the resin 6 have been described, but it is also possible to form the holes in a ring shape surrounding the outside of the through hole 11. It can also be formed with a large number of holes, two or more. Further, in both the first embodiment and the die pad, a large number of through holes may be formed instead of one. Although the second embodiment has been described with reference to the example in which the through hole 11 is filled with the resin 6, it goes without saying that the same applies when the through hole 11 is filled with the preform material 4.
【００１７】[0017]
【発明の効果】以上説明したように本発明によれば、樹
脂が吸湿した水分のみでなく、プリフォーム材が吸湿し
た水分の蒸気も有効に成形された樹脂の外に放出できる
ため、ハンダのリフローなどプリント基板への装着時に
高温になっても、樹脂とダイパッドの界面に水分が拡散
して蒸気の膨張による樹脂の剥離やクラックが生じると
いうことはない。そのため、歩留が向上し、信頼性の高
い半導体装置をえられる。As described above, according to the present invention, not only the moisture absorbed by the resin but also the moisture vapor absorbed by the preform material can be effectively discharged to the outside of the molded resin. Even if the temperature becomes high during mounting on a printed circuit board such as reflow, moisture does not diffuse at the interface between the resin and the die pad, and peeling or cracking of the resin due to expansion of vapor does not occur. Therefore, the yield is improved and a highly reliable semiconductor device can be obtained.
【図１】本発明の一実施例である半導体装置の断面構造
を示す説明図である。FIG. 1 is an explanatory diagram showing a cross-sectional structure of a semiconductor device that is an embodiment of the present invention.
【図２】本発明の他の実施例である半導体装置の断面構
造を示す説明図である。FIG. 2 is an explanatory diagram showing a cross-sectional structure of a semiconductor device according to another embodiment of the present invention.
【図３】従来の半導体装置の樹脂にクラックの入った例
を説明する図である。FIG. 3 is a diagram illustrating an example in which a resin of a conventional semiconductor device has cracks.
１ ダイパッド ３ 半導体チップ ４ プリフォーム材 ６ 樹脂 11 貫通孔 61、62、63 孔 1 Die pad 3 Semiconductor chip 4 Preform material 6 Resin 11 Through holes 61, 62, 63 holes
Claims (3)
ム材でダイボンディングされ、該半導体チップおよびそ
の周囲のワイヤボンディング部が樹脂で封入されてなる
半導体装置であって、前記ダイパッドに貫通孔が形成さ
れ、前記プリフォーム材が前記樹脂の外部に連通するよ
うに前記樹脂が成形されていることを特徴とする半導体
装置。1. A semiconductor device in which a semiconductor chip is die-bonded to a die pad with a preform material, and the semiconductor chip and a wire bonding portion around the semiconductor chip are sealed with a resin, wherein a through hole is formed in the die pad. A semiconductor device, wherein the resin is molded so that the preform material communicates with the outside of the resin.
樹脂に孔が形成され、前記プリフォーム材が前記樹脂の
外部に連通していることを特徴とする請求項１記載の半
導体装置。2. The semiconductor device according to claim 1, wherein holes are formed in the resin so as to be continuous with the through holes of the die pad, and the preform material communicates with the outside of the resin.
位置で前記樹脂に孔が形成され、前記ダイパッドと前記
樹脂との界面を介して前記プリフォーム材が前記樹脂の
外部に連通していることを特徴とする請求項１記載の半
導体装置。3. A hole is formed in the resin at a position deviated from the position of the through hole of the die pad, and the preform material communicates with the outside of the resin through an interface between the die pad and the resin. The semiconductor device according to claim 1, wherein:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5242492A JP3179845B2 (en) | 1992-03-11 | 1992-03-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5242492A JP3179845B2 (en) | 1992-03-11 | 1992-03-11 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05259344A true JPH05259344A (en) | 1993-10-08 |
| JP3179845B2 JP3179845B2 (en) | 2001-06-25 |
Family
ID=12914403
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5242492A Expired - Fee Related JP3179845B2 (en) | 1992-03-11 | 1992-03-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3179845B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2021186657A1 (en) * | 2020-03-19 | 2021-09-23 |
-
1992
- 1992-03-11 JP JP5242492A patent/JP3179845B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2021186657A1 (en) * | 2020-03-19 | 2021-09-23 | ||
| WO2021186657A1 (en) * | 2020-03-19 | 2021-09-23 | 三菱電機株式会社 | Semiconductor device and method for manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3179845B2 (en) | 2001-06-25 |
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