JPH05259310A - Hybrid ic - Google Patents

Hybrid ic

Info

Publication number
JPH05259310A
JPH05259310A JP4706892A JP4706892A JPH05259310A JP H05259310 A JPH05259310 A JP H05259310A JP 4706892 A JP4706892 A JP 4706892A JP 4706892 A JP4706892 A JP 4706892A JP H05259310 A JPH05259310 A JP H05259310A
Authority
JP
Japan
Prior art keywords
protective layer
shield layer
conductive material
layer
hybrid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4706892A
Other languages
Japanese (ja)
Other versions
JP2556794B2 (en
Inventor
Kenichiro Sugimoto
健一朗 杉本
Shinichi Wakita
真一 脇田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tatsuta Electric Wire and Cable Co Ltd
Original Assignee
Tatsuta Electric Wire and Cable Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tatsuta Electric Wire and Cable Co Ltd filed Critical Tatsuta Electric Wire and Cable Co Ltd
Publication of JPH05259310A publication Critical patent/JPH05259310A/en
Application granted granted Critical
Publication of JP2556794B2 publication Critical patent/JP2556794B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Compositions Of Macromolecular Compounds (AREA)

Abstract

PURPOSE:To facilitate and secure the connection between a ground lead terminal and a shield layer when forming the shield layer 6 of a hybrid IC by dip coating. CONSTITUTION:A protective layer 5 is made by soaking a substrate 1, where electronic part elements 2 and 3 are mounted, in insulating resin bath, in the condition that a conducive material 7 is laid on the ground lead terminal 4a, and a shield layer 6 is made by soaking the said substrate 1 in conductive coating bath, including a bend, after bending the conductive material 7 projecting from the protective layer 5 onto the top side of the protective layer 5.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、基板上の電子部品素
子が絶縁性樹脂の保護層により封止され、その上にシー
ルド層が形成されたハイブリッドICに関するものであ
り、とくに基板上のグランドラインとシールド層の接続
構造を特徴とする。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid IC in which an electronic component element on a substrate is sealed by a protective layer made of an insulating resin and a shield layer is formed on the protective layer. It features a connection structure between the line and the shield layer.

【0002】[0002]

【従来の技術及びその課題】ハイブリッドICはプリン
ト配線基板上に実装して用いられ、その電子部品素子は
絶縁性樹脂の保護層によって被覆されて、外部環境から
の保護がなされ、さらにその上にシールド層が形成され
て、このハイブリッドICから出る電磁波の外部への影
響及び外部からハイブリッドICへの影響を遮断するよ
うになっている。
2. Description of the Related Art A hybrid IC is mounted on a printed wiring board for use, and its electronic component element is covered with a protective layer of an insulating resin to protect it from the external environment. A shield layer is formed to block the external influence of the electromagnetic wave emitted from the hybrid IC and the external influence on the hybrid IC.

【0003】そのシールド層の形成には、金属ケースの
外装を設ける手段と、実開昭61−75192号公報等
に示される導電性物質を塗布する手段とがある。前者は
形状が大型となり高値である。一方、後者はハイブリッ
ドIC全体を小型化し得るとともに製作コストも安価で
あるという利点がある。
To form the shield layer, there are means for providing an outer case of a metal case and means for applying a conductive substance as disclosed in Japanese Utility Model Laid-Open No. 61-75192. The former has a large shape and is expensive. On the other hand, the latter has the advantage that the entire hybrid IC can be downsized and the manufacturing cost is low.

【0004】そして、後者の手段におけるグランドライ
ンとシールド層の接続構造として、上記公開公報に電子
部品素子間のグランドライン上に設けたグランドチップ
で行うものが開示されている。
As the connection structure between the ground line and the shield layer in the latter means, the above-mentioned publication discloses a structure in which a ground chip provided on the ground line between electronic component elements is used.

【0005】しかし、この技術は、チップが電子部品素
子間にあるため、電子部品素子の配置に制限が生じ、ま
たグランドチップを小さいものにすると、シールド層と
の接続が不確実になるなどの不都合がある。
However, in this technique, since the chip is between the electronic component elements, the arrangement of the electronic component elements is limited, and if the ground chip is made small, the connection with the shield layer becomes uncertain. There is inconvenience.

【0006】この発明は、上記実情に鑑み、グランドラ
インとシールド層の接続を保護層の外側で容易になし得
るようにすることを課題とする。
In view of the above situation, it is an object of the present invention to easily connect the ground line and the shield layer outside the protective layer.

【0007】[0007]

【課題を解決するための手段】上記の課題を解決するた
めに、この発明にあっては、基板上に電子部品素子を搭
載し、その上を絶縁性樹脂の保護層で被覆するととも
に、所要数のリード端子をその保護層から突出させ、前
記保護層上にシールド層を形成した従来周知のハイブリ
ッドICにおいて、前記リード端子のグランドリード端
子と保護層間にその端子に電気的に接続された屈曲可能
な導電材が介設され、その導電材は前記保護層から突出
したのち内側に屈曲して前記保護層と前記シールド層の
間に介設されてそのシールド層に電気的に接続されてい
る構成としたのである。
In order to solve the above-mentioned problems, according to the present invention, an electronic component element is mounted on a substrate, and a protective layer of an insulating resin is formed on the electronic component element. In a conventionally known hybrid IC having a number of lead terminals protruding from the protective layer and a shield layer formed on the protective layer, a bend electrically connected to the ground lead terminal of the lead terminal and the protective layer. A possible conductive material is provided, and the conductive material is protruded from the protective layer and then bent inward to be interposed between the protective layer and the shield layer and electrically connected to the shield layer. It has been configured.

【0008】このように構成するハイブリッドICは、
電子部品素子を搭載した基板を、上記導電材をグランド
リード端子に重ねた状態で絶縁性樹脂浴に浸漬して上記
保護層を形成し、その保護層から突出する導電材を保護
層上面に屈曲したのち、その屈曲部を含めて、前記基板
を導電塗料浴に浸漬して上記シールド層を形成するとよ
い。
The hybrid IC thus constructed is
The board on which the electronic component element is mounted is immersed in an insulating resin bath with the conductive material stacked on the ground lead terminal to form the protective layer, and the conductive material protruding from the protective layer is bent on the upper surface of the protective layer. After that, the shield layer including the bent portion may be dipped in a conductive paint bath to form the shield layer.

【0009】上記シールド層用導電塗料としては、公知
の種々のもの、例えば、下記の(A)乃至(D)の配合
のもの、又は(A′)〜(E′)の配合のものを使用す
る。
As the above-mentioned conductive paint for the shield layer, various known ones, for example, the following blends (A) to (D) or (A ') to (E') are used. To do.

【0010】 記 (A)0.05〜0.2重量部のチタネート、ジルコネ
ート、またはその混合物により表面被覆した、金属銅粉
100重量部 (B)レゾール型フェノール樹脂5〜33重量部 (C)アミノ化合物0.5〜3.5重量部 (D)キレート層形成剤3.0〜10重量部。
Note (A) 100 parts by weight of metallic copper powder surface-coated with 0.05 to 0.2 parts by weight of titanate, zirconate, or a mixture thereof (B) 5 to 33 parts by weight of resol type phenolic resin (C) Amino compound 0.5 to 3.5 parts by weight (D) Chelate layer forming agent 3.0 to 10 parts by weight.

【0011】 記 (A′)0.05〜0.2重量部のチタネート、ジルコ
ネート、またはその混合物により表面被覆した、金属銅
粉100重量部 (B′)レゾール型フェノール樹脂5〜30重量部 (C′)チキソトロピック調整材0.5〜4重量部 (D′)アミノ化合物0.5〜3.5重量部 (E′)キレート層形成材3.0〜10重量部。
(A ') 100 parts by weight of metal copper powder surface-coated with 0.05 to 0.2 parts by weight of titanate, zirconate, or a mixture thereof (B') 5 to 30 parts by weight of resol type phenolic resin ( C ′) 0.5 to 4 parts by weight of thixotropic adjusting material (D ′) 0.5 to 3.5 parts by weight of amino compound (E ′) 3.0 to 10 parts by weight of chelate layer forming material.

【0012】上記レゾール型フェノール樹脂は下記のも
のとするとよい。 記 2−1置換体、2,4−2置換体、2,4,6−3置換
体、メチロール基、ジメチレンエーテル、フェニル基の
各赤外線透過率をl,m,n,a,b,cとするとき、
各透過率の間に、 (イ)l/n=0.8〜1.2 (ロ)m/n=0.8〜1.2 (ハ)b/a=0.8〜1.2 (ニ)c/a=1.2〜1.5 なる関係が成り立つレゾール型フェノール樹脂。
The above-mentioned resol type phenol resin is preferably the following. The 2-1 substitution product, 2,4-2 substitution product, 2,4,6-3 substitution product, methylol group, dimethylene ether, each infrared transmittance of phenyl group is 1, m, n, a, b, When we say c,
Between each transmittance, (a) l / n = 0.8 to 1.2 (b) m / n = 0.8 to 1.2 (c) b / a = 0.8 to 1.2 ( D) A resole-type phenol resin in which the relationship of c / a = 1.2 to 1.5 is established.

【0013】基板材料は、エポキシ樹脂、フェノール樹
脂、ガラス繊維、セラミックスなどの絶縁材とする。導
電材は、銅箔などの屈曲可能で導電性の高いものを適宜
に使用する。なお、上記導電塗料の詳細は特開平2−1
6172号公報、特開平3−6254号公報等を参照。
The substrate material is an insulating material such as epoxy resin, phenol resin, glass fiber or ceramics. As the conductive material, a bendable and highly conductive material such as copper foil is appropriately used. The details of the conductive paint are described in JP-A-2-1.
See Japanese Patent No. 6172 and Japanese Patent Laid-Open No. 3-6254.

【0014】[0014]

【作用】このように構成するこの発明に係るグランド用
導電材は屈曲可能なため、保護層とシールド層のディッ
プコーティングの順序に適応して屈曲できるクランド接
続材とすることができ、作業性がよく、かつシールド層
との接続が確実となる。
Since the grounding conductive material according to the present invention configured as described above is bendable, it can be used as a cland connecting material that can be bent in accordance with the order of dip coating of the protective layer and the shield layer, and the workability is improved. Good and secure connection with the shield layer.

【0015】[0015]

【実施例】まず、導電塗料は、粒径5〜10μmの比表
面積0.4m2 /g以下、水素還元減量0.25%以下
の樹枝状金属銅粉100重量部を攪拌機に入れて、チタ
ネートを少量ずつ添加しながら攪拌して、チタネートを
金属銅粉の表面に被覆させた。しかるのち、その金属銅
粉に、還元剤のアミノフェノール、キレート層形成剤の
トリエタノールアミン、特開平2−16172号公報記
載のレゾール型フェノール樹脂、チキソトロピック調整
剤であるポリビニルブチラール樹脂(BM−1、積水化
学社製)をそれぞれ表1に示す割合で配合し、溶剤とし
て、エチルカルビトールとブチルセロソルブの混合溶剤
を加え、20分間3軸ロールで定位置練りし、粘度がリ
オン社製の測定機VT−04により20〜40Pとなる
ようにして、導電塗料浴を得た。
EXAMPLE First, 100 parts by weight of dendritic metal copper powder having a specific surface area of 0.4 m 2 / g or less and a hydrogen reduction weight loss of 0.25% or less having a particle size of 5 to 10 μm was put into a stirrer to prepare a titanate. Was added little by little and stirred to coat the surface of the metallic copper powder with titanate. Thereafter, the metal copper powder was added to the reducing agent aminophenol, the chelate layer forming agent triethanolamine, the resol type phenol resin described in JP-A-2-16172, and the polyvinyl butyral resin (BM- 1, Sekisui Chemical Co., Ltd.) were mixed in the proportions shown in Table 1, a mixed solvent of ethyl carbitol and butyl cellosolve was added as a solvent, and the mixture was kneaded in place with a triaxial roll for 20 minutes to measure the viscosity by Rion A machine of VT-04 was used to obtain 20 to 40 P to obtain a conductive paint bath.

【0016】エチルカルビトールや、ブチルセロソルブ
に代えて、ブチルカルビトール、ブチルカルビトールア
セテート、ブチルセロソルブアセテート、メチルイソブ
チルケトン、トルエン、キシレン等公知のものを使用す
ることができる。
In place of ethyl carbitol or butyl cellosolve, known ones such as butyl carbitol, butyl carbitol acetate, butyl cellosolve acetate, methyl isobutyl ketone, toluene and xylene can be used.

【0017】[0017]

【表1】 [Table 1]

【0018】一方、図1に示すように、エポキシ樹脂基
板1上に、各種チップ部品2、抵抗3等の電子部品素子
を搭載又は印刷して設けるとともに、その回路から所要
数のリード端子4…、4aを突出させる。
On the other hand, as shown in FIG. 1, electronic component elements such as various chip components 2 and resistors 3 are mounted or printed on the epoxy resin substrate 1, and a required number of lead terminals 4 ... 4a is projected.

【0019】その基板1を、グランドリード端子4aの
基部4a′に銅箔の導電材7を添わせてエポキシ樹脂浴
中に浸漬し、所要厚の保護層5を形成する。その浸漬の
際、各リード端子4…、4aの露出部(接続部)まで、
すなわち、接続部を残して浸漬し、各リード端子4……
間が確実に樹脂で充填被覆されるようにする。これは、
後述のシールド層6とリード端子4を短絡させないため
である。
The substrate 1 is dipped in an epoxy resin bath with a copper foil conductive material 7 added to the base 4a 'of the ground lead terminal 4a to form a protective layer 5 having a required thickness. During the dipping, up to the exposed parts (connection parts) of the lead terminals 4, ..., 4a,
In other words, the lead terminal 4 is immersed by immersing it with the connection part left.
Ensure that the space is filled and covered with resin. this is,
This is because the shield layer 6 and the lead terminal 4 which will be described later are not short-circuited.

【0020】つづいて、導電材7の突出部分を保護層5
側(内側)に屈曲し、その状態の基板1を、前記各導電
塗料浴に浸漬して、所要厚のシールド層6を形成する。
その浸漬深さはリード端子4、4a側の保護層5の縁に
到らないようにする。このとき、導電材7上にもシール
ド層6が形成され、導電材7を介し、グランドリード端
子4aとシールド層6が電気的に接続される。
Subsequently, the protruding portion of the conductive material 7 is covered with the protective layer 5.
The substrate 1 bent to the side (inside) and in that state is dipped in each of the conductive paint baths to form a shield layer 6 having a required thickness.
The immersion depth should not reach the edge of the protective layer 5 on the side of the lead terminals 4 and 4a. At this time, the shield layer 6 is also formed on the conductive material 7, and the ground lead terminal 4 a and the shield layer 6 are electrically connected via the conductive material 7.

【0021】この各実施例においては、十分な効果を有
するシールド層6とすることができ、また、シールド層
6とグランドリード端子4aの導電性も支障はなかっ
た。なお、実施例5〜6はチキソトロピック調整剤を添
加しているので、添加していない実施例1〜4に比べ、
ディップコーティング後にだれを生じなかった。
In each of the embodiments, the shield layer 6 having a sufficient effect can be obtained, and the conductivity of the shield layer 6 and the ground lead terminal 4a has no problem. In addition, since Examples 5-6 added the thixotropic adjuster, compared with Examples 1-4 which did not add,
No sagging after dip coating.

【0022】[0022]

【発明の効果】この発明は以上のように構成したので、
基板上のグランドラインとシールド層が確実に導電し、
ハイブリッドICの製作性もよく、製造コストの低減を
図り得る。
Since the present invention is constructed as described above,
Make sure that the ground line on the board and the shield layer are conductive,
The hybrid IC has good manufacturability, and the manufacturing cost can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】aは一実施例の正面図、bは同図のX−X線断
面図
1 is a front view of one embodiment, and b is a sectional view taken along line XX of FIG.

【符号の説明】[Explanation of symbols]

1 基板 2 チップ部品 3 抵抗 4 リード端子 4a グランドリード端子 5 保護層 6 シールド層 7 導電材 1 substrate 2 chip component 3 resistor 4 lead terminal 4a ground lead terminal 5 protective layer 6 shield layer 7 conductive material

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 基板上に電子部品素子を搭載し、その上
を絶縁性樹脂の保護層で被覆するとともに、所要数のリ
ード端子をその保護層から突出させ、前記保護層上にシ
ールド層を形成したハイブリッドICにおいて、前記リ
ード端子のグランドリード端子と保護層間にその端子に
電気的に接続された屈曲可能な導電材が介設され、その
導電材は前記保護層から突出したのち内側に屈曲して前
記保護層と前記シールド層の間に介設されてそのシール
ド層に電気的に接続されていることを特徴とするハイブ
リッドIC。
1. An electronic component element is mounted on a substrate, a protective layer made of an insulating resin is coated on the electronic component element, a required number of lead terminals are projected from the protective layer, and a shield layer is formed on the protective layer. In the formed hybrid IC, a bendable conductive material electrically connected to the terminal is provided between the ground lead terminal of the lead terminal and the protective layer, and the conductive material is bent inward after protruding from the protective layer. Then, the hybrid IC is provided between the protective layer and the shield layer and electrically connected to the shield layer.
【請求項2】 請求項1に記載のハイブリッドICを製
造するに際し、電子部品素子を搭載した基板を、上記導
電材をグランドリード端子に重ねた状態で絶縁性樹脂浴
に浸漬して上記保護層を形成し、その保護層から突出す
る導電材を保護層上面に屈曲したのち、その屈曲部を含
めて、前記基板を導電塗料浴に浸漬して上記シールド層
を形成することを特徴とするハイブリッドICの製造方
法。
2. When manufacturing the hybrid IC according to claim 1, the substrate on which the electronic component element is mounted is immersed in an insulating resin bath in a state where the conductive material is placed on a ground lead terminal, and the protective layer is formed. And a conductive material protruding from the protective layer is bent on the upper surface of the protective layer, and then the substrate including the bent portion is immersed in a conductive paint bath to form the shield layer. IC manufacturing method.
JP4047068A 1992-01-13 1992-03-04 Hybrid IC Expired - Fee Related JP2556794B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP4-4023 1992-01-13
JP402392 1992-01-13

Publications (2)

Publication Number Publication Date
JPH05259310A true JPH05259310A (en) 1993-10-08
JP2556794B2 JP2556794B2 (en) 1996-11-20

Family

ID=11573369

Family Applications (2)

Application Number Title Priority Date Filing Date
JP4047068A Expired - Fee Related JP2556794B2 (en) 1992-01-13 1992-03-04 Hybrid IC
JP4047105A Expired - Fee Related JP2526194B2 (en) 1992-01-13 1992-03-04 Hybrid IC

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP4047105A Expired - Fee Related JP2526194B2 (en) 1992-01-13 1992-03-04 Hybrid IC

Country Status (1)

Country Link
JP (2) JP2556794B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62235799A (en) * 1986-04-07 1987-10-15 日本電気株式会社 Hybrid integrated circuit device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62235799A (en) * 1986-04-07 1987-10-15 日本電気株式会社 Hybrid integrated circuit device

Also Published As

Publication number Publication date
JP2556794B2 (en) 1996-11-20
JPH05259318A (en) 1993-10-08
JP2526194B2 (en) 1996-08-21

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