JPH05258082A - Microcomputer - Google Patents

Abstract

PURPOSE:To provide a computer in which one kind of clock is used for both a CPU and a refresh counter, and a refresh cycle is not affected even at the time of changing only a CPU clock. CONSTITUTION:A clock 101 is frequency-divided by a clock frequency-divider 12, and frequency-division clocks 102-104 are outputted and inputted to a three- input selector 13. The output 106 of a clock selection register 15 is inputted to the selector 13, one of the frequency-division clocks 102-104 is selected, and inputted to a clock driver 14 and a CPU 11. The writing of the output 109 of the CPU 11 is operated to a refresh interval setting register 16, and the output 110 of the register 16 is inputted and loaded to a refresh counter 17. A clock 108 is divided by the counter 17, refresh output signals 112-114 are outputted, one of them is selected by a three-input selector 18 after a clock selection register output signal 111 is received, and a refresh signal 115 is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly to a microcomputer provided with a refresh interval timer for measuring a refresh cycle.

[0002]

2. Description of the Related Art In a conventional microcomputer of this type, a clock generator for dividing a clock input from the outside is provided, and only one system clock is used as a CPU clock and a refresh counter clock. It is common to have

FIG. 3 is a block diagram of a conventional microcomputer, which includes a CPU 31, a clock frequency divider 32, a 3-input selector 33, a clock driver 34,
A clock selection register 35, a refresh interval setting register 36, a refresh counter 37, etc.
01 is frequency-divided in the clock frequency divider 32 and is input to the 3-input selector 33 as frequency-divided clocks 302, 303 and 304. For the 3-input selector 33,
The clock selection signal 306 output from the clock selection register 35 is input via the CPU output 305, and one of the divided clocks 302, 303, and 304 is supplied via this clock selection signal 306. Selected, CPU via clock driver 34
31 is input. The clock 308 output from the clock driver 34 is also input to the refresh counter 37, and the refresh counter 37 outputs a predetermined refresh signal 318.

[0004]

In the conventional microcomputer described above, for example, when the configuration shown in FIG. 3 is adopted, the refresh interval is set when the input clock itself to the CPU is changed. Therefore, it is necessary to change the value of the refresh interval setting register at the same time, which makes register calls unnecessary for program design, which is extremely inefficient. It has the drawback of being easy to induce.

[0005]

A microcomputer according to the present invention is a clock selection register for selecting a division ratio of a clock input to a CPU, and a division ratio of the clock according to a division ratio specified by the clock selection register. The frequency divider that performs frequency division, the refresh interval setting register that sets the refresh interval to refresh the dynamic memory, and the refresh interval that is specified by the refresh interval setting register, and the clock output from the frequency divider. A refresh counter that counts with a count clock,
And a selector for selecting and outputting the divided output of the refresh counter according to the designation of the clock selection register.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG. 1, this embodiment uses CP
U11, clock divider 12, and 3-input selector 13
And 18, a clock driver 14, a clock selection register 15, a refresh interval setting register 16, and a refresh counter 17.

In FIG. 1, an externally input clock 101 is input to a clock frequency divider 12 for frequency division, and frequency-divided clocks 102, 103 and 104 are output and input to a 3-input selector 13. For the 3-input selector 13, the clock selection signal 106 output from the clock selection register 15 via the CPU output 105.
Is input, and one of the divided clocks 102, 103, and 104 is selected via the clock selection signal 106, and the clock driver 14 is selected.
Is input to the CPU 11 via. The clock 108 output from the clock driver 14 is also input to the refresh counter 17.

Further, the CPU output 109 is written to the refresh interval setting register 16, but this refresh interval setting register 1
The output 110 of 6 is input to the 8-stage refresh counter 17 and the content thereof is loaded. In the refresh counter 17, the clock 108 is 25 at maximum.
Predetermined refresh counter output signal 1 divided into 6
12 (256 frequency division output), 113 (128 frequency division output) and 114 (64 frequency division output) are output and input to the 3-input selector 18, respectively. 3-input selector 18
In response to the clock selection register output signal 111 of the clock selection register 15, one of the three refresh counter output signals 112, 113 and 114 is selected and output as the refresh signal 115. At that time, the divided clock 10
2, 103 and 104 and the refresh counter output signals 112, 113 and 114,
Divided clock 102 and refresh counter output signal 1
14, divided clock 103 and refresh counter output signal 113, divided clock 104 and refresh counter output signal 112 are selected in the form of pairs,
The clock selection register output signal 111 is output from the clock selection register 15.

When such a configuration is adopted, for example, 1/2 times the clock is selected and input to the CPU 11, and the refresh interval setting register 1
The operation when the clock for the CPU 11 is changed to 1/8 times when 0 is set for 6 will be described below.

Clock selection register 15 from CPU 11
When the write is performed on the divided clock 103, the divided clock 103 is selected in the 3-input selector 13, and the clock 1
It is input to the clock driver 14 as 07. This clock 107 is sent to the CPU 1 via the clock driver 14.
In addition to being input to 1, the refresh counter 17 is also input. On the other hand, the output 111 of the clock selection register 15 is input to the 3-input selector 18, whereby the refresh signal 114 is selected in the clock selection register 15 and the refresh signal 11 is selected.
5, the refresh signal 115 is output.
Are held the same as before the change of the clock division number for the CPU 11. On the contrary, when the clock division number is changed from ⅛ to ½, in the 3-input selector 18, the refresh signal 112 is selected so that the output of the refresh signal 115 is also the clock division number. It is kept the same as before the number change.

Next, FIG. 2 is a block diagram showing a second embodiment of the present invention. As shown in FIG. 2, in this embodiment, the CPU 21, the clock divider 22, the 3-input selectors 23 and 28, the clock driver 24, the clock selection register 25, the refresh interval setting register 26, and the refresh It comprises a counter 27 and a clock master register 29.

As is clear from the comparison between FIGS. 2 and 1, the difference between this embodiment and the first embodiment is that the clock mask register 29 is added. The operation of the constituent elements not directly related to the function of the clock mask register 29 is the same as in the case of the first embodiment described above.

In FIG. 2, an externally input clock 201 is input to a clock frequency divider 22 for frequency division, frequency-divided clocks 202, 203 and 204 are output and input to a 3-input selector 23. For the 3-input selector 23, the clock selection signal 206 output from the clock selection register 25 via the CPU output 205.
Is input, and one of the divided clocks 202, 203, and 204 is selected via the clock selection signal 206, and the clock driver 24
Is input to the CPU 21 via. The clock 208 output from the clock driver 24 is also input to the refresh counter 27.

The CPU output 209 is written to the refresh interval setting register 26. The refresh interval setting register 2
The output 210 of 6 is input to the eight-stage refresh counter 27 and the contents thereof are loaded. In the refresh counter 27, the clock 108 is 25 at maximum.
It is divided into 6 and a predetermined refresh counter output signal 2
12 (256 frequency division output), 213 (128 frequency division output) and 214 (64 frequency division output) are output and input to the 3-input selector 28, respectively.

On the other hand, in the clock master register 29, when the output 217 from the CPU 21 is written, the input of the output signal 216 of the clock selection register 25 is masked and the signal 218 output from the clock mask register 29 is masked. In the 3-input selector 28, one of the refresh counter output signals 212, 213 and 214 is selected and output as the refresh signal 215. In this case, when the clock mask register is set, the operation of the CPU 21 and the clock input to the refresh counter 27 work in the same manner.

The operation other than the operation by the clock mask register 29 is the same as that of the first embodiment.

[0018]

As described above, the present invention provides a CPU
While using the same clock as the count clock of the internal refresh counter, it is possible to execute the instruction to operate only at the CPU at different frequencies with one input / output instruction, which makes it possible to improve the efficiency of program design. In addition to the above effect, there is a secondary effect that it is possible to prevent destruction of the contents of the dynamic memory due to a setting mistake.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional example.

[Explanation of symbols]

11, 21, 22 CPU 12, 22, 23 Clock divider 13, 18, 23, 28, 33 3 Input selector 14, 24, 34 Clock driver 15, 25, 35 Clock selection register 16, 26, 36 Refresh interval setting Registers 17, 27, 37 Refresh counter 29 Clock master register

Claims (1)

[Claims] 1. A clock selection register for selecting a division ratio of a clock input to a CPU, a divider for dividing the clock according to a division ratio specified by the clock selection register, and a dynamic memory. A refresh interval setting register for setting a refresh interval for refreshing; and a refresh counter for counting the refresh interval by counting the clock output from the frequency divider by the designation of the refresh interval setting register, A microcomputer, comprising: a selector that selects and outputs a frequency-divided output of the refresh counter according to a designation of a clock selection register.