JPS6235137B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device having a display function.

In recent years, with the development of large-scale integrated circuit (LSL) technology, the scope of application of microcomputers that have data processing functions on a single chip has rapidly expanded, and they have also been widely applied to consumer devices aimed at general consumers.
Most can be controlled by a one-chip microcomputer. Relatively inexpensive display devices such as LEDs (light emitting diodes) and fluorescent display tubes are most often used as output devices for such consumer devices.

On the other hand, in order for a microcomputer to drive a display device, it must generate digit signals and segment signals indicating what should be displayed in which digit, and the hardware mechanism for this purpose is extremely complicated. Therefore, if a separate display control device is used, the microcomputer only needs to transfer display data to the display control device.
Although the display control function of the microcomputer can be omitted, an external display control device is required, which has the disadvantage of increasing the price. For this reason, it is necessary to equip a microcomputer, which can be manufactured at a relatively low cost, with functions capable of generating digit signals and segment signals and further controlling the display device.

Conventional microcomputers with display functions include display-only hardware such as electronic desktop calculators, namely a digit signal counter for generating digit signals, a mechanism for generating segment signals synchronized with the digit signals, and these devices. Some devices have a display control mechanism that controls the display signals of , and perform display processing without the intervention of software. However, since electronic desktop calculators have limited display devices, the display pattern is fixed and the number of displayed digits is also constant, making them lacking in versatility. In addition, dedicated display hardware cannot use the ports (including input/output terminals) from which display signals are output for any purpose other than display, even if display processing is not performed.
The display mechanism cannot be used for data processing other than display, and the use efficiency is extremely low, especially in microcomputers with a limited number of terminals.

In addition to the above, there are also microcomputers that perform display processing using program processing, so-called software, instead of dedicated display hardware. This is software controlled, so
Although a port through which a display signal is output can be freely used for other processing by a program, display processing and other data processing must be performed in a time-sharing manner. Therefore, if the ratio of the period during which one digit signal is activated to the scanning period of all digit signals (hereinafter referred to as display duty) is set to exceed a predetermined value, the display will flicker and the brightness will decrease. This causes a significant deterioration in display quality. Therefore, when creating a display control program, the program must be created keeping in mind the period of the digit signal and the display duty, which requires extremely difficult work.
In other words, in software processing, the control program is divided according to the period of the digit signal, and display processing is performed to calculate the period of the digit signal and create a display signal so that the display signal can be created between the divided control programs. Complicated control must be added to insert the program into the control program. Therefore, not only the control program is interrupted for display processing, but also the development period (processing period) of the entire program is lengthened. Furthermore, when a control program and a display processing program are executed in a time-sharing manner, the display duty changes depending on the execution time of the control program, and when the execution time of the control program is long, the display duty becomes extremely small and becomes clear. There was a drawback that it was not possible to display a clear image. In addition, inserting a display processing program into the control program increases the processing time of the entire program, and if the operating frequency of the microcomputer is increased to overcome this, power consumption increases significantly. Put it away. In particular, consumer appliances often use batteries as a power source, and there is a problem of backup during power outages, which is a serious drawback in that they consume a lot of power.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a data processing device that has a display function and is versatile.

Furthermore, another object of the present invention is to provide a novel data processing device in which input/output terminals used for display processing can be used for data processing other than display.

The present invention provides a data processing device that performs display processing and normal data processing, including a memory that stores both display data and data processing data;
a first addressing circuit that reads data for display from the memory; a second addressing circuit that reads data for data processing from the memory; and a period during which the memory is not used in each instruction machine cycle during normal data processing. a clock timing circuit that generates a clock output; a first gate that connects the first addressing circuit and the memory during a period when the clock output is generated; and a second addressing circuit during a period when the clock output is not present. a second gate that connects the first addressing circuit to the memory; a port that outputs the output of the first addressing circuit to an external display unit as a digit signal; It includes a register for storing data before the clock output is generated when the data is output to the outside, and a mode specifying section, and the clock output is generated and the first addressing circuit and the memory are connected to the first address specifying circuit. During the period when the first addressing circuit is connected through the gate of the first addressing circuit, the operation of the first addressing circuit is stopped by the output from the mode specifying section, and the data stored in the register is output from the port. This is a characteristic feature.

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of a data processing device showing an embodiment of the present invention. A microcomputer 1 composed of a one-chip LSI has a ROM 2 for storing a control program, a program counter 3 for specifying this address, and a ROM 2 for storing a control program. , a stack register 4 that saves the contents of the program counter 3 when a subroutine is called, an instruction decoder 5 that decodes output data from the ROM 2, an ALU 6 that performs arithmetic and logical operations, and a register used for operations. Accumulator (ACC) 7 and ALU
a carry flag 8 that is set if a carry occurs as a result of the operation in step 6; a data pointer 9 that is used to specify the address of the RAM 13 and transfer data between the specified address and the data bus 25; The RAM 13 decodes the output of the data pointer 9 or digit signal counter 10.
RAM address decoder 1 that selects the address of
1 and a control signal from the instruction decoder 5 that decodes the ROM contents, data is read from the RAM 13 to the data bus 25, and data is read from the data bus 25.
It also includes a gate circuit 12 that functions to write data into the RAM 13. The RAM 13 stores data, the digit signal counter 10 generates a digit signal, and the counter specifies the address of the RAM 13, the contents of which are counted up by the clock output from the clock timing circuit 20. Furthermore, the digit signal counter 10 is connected to the added mode register A2.
1. It is also controlled by mode register B22. The inverter 14 is the clock timing circuit 2
By inverting the output of 0, gate 15 and gate 16
For example, when the output of the clock timing circuit 20 is not energized, the gate 16 is closed, the gate 15 is open, and the data pointer 9 reads the address of the RAM 13 via the RAM address decoder 11. Specify. Further, when the output of the clock timing circuit 20 is activated, the gate 15 is closed and the gate 16 is opened, so that the output of the digit signal counter 10 specifies the address of the RAM 13 via the RAM address decoder 11. A digit signal decoder/port 18 decodes the output of the digit signal counter 10 and generates a signal for each digit to drive and scan a display device (not shown).
When the count-up of the digit signal counter 10 is stopped by the control of the digit signal counter 10, all outputs of the digit signal decoder/decoder of the port 18 are deactivated, all digit signal outputs are prohibited, and instead of the register 19 described later. The contents of the file can be output. This control can be performed by a well-known multiplexer circuit, and the switching is performed by mode register A21.
It can be defined according to the state of Further, the output of the clock timing circuit 20 is energized to the segment port 17, the gate 15 is closed, and the contents of the address specified by the digit signal counter 10 when the address of the RAM 13 is specified are written. Register 19 temporarily stores and holds data from data bus 25, has the same number of bits as the output bits of digit signal decoder/port 18, and is multiplexed to each output of the decoder. Mode register A21 and mode register B22 are flip-flops that are set and reset by instructions, respectively, and when mode register A21 is reset,
Digit signal counter 10 is connected to clock timing circuit 2
Specify the address of RAM13 at the timing when the output of 0 is activated, and send it to segment port 17.
Output data of RAM 13 is written. Further, the digit signal decoder/port 18 is connected to the digit signal counter 10.
Decodes the output of and generates a digit signal. Further, when the digit signal counter 10 is sequentially counted up by the output of the clock timing circuit 20, a mode is entered in which the digit signals are sequentially updated and display is executed. On the other hand, when the mode register A21 is set, the digit signal counter 10 does not count up even when the output of the clock timing circuit 20 is input, but is set to a state where the count contents at that time are maintained. Also, all decoder outputs of the digit signal decoder/port 18 are deactivated. Furthermore, by stopping the count-up operation of the digit signal counter 10, its contents are held, and all of its outputs are set to the "1" level (or "0" level), so that the RAM 1 is maintained during this period.
The address to 3 is a fixed address of all "1" (or all "0"). This inhibits the clock supplied to the digit signal counter 10 by the signal from the mode register 2A and closes the gate circuit of its output, thereby setting all the outputs of the gate circuit to "1" (or "1"). This is because it can be fixed at 0''). Next, when mode register B22 is reset, digit signal counter 1
0 causes the display device to sequentially generate all-digit signals by repeatedly counting the maximum number of digits set in advance as the number of display digits. Further, when the mode register B22 is set, the digit signal counter 10 repeats counting only half of the maximum number of digits, and only half of the digit signals are generated. Such control can be achieved by gate control such that all outputs of the digit signal decoder/port 18 are inhibited by a set output of the output mode register B 22 of half of the outputs of the mode register A 21 which serve as the output of the digit signal counter 10. . For example, when the maximum number of digit signals is set to 8 digits, when the mode register B22 is set, only digit signals of 1 to 4 digits are repeatedly output from the digit signal decoder/port 18. Therefore, the remaining (5 to 8
The digit signal for digit) is not generated and the corresponding decoder output of digit signal decoder/port 18 remains de-energized. Clock timing circuit 20 for generating clock and system timing signals
controls the transfer of the count-up signal to the digit signal counter 10, the inverter 14, the gate 15, and the segment port 17, and controls the RAM 1 based on the address specified by the digit signal counter 10.
Control is performed to write the contents of 3 to the segment port. Furthermore, the control circuit 23 performs control such as determining the status of each block and flags, and branching the program. I/O port 24 transfers data between microcomputer 1 and external peripheral devices.

Next, the operation of this embodiment will be explained with reference to the second system timing diagram.

One instruction cycle consists of three timing periods: T ₁ T ₂ T ₃ . For example, the contents of RAM13 addressed by data pointer 9 can be transferred to ACC7.
The instruction to store the contents of data pointer 9 by 1 (hereinafter referred to as increment) is as follows:
In T ₁ timing period, data pointer 9
The contents of the RAM 13 addressed by are read out to the data bus 25 via the gate circuit 12. next
The contents of data bus 25 are transmitted in T ₂ timing cycles.
Write to ACC7. Furthermore, in the _T3 timing period, the contents of the data pointer 9 are read onto the data bus 25, the contents are incremented by the ALU 6, and the contents are written to the data pointer 9 again. That is, T ₁ and T ₂ timings are timings for reading the contents of RAM 13 and writing data to RAM 13, and T ₃ timings are timings for reading the contents of RAM 13 and writing data to RAM 13.
3, such as data processing such as determination of the control circuit 23, setting of the carry flag 8, or incrementing of the data pointer 9.

Therefore, by transferring the clock signal from the clock timing circuit 20 in this _T3 timing period, the gate 15 is closed and the digit signal counter 10 is closed.
Address specification of RAM 13 can be executed from . Also, segment port 17 has
The contents read from RAM 13 are written. Now, reset the mode register A21 and select the RAM in which the digit signal counter 10 specifies the segment data corresponding to the digit signal to be displayed in advance before displaying.
If you set the address value to 13, each instruction
At timing _T3 , the segment port 17 reads the segment data set in the RAM 13 and outputs the segment signal to be displayed in synchronization with the digit signal scanning. Furthermore, the digit signal counter 10 always outputs the count output to the digit signal decoder/port 18, so during the period when this digit signal is being output, the segment port 17 and the digit signal decoder/port 18 drive the external display device. and display it. That is, when the content of the digit signal counter 10 is counted up and the displayed digit is updated, the updated content is used as address designation of the RAM 13, so the segment data corresponding to the updated digit signal is transferred from the RAM 13 to the T. The signal is taken out at _three timings, written to the segment port 17, and output as a segment signal to the display device, and data processing and display processing are performed in a time-sharing manner.

Here, as a means for storing segment data at the address value specified by the digit signal counter 10 in the RAM 13, it is possible to write the segment data to a predetermined address value using a group of commands that operate the RAM 13, or to display the segment data. When the desired data is obtained, the display data is set in the program counter 3, and the segment data is stored in advance at a predetermined address in the ROM 2 whose address is the display data. Read the segment data using
It is also possible to write to the RAM 13 using a so-called table reference instruction.

Next, when the mode register A21 is set, the digit signal counter 10 retains its contents and stops counting, and no digit signal is generated from the digit signal decoder/port 18. Digit signal decoder/port 18 is used as a data transfer port for purposes other than display processing. In addition, the contents of the fixed address of RAM 13 are output to the segment port 17, and during the display prohibition period, the address is all “1” (or all “0”).
is supplied to the RAM 13. Therefore, if you write the data you want to output to the outside in the address hole "1" (or all "0") position of the RAM 13 during the periods T ₁ and T ₂ , the data will be sent to the segment port 17 while display is prohibited. It can be output to the outside via.

Therefore, by setting the mode register A21, the digit signal counter 10 can be stopped in its current state and the display can be temporarily interrupted. At this time, the digit signal decoder/port 18 or the segment port 17 can be used for purposes other than display, such as a key scan signal output port for a keyboard or the like. On the other hand, since the digit signal counter 10 retains the contents immediately before the stop, by subsequently resetting the mode register A21, the display process can be resumed from the state immediately before the interruption. Therefore, even if the display is temporarily interrupted in the middle of display, the digit signal will not be updated during this time, and even if the display process is restarted, a certain digit will not be displayed and the display duty will differ between digits. Continuous display can be performed instead of

FIG. 3 is a timing chart of digit signals and segment signals in an embodiment in which the segment port 17 is used as a general-purpose port.

If the mode register A21 is set at a timing while the fourth digit signal is currently being energized to the display device, the fourth digit signal will be de-energized at the timing, and the segment port 17 will not be activated until the display device is stopped. The segment signal corresponding to the fourth digit signal is output from , but since the contents of the fixed address of RAM 13 are output immediately after the timing, segment port 17 can be used as a general-purpose port by manipulating the contents of the fixed address of RAM 13. be able to. Further, when the mode register A21 is reset at timing, the segment signal for the fourth digit signal is output from the segment port 17 immediately after timing B, and subsequently the fourth digit signal is activated again. As a result, the display of the fourth digit is restarted, and then the display of the fifth digit, etc. is executed. In this case, the period in which the fourth digit signal is activated is the period in which the fourth digit signal is activated.
As shown in the figure, this is the period d, and this + period is exactly the same as the period during which the digit signals other than the fourth digit are activated and the display is not interrupted midway.

As described above, even if the display is interrupted midway, the display after restarting can be executed continuously, and it is also possible to execute other data processing using the display ports 17 and 18 when the display is interrupted. By sharing input/output terminals, a highly versatile data processing device can be provided.

Furthermore, if mode register A21 is reset and mode register B22 is reset, digit signals of the maximum number of digits will be sequentially output from the digit signal decoder/port 18, but if mode register B22 is set, half of the maximum number of digits will be output. Only the signal is output from the digit signal decoder/port 18. At this time, if predetermined transfer data is set in the register 19 that is OR-connected to the decode output of the digit signal decoder/port 18, the bit contents of the register 19 will be output to the outside from the port of the digit signal that is not displayed. be able to. That is, the output bits of the digit signal decoder/port 18 having half the maximum number of digits can be used as a general-purpose port.

Furthermore, even if the mode register A21 is reset and display is being executed, the data pointer 9
The digit signal counter is specified by _T3 timing.
By changing the segment data of the address value of the RAM 13 during the _T1 and _T2 timing periods, display data can be changed while display processing is being executed.

Furthermore, mode register A21 is reset,
When mode register B22 is set, digit signal counter 10 specifies only half of the addresses in RAM 13 where segment data is to be stored, so other address values are used as storage addresses for data used in internal calculations. RAM can be used effectively. Furthermore, in this case, there is an advantage that the display duty value becomes larger than when the maximum number of digits is used, and the brightness increases accordingly.

As described above, it is possible to temporarily interrupt the display using mode register A21 and use the digit signal decoder/port 18 or segment port 17 as a general-purpose port for purposes other than display, and then interrupt the display. Since it is possible to resume from the previous state, ports can be used effectively without any hindrance to display processing, and data processing functions are expanded. In addition, the number of display digits can be changed arbitrarily by using the mode register B22, so ports that are not used for display can be used as other data transfer ports in parallel with display processing, thereby making it possible to use ports that are not used for display as other data transfer ports. It is possible to increase the display brightness as the display brightness increases.

In this way, according to the present invention, by skillfully utilizing the empty timing of RAM, processing other than display can be executed in a time-sharing manner without degrading the display processing function, and the input/output terminal of the display port can be used as a general-purpose input/output terminal. Can be used as an output terminal. Therefore, not only the data processing capability is expanded, but also the processing speed of display processing and other data processing is significantly improved. In addition, it is possible to perform complex display processing without software intervention, and when controlling a display device with a small number of display digits, port usage efficiency can be greatly increased. Even if there is a problem, the segment data can be changed arbitrarily without stopping the execution, and the display pattern can be changed extremely easily.

Furthermore, the mode register A21 and mode register B22 are set and reset by commands, but by writing the contents of the data bus 25 using the control signal of the command decoder 5, the stored data can be set. Good too. Furthermore, by setting and resetting the mode register B22, the number of digit signals to be output can be set to two types of values (full digit and half digit). It is clear that the number of digit signals can be made finely variable, and in this case it is clear that the port usage efficiency is further improved. Also, register 19
is configured with the same number of bits as the output bits of the digit signal decoder/port 18, but the setting of this number of bits may be changed as appropriate. Also, segment data from the RAM 13 is transferred to the segment port 17 using a dedicated data bus 30.
Data bus 25 may also be used for data transfer. Furthermore, it is obvious that the present embodiment can be integrated into a single chip, or a part or any control block may be formed on separate chips and used in combination.

Note that this embodiment has described an example in which two mode registers are used to control a digit signal counter and a port, but when using the entire output of port 18 for display, mode register B22 is not necessarily necessary and can be omitted. Obviously, it may be omitted. Furthermore, the present invention allows display data and normal processing data to be stored in the same memory (RAM 13), and allocates a period during which this memory is not accessed during normal processing as a display processing period. When it is necessary to output data externally in priority to display, it is possible to temporarily suspend display and output data externally, and at that time, the data is allocated for display. This allows data to be output to the outside using a port. Therefore, it has at least a mode register A, and switches between the digit signal counter 10 and the data pointer 9 using a clock timing circuit 20 (when RAM is not accessed (T
3) A circuit that generates an output) can achieve the above-mentioned effects.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIGS. 2 and 3 are operation timing charts thereof, respectively. 1...1 chip microcomputer, 2...
ROM, 3...Program counter, 4...Stack register, 5...Instruction decoder, 6...
ALU, 7...ACC, 8...Carry Flag,
9...Data pointer, 10...Digit signal counter, 11...RAM address decoder A, 12...
...gate circuit, 13...RAM, 14...inverter, 15...gate, 16...gate, 17...
...Segment port, 18...digit signal decoder/
Port, 19...Register, 20...Clock timing circuit, 21...Mode register A, 22
...Mode register B, 23...Control circuit, 24
...I/O port, 25...data bus.

Claims (1)

[Claims] 1. In a data processing device that performs display processing and normal data processing, a memory that stores both display data and data processing data, a first addressing circuit that reads display data from the memory, and a data a second addressing circuit that reads processing data from the memory; a clock timing circuit that generates a clock output during a period when the memory is not used in each instruction machine cycle during normal data processing; and a period during which the clock output is generated. a first gate that connects the first addressing circuit and the memory; a second gate that connects the second addressing circuit and the memory during a period when the clock is not output; and a second gate that connects the second addressing circuit and the memory;
A port that outputs the output of the addressing circuit as a digit signal to an external display unit, and a port that outputs data that is connected to the port and is created by data processing and is to be output to the outside before the clock output is generated. and a mode specifying section, and during a period when the clock output is generated and the first addressing circuit and the memory are connected via the first gate, the clock output from the mode specifying section is A data processing device characterized in that the operation of the first addressing circuit is stopped by the output, and the data stored in the register is output from the port.