JPH0619840A - Data processor - Google Patents

Abstract

PURPOSE:To obtain a data processor where the setting of an operation frequency can dynamically be changed without deteriorating efficiency. CONSTITUTION:This processor is provided with a selector means 14 setting the number of the waiting clocks and the period of access to the other unit by a clock selection signal 103, a connter means 15 inputting the clock 101 of the prescribed frequency without depending on the clock selection signal and counting the clock, and a selector means 16 selecting the output of the counter means 15 by an interval selection signal 109. A bus control unit 17 starts various bus cycles by output from the respective selector means 14 and 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processor having a queuing control mechanism for a bus master unit and other external / internal units or a constant interval access control mechanism.

[0002]

2. Description of the Related Art Conventionally, in a data processor having a clock generator for dividing an external / internal clock of this type, one system clock is commonly used in most units, and when the division ratio is changed. The processing speed of all the units changed at the same time. Therefore, if there is a problem in real time such as wait control between bus master and slave and refresh interval of dynamic memory, either set the condition to satisfy all the frequency division ratios to be used, or It was necessary to change the setting values of the wait controller and refresh controller before or after the change.

[0003]

However, if the set value is set so as to satisfy the conditions at all the frequency division ratios, more refresh cycles than necessary are activated when the frequency is high, that is, when high-speed processing is required, Further, when the frequency is low, there is a problem that efficiency is greatly reduced, for example, unnecessary wait cycles are inserted and the processing speed is extremely reduced. Further, in order to dynamically change the settings, it is generally necessary to change the settings by a program, but these settings generally need to be reversed when increasing or decreasing the division ratio. Therefore, the same routine cannot be used, which causes problems such as making the program complicated, increasing the size, and increasing errors. An object of the present invention is to provide a data processor capable of dynamically changing the setting of the operating frequency without lowering the efficiency.

[0004]

According to the present invention, there is provided selector means for setting the number of clocks for waiting for access to another unit and the cycle thereof by a clock selection signal, and a clock of a constant frequency regardless of the clock selection signal. A counter means for counting this clock and a selector means for selecting the output of the counter means by an interval selection signal, and the bus control unit activates various bus cycles by the output from each selector means. To do.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a first embodiment of the present invention. The present embodiment is an example of a data processor that automatically controls the number of waits and the refresh interval during external access according to the division ratio of the operating clock. In the figure, 11
Is a frequency divider, which divides the input clock 101 and outputs a clock group 102 of 1/2 to 1/2 ⁿ . Reference numeral 12 denotes a clock selector, which selects one of the divided clocks 102 according to an instruction of a clock selection signal 103 and supplies it to each unit as a basic clock 104.

A wait counter 13 generates a wait count signal group 106 from the bus status signal 105 and the clock 104. Reference numeral 14 denotes a wait selector which selects an appropriate one from the wait count signal group 106 according to the set value of the wait counter 13 and the clock selection signal 103 and outputs it as a wait signal 107.

A refresh counter 15 further divides a fixed one of the divided clock groups 102 to generate a refresh request signal group 108 of each cycle. 16 is a refresh interval selector,
The refresh interval selection signal 109 selects one from the refresh request signal group 108 and outputs the refresh request signal 110. A bus control unit 17 activates various bus cycles based on the wait signal 107 and the refresh request signal 110.

In the first embodiment, the wait selector 14 automatically changes the number of waits in each bus cycle by the clock selection signal 103, so that the program can access without being aware of the operating frequency. Further, since the refresh counter 15 is always supplied with the clock of the same cycle regardless of the clock selection signal 103, the refresh cycle can be kept constant regardless of the operating frequency. As a result, the program does not need to be aware of the frequency even when the operating frequency of the processor is dynamically changed, and the performance at each frequency can be kept to the maximum.

FIG. 2 is a block diagram of a second embodiment of the present invention, in which the same parts as those in the first embodiment of FIG. 1 are designated by the same reference numerals. In the second embodiment, the frequency divider 11 and the clock selector 12 are not provided, and the input clock 101 is directly fed to the wait counter 13, the refresh counter 15,
The clock switching information 111 is input to the bus control unit 17, and the wait selector 14 and the refresh interval selector 16 are input.

According to the second embodiment, while the clock input 101 needs to be fixed in the first embodiment,
This is an example in which the use of the clock switching information 111 can be applied even when the input clock 101 itself changes. This example is more effective than the first embodiment in that the change of the input clock 101 of the refresh counter 15 can be changed by the refresh interval selector 16 identifying and canceling the clock switching information 111. Is.

[0011]

As described above, according to the present invention, the operating frequency of the processor can be controlled by automatically converting various setting values by the operating clock setting signal or by using the clock which is not influenced by the operating clock setting signal. Even when changing dynamically, it is not necessary for the program to be aware of the frequency, and it is possible to maintain the maximum performance at each frequency.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of a data processor of the present invention.

FIG. 2 is a block diagram of a second embodiment of the present invention.

[Explanation of symbols]

 11 frequency divider 12 clock selector 13 wait counter 14 wait selector 15 refresh counter 16 refresh interval counter 17 bus control unit

Claims (1)

[Claims] 1. A selector means for setting a waiting clock number and a cycle for access to another unit by a clock selection signal, and a counter means for inputting a clock of a constant frequency regardless of the clock selection signal and counting this clock. And a selector means for selecting the output of the counter means by an interval selection signal, and the bus control unit is configured to activate various bus cycles by the output from each selector means. .