US5414816A - Data transfer apparatus having means for controlling the difference in speed between data input/output ports and memory access - Google Patents

Data transfer apparatus having means for controlling the difference in speed between data input/output ports and memory access Download PDF

Info

Publication number
US5414816A
US5414816A US08/115,754 US11575493A US5414816A US 5414816 A US5414816 A US 5414816A US 11575493 A US11575493 A US 11575493A US 5414816 A US5414816 A US 5414816A
Authority
US
United States
Prior art keywords
memory
channels
memory access
input
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US08/115,754
Inventor
Hajime Oyadomari
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP31842988A external-priority patent/JPH0715669B2/en
Priority claimed from JP63318428A external-priority patent/JP2669020B2/en
Application filed by NEC Corp filed Critical NEC Corp
Priority to US08/115,754 priority Critical patent/US5414816A/en
Application granted granted Critical
Publication of US5414816A publication Critical patent/US5414816A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Definitions

  • the present invention relates to a data transfer apparatus for a data processing system.
  • a conventional data transfer apparatus of this type includes a plurality of memory access flags to perform memory access. Each memory access is assigned to the corresponding channel. As shown in FIG. 2, a memory access time slot of one channel is assigned to a specific machine cycle of one period at the time of memory access. For example, in the memory access, data having a specific data length, e.g., 8-byte data, is exchanged between a memory and an input/output device within a predetermined period, e.g., four machine cycles each assigned to four channels.
  • a memory access buffer is arranged for only one memory access cycle corresponding to, e.g., 8-byte data.
  • an upper limit of memory access performance of one channel is determined. It is generally considered that the memory access speed is high, and is not lower than a transfer speed of an input/output device.
  • an input/output device such as a semiconductor disk
  • generations of main frame and peripheral system apparatus do not coincide with each other. Therefore, an input/output device having a transfer speed higher than the memory access speed has been required.
  • speed matching is performed between the input/output device and the data transfer apparatus through an adapter such as a local memory for buffering one block of a data record of the input/output device.
  • an adapter such as a local memory for buffering one block of a data record of the input/output device.
  • this speed matching causes an increase in hardware, and a delay of an I/O time period occurs by an access time of the local memory. Therefore, such high-performance input/output device cannot be efficiently used.
  • a data transfer apparatus comprising a plurality of channels which are respectively connected to input/output devices and to which channel numbers are respectively assigned.
  • Transfer speed control means are arranged between these channels and a memory, the transfer speed control means including means for monitoring a rate of data transfer from the input/output devices to the memory, and means for controlling and decreasing a difference in speed between data sent from the input/output devices and memory access when the monitor result represents a predetermined difference.
  • FIG. 1 is a block diagram showing an arrangement of a data processing system which includes a data transfer apparatus according to the first embodiment of the present invention
  • FIG. 2 is a timing chart for explaining the operation of a conventional data transfer apparatus
  • FIG. 3 is a block diagram showing a data transfer apparatus according to the second embodiment of the present invention.
  • FIG. 4 is a timing chart for explaining the operation of the data transfer apparatus according to the second embodiment of the present invention.
  • FIG. 5 is a block diagram showing a data transfer apparatus according to the third embodiment of the present invention.
  • a data transfer apparatus 1 is connected to input/output devices 31 to 3n through connecting lines 501 to 50n, respectively.
  • This data transfer apparatus includes channels 111 to 11n to which channel numbers are respectively assigned, memory request flags (MRF) 131 to 13n for controlling memory access to a memory 2 in units of the channels, a plurality of memory access buffers 121 to 12n (4W ⁇ 8B) which correspond to the channels and are used to perform memory access to the memory 2, a memory-side buffer pointer (PTM) 16 for counting the access count between the memory 2 and the buffers 121 to 12n, a channel-side buffer pointer (PTH) 15 for counting the access count between the channels 111 to 11n and the buffers 121 to 12n, an arithmetic circuit (DELT) 17 for calculating a difference between the content of the memory-side buffer pointer 16 and that of the channel-side buffer pointer 15 to output a difference signal representing this difference, and a memory request control circuit 14 for
  • the input/output device 32 When the input/output device 32 receives an input/output instruction to perform data transfer, first, the pointers PTM 16 and PTH 15 are reset, and an output from the DELT 17 is set at "0".
  • the PTH 15 is "+1" when 8-byte data is transferred from the channel 112 to the buffer 122. Since an input operation is performed, an output from the DELT 17 corresponds to PTH - PTM, i.e., goes to "1".
  • the control circuit 14 turns the memory request flag 132 on, and starts memory access to store the 8-byte data in the memory 2. When the end condition of this memory request is returned from the memory 2, the PTM 16 is incremented by one, and an output from the DELT 17 returns to "0" again.
  • the PTH 15 goes to "2".
  • the DELT 17 is sequentially decremented, and various memory access modes can be performed in accordance with a transfer speed of the input/output device.
  • the second embodiment of the present invention is shown in FIG. 3.
  • the second embodiment has the same arrangement as in the first embodiment except for the following.
  • a memory request timing control circuit 24 is used in place of the memory request control circuit 14 in FIG. 4 to change a timing of memory access when a difference signal exceeds a predetermined value
  • memory access slot flip-flops (MAF) 231 to 23n are used in place of the memory request flags 131 to 13n.
  • FIG. 4 is a timing chart for explaining memory access in the second embodiment.
  • FIG. 4 indicates that the memory access for the channels (CH0 to CH3) is time-divisionally output during the 4T cycles, normally, and reply is returned during 4T cycles.
  • the flexibility with respect to a transfer speed can be improved, and a high-efficiency data transfer apparatus can be provided.
  • the memory access buffer count is used, and the multiplexed memory access time slot corresponding to the channel is output. Therefore, a high efficient high-speed data transfer apparatus can be provided.
  • FIG. 5 shows the third embodiment of the present invention.
  • the same reference numerals in FIG. 5 denote the same parts as in FIG. 1.
  • a data transfer apparatus 1 is connected to input/output devices 51 to 5n through connecting lines 31 to 3n, respectively.
  • the data transfer apparatus 1 includes channels 111 to 11n, to which channel numbers are respectively assigned, memory request flags 131 to 13n, set to be "1" during memory access, for controlling the memory access to a memory 2 in units of channels, a memory access decoder 61 for decoding the contents of the memory request flags 131 to 13n, measuring circuits 751 to 75n for measuring transfer speeds of the input/output devices 51 to 5n, and a change circuit 72 for changing the correspondence between the memory request flags 131 to 13n and the channel numbers on the basis of the measurement result of the measuring circuits 751 to 75n.
  • the data transfer apparatus 1 performs a data transfer operation between the input/output devices 51 to 5n and the memory 2.
  • the measuring circuits 751 to 75n respectively consist of 4-bit flip-flops (F/Fs), for holding the access counts between the channels and the input/output devices during one memory access cycle.
  • an input/output instruction is output from a central processing unit (not shown) to the data transfer apparatus 1 of this embodiment, and a specific channel, e.g., the channel 112, starts the data transfer from/to the input/output device 52 using a connection path 32, and the data transfer from/to the memory 2 using the memory access flag 132.
  • a specific channel e.g., the channel 112
  • the change circuit 72 causes the memory request flag corresponding to the channel which does not perform memory access, e.g., the memory request flag 131, to correspond to the channel 112, thus performing the operation of the memory request.
  • the change circuit 72 sequentially changes the correspondence between the memory request flag and the channel, and the memory access of the high-speed input/output device is preferentially processed.
  • the memory request flag 132 is reset.
  • a predetermined value is subtracted in the measuring circuit 752, and the measuring circuit 752 is completely reset when the memory request flag 131 is reset.
  • the high-speed input/output device can perform multiplexed memory access corresponding to a multiple of the predetermined value of the measuring circuit, high-speed memory access can be expected.
  • the data transfer apparatus including a plurality of memory request flags
  • hardware can be decreased, thus providing a highly efficient data transfer apparatus.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Communication Control (AREA)

Abstract

A data transfer apparatus includes a plurality of channels and a transfer speed control circuit. A plurality of channels are connected to input/output devices, respectively. Each channel is assigned a corresponding channel number. The transfer speed control circuit is arranged between the channels and a memory. The transfer speed control circuit includes a monitor for monitoring a rate of data transfer from the input/output devices to the memory, and a controller for controlling and decreasing a difference in speed between data sent from the input/output devices and memory access when the monitor result represents a predetermined difference.

Description

This application is a continuation of application Ser. No. 07/873,694, filed Apr. 21, 1992, now abandoned, which is a continuation of application Ser. No. 07/451,990, filed Dec. 18, 1989, now abandoned.
BACKGROUND OF THE INVENTION
The present invention relates to a data transfer apparatus for a data processing system.
A conventional data transfer apparatus of this type includes a plurality of memory access flags to perform memory access. Each memory access is assigned to the corresponding channel. As shown in FIG. 2, a memory access time slot of one channel is assigned to a specific machine cycle of one period at the time of memory access. For example, in the memory access, data having a specific data length, e.g., 8-byte data, is exchanged between a memory and an input/output device within a predetermined period, e.g., four machine cycles each assigned to four channels. A memory access buffer is arranged for only one memory access cycle corresponding to, e.g., 8-byte data.
In such a data transfer apparatus, an upper limit of memory access performance of one channel is determined. It is generally considered that the memory access speed is high, and is not lower than a transfer speed of an input/output device.
However, an input/output device such as a semiconductor disk, has been developed, and generations of main frame and peripheral system apparatus do not coincide with each other. Therefore, an input/output device having a transfer speed higher than the memory access speed has been required.
In such a case, speed matching is performed between the input/output device and the data transfer apparatus through an adapter such as a local memory for buffering one block of a data record of the input/output device. However, this speed matching causes an increase in hardware, and a delay of an I/O time period occurs by an access time of the local memory. Therefore, such high-performance input/output device cannot be efficiently used.
SUMMARY OF THE INVENTION
It is a principal object of the present invention to perform a data transfer operation more efficiently than can a conventional apparatus.
It is another object of the present invention to perform a data transfer operation at a higher speed than can a conventional apparatus.
In order to achieve the above objects, according to the present invention, there is provided a data transfer apparatus comprising a plurality of channels which are respectively connected to input/output devices and to which channel numbers are respectively assigned. Transfer speed control means are arranged between these channels and a memory, the transfer speed control means including means for monitoring a rate of data transfer from the input/output devices to the memory, and means for controlling and decreasing a difference in speed between data sent from the input/output devices and memory access when the monitor result represents a predetermined difference.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram showing an arrangement of a data processing system which includes a data transfer apparatus according to the first embodiment of the present invention;
FIG. 2 is a timing chart for explaining the operation of a conventional data transfer apparatus;
FIG. 3 is a block diagram showing a data transfer apparatus according to the second embodiment of the present invention;
FIG. 4 is a timing chart for explaining the operation of the data transfer apparatus according to the second embodiment of the present invention; and
FIG. 5 is a block diagram showing a data transfer apparatus according to the third embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Preferred embodiments of the present invention will be described hereinafter with reference to the accompanying drawings.
Referring to FIG. 1, a data transfer apparatus 1 according to the first embodiment of the present invention is connected to input/output devices 31 to 3n through connecting lines 501 to 50n, respectively. This data transfer apparatus includes channels 111 to 11n to which channel numbers are respectively assigned, memory request flags (MRF) 131 to 13n for controlling memory access to a memory 2 in units of the channels, a plurality of memory access buffers 121 to 12n (4W×8B) which correspond to the channels and are used to perform memory access to the memory 2, a memory-side buffer pointer (PTM) 16 for counting the access count between the memory 2 and the buffers 121 to 12n, a channel-side buffer pointer (PTH) 15 for counting the access count between the channels 111 to 11n and the buffers 121 to 12n, an arithmetic circuit (DELT) 17 for calculating a difference between the content of the memory-side buffer pointer 16 and that of the channel-side buffer pointer 15 to output a difference signal representing this difference, and a memory request control circuit 14 for changing the correspondence between each memory request flag and the corresponding channel number when the difference signal exceeds a predetermined value. The data transfer apparatus performs data transfer between the input/output devices 31 to 3n and the memory 2.
When the input/output device 32 receives an input/output instruction to perform data transfer, first, the pointers PTM 16 and PTH 15 are reset, and an output from the DELT 17 is set at "0".
Assume that the PTH 15 is "+1" when 8-byte data is transferred from the channel 112 to the buffer 122. Since an input operation is performed, an output from the DELT 17 corresponds to PTH - PTM, i.e., goes to "1". The control circuit 14 turns the memory request flag 132 on, and starts memory access to store the 8-byte data in the memory 2. When the end condition of this memory request is returned from the memory 2, the PTM 16 is incremented by one, and an output from the DELT 17 returns to "0" again.
When the next 8-byte data is transferred from the input/output device 32 to increment the PTH 15 by one, the PTH 15 goes to "2". When 8-byte data is fetched again from the channel to the buffer 122 during memory access of the memory request flag 132="1", DELT=2 since PTH=3, and PTM=1. The control circuit 14 determines from an output of the DELT=2 that the transfer speed of the input/output device 32 is higher than the memory access speed, and assigns the memory request flag corresponding to the channel number which is not used, e.g., assigns the memory request flag 131 to the channel 112, thus starting memory access.
Thus, when memory access is performed at a lower speed than that of the input/output device, a multiplexed memory request which can be stored in the buffer 122 can be output. More specifically, since the buffer in this embodiment can store four words, the multiplexed memory request can be output up to a difference between the PTH and PTM, i.e., DELT=4.
When the memory request end condition is returned, the DELT 17 is sequentially decremented, and various memory access modes can be performed in accordance with a transfer speed of the input/output device.
Note that although the above description can be applied to an input operation, an output operation can be performed completely in the same manner as in the above description when an output from the DELT 17 is PTM - PTH,.
The second embodiment of the present invention is shown in FIG. 3. The second embodiment has the same arrangement as in the first embodiment except for the following. In the second embodiment, a memory request timing control circuit 24 is used in place of the memory request control circuit 14 in FIG. 4 to change a timing of memory access when a difference signal exceeds a predetermined value, and memory access slot flip-flops (MAF) 231 to 23n are used in place of the memory request flags 131 to 13n.
FIG. 4 is a timing chart for explaining memory access in the second embodiment. FIG. 4 indicates that the memory access for the channels (CH0 to CH3) is time-divisionally output during the 4T cycles, normally, and reply is returned during 4T cycles.
When an input/output device 31 is started in response to an input/output instruction, a PTM 16 and a PTH 15 are reset, and a DELT 17 goes to "0". In an input operation, since DELT=PTH - PTM. Therefore, when 8B data is transferred from a channel 111 to a buffer 121, PTH=1, and DELT=1. At this time, if an MAF 231 is set at "1", memory access can be performed. Therefore, memory access is performed, and the PTM is incremented by one in the next cycle, thus returning to DELT=0. When the transfer speed of the input/output device 31 is high, and the next 8B data are continuously supplied from the channel 111, as shown in FIG. 4, DELT=2 may often be obtained.
At this time, the timing control circuit 24 keeps the MAF 231 on during 2T cycles, to skip the succeeding memory access slot of the CH1 (MAF1). Therefore, the memory access of the channel 111 (CHO) is continuously performed during the 2T cycles, and hence the PTM 16 is continuously incremented by one, thus returning to DELT=0.
Thus, since the access cycles of the channel which requires high-speed memory access are time-divisionally multiplexed, in this embodiment, one channel access cycle can be performed by a maximum of a 4 W buffer capacity, i.e., by DELT=4.
All the above operations are input operations. In an output operation, DELT=PTM - PTH is calculated, and the same operations as in the input operations can be performed until the PTM 16 is updated for reply.
As described above, according to this embodiment, when the channel number correspondence of the memory request flag is changed, and the multiplexed memory request is supplied by the data count in the buffer, the flexibility with respect to a transfer speed can be improved, and a high-efficiency data transfer apparatus can be provided. According to this embodiment, in a data transfer apparatus for performing time-divisional memory access in correspondence with the channels, the memory access buffer count is used, and the multiplexed memory access time slot corresponding to the channel is output. Therefore, a high efficient high-speed data transfer apparatus can be provided.
FIG. 5 shows the third embodiment of the present invention. The same reference numerals in FIG. 5 denote the same parts as in FIG. 1. Referring to FIG. 5, a data transfer apparatus 1 is connected to input/output devices 51 to 5n through connecting lines 31 to 3n, respectively. The data transfer apparatus 1 includes channels 111 to 11n, to which channel numbers are respectively assigned, memory request flags 131 to 13n, set to be "1" during memory access, for controlling the memory access to a memory 2 in units of channels, a memory access decoder 61 for decoding the contents of the memory request flags 131 to 13n, measuring circuits 751 to 75n for measuring transfer speeds of the input/output devices 51 to 5n, and a change circuit 72 for changing the correspondence between the memory request flags 131 to 13n and the channel numbers on the basis of the measurement result of the measuring circuits 751 to 75n. The data transfer apparatus 1 performs a data transfer operation between the input/output devices 51 to 5n and the memory 2. The measuring circuits 751 to 75n respectively consist of 4-bit flip-flops (F/Fs), for holding the access counts between the channels and the input/output devices during one memory access cycle.
Assume that an input/output instruction is output from a central processing unit (not shown) to the data transfer apparatus 1 of this embodiment, and a specific channel, e.g., the channel 112, starts the data transfer from/to the input/output device 52 using a connection path 32, and the data transfer from/to the memory 2 using the memory access flag 132.
When the transfer speed of the input/output device 52 is high, and the access count between the channel and the input/output device which exceeds the predetermined value (when a difference occurs with respect to the predetermined value) is measured by the measuring circuit 752 while the memory request flag 132 is ON, the change circuit 72 causes the memory request flag corresponding to the channel which does not perform memory access, e.g., the memory request flag 131, to correspond to the channel 112, thus performing the operation of the memory request. At this time, if the channel 111 starts memory access, the change circuit 72 sequentially changes the correspondence between the memory request flag and the channel, and the memory access of the high-speed input/output device is preferentially processed.
When the preceding memory access is completed, the memory request flag 132 is reset. At the same time, a predetermined value is subtracted in the measuring circuit 752, and the measuring circuit 752 is completely reset when the memory request flag 131 is reset.
Thus, since the high-speed input/output device can perform multiplexed memory access corresponding to a multiple of the predetermined value of the measuring circuit, high-speed memory access can be expected.
As described above, according to the present invention, in the data transfer apparatus including a plurality of memory request flags, when a plurality of memory request flags are assigned to perform memory access of the high-speed input/output device, hardware can be decreased, thus providing a highly efficient data transfer apparatus.

Claims (3)

What is claimed is:
1. A data transfer apparatus, comprising:
a plurality of channels, each channel connected to a respective input/output device to which channel numbers are respectively assigned;
transfer speed control means interconnected between said channels and a memory, further including monitoring means for monitoring a number of waiting memory accesses from said input/output devices to said memory in each of said channels, the each waiting memory access being generated in response to a difference between a memory access speed and a data entering/exiting speed of said input/output devices; and
adjusting means, when the monitoring result detects a predetermined difference, for controlling said input/output devices based on the predetermined difference;
wherein, said adjusting means includes a plurality of memory access buffers interconnected between said memory and each of said channels, for storing plural transfer data and accessing said memory;
said monitoring means includes a plurality of memory access slot flip-flops arranged in correspondence with the channel numbers, for controlling a memory access time slot of said memory in said respective channels storing the transfer data in said memory access buffers, a memory-side buffer pointer for counting access counts between said memory and each of said memory access buffers in accordance with said channel numbers, and a channel-side buffer pointer for counting access counts between each of said channels and each of said memory access buffers in accordance with said channel numbers; and
said adjusting means further includes an arithmetic circuit for calculating a difference between the content of said memory-side buffer pointer and that of said channel-side buffer pointer to output a difference signal in each of said channels, and a changing means for changing a memory access timing when the difference signal exceeds a predetermined value, said changing means multiplexing the memory access time slots corresponding to one of said channels of which the difference signal represents the predetermined value.
2. A data transfer apparatus, comprising:
a plurality of channels each connected to a respective input/output device to which channel numbers are respectively assigned;
transfer speed control means interconnected between said channels and a memory, further including a monitoring means for monitoring a number of waiting memory accesses from said input/output devices to said memory in each of said channels, each waiting memory access being generated in response to a difference between a memory access speed and a data entering/exiting speed of said input/output devices; and
adjusting means, when the monitoring result detects a predetermined difference, for controlling said input/output devices based on the predetermined difference;
wherein, said monitoring means include a plurality of memory access buffers interconnected between said memory and each of said channels for storing plural transfer data and accessing said memory, and measuring means for measuring the transfer speed of each of said input/output devices;
said adjusting means including a changing means for changing a correspondence between memory request flags and the channel numbers when the measurement result of said measuring means exceeds a predetermined value, said memory responsive to said memory request flags of a corresponding channel for accessing said transfer data in a corresponding memory access buffer in a time division multiplex fashion said changing means achieving high-speed memory access by assigning at least two of said memory request flags to a given channel when said measuring means measures a transfer speed for greater than a predetermined value in said given channel.
3. A data transfer apparatus, comprising:
a plurality of channels, each said channel connected to a respective input/output device to which channel numbers are respectively assigned;
transfer speed control means interconnected between said channels and a memory, further including monitoring means for monitoring a number of waiting memory accesses from said input/output devices to said memory in each of said channels, the waiting memory accesses being generated in response to a difference between a memory access speed and a data entering/exiting speed of said input/output devices; and
adjusting means, when the monitoring result detects a predetermined difference, for controlling said input/output devices based on the predetermined difference;
wherein; said adjusting means includes a plurality of memory access buffers, which buffers are interconnected between said memory and each of said channels, for storing plural transfer data to access said memory;
said monitoring means, including a plurality of memory request flags assigned in correspondence with the channel numbers, for requesting memory access to said memory in each of said channels by storing the transfer data in said memory access buffers, a memory-side buffer pointer for counting access counts between said memory and each of said memory access buffers in accordance with said channel numbers, and a channel-side buffer pointer for counting access counts between each of said channels and each of said memory access buffers in accordance with said channel numbers;
said adjusting means further including an arithmetic circuit for calculating a difference between the content of said memory-side buffer pointer and that of said channel-side buffer pointer in each of said channels, to output a difference signal; and
changing means for changing a corresponding relationship between said memory request flags and the channel numbers when the difference signal exceeds a predetermined value, said changing means assigning at least one of memory request flags assigned to non-used channel numbers to a used channel number with the predetermined value.
US08/115,754 1988-12-19 1993-09-03 Data transfer apparatus having means for controlling the difference in speed between data input/output ports and memory access Expired - Lifetime US5414816A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US08/115,754 US5414816A (en) 1988-12-19 1993-09-03 Data transfer apparatus having means for controlling the difference in speed between data input/output ports and memory access

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
JP63-318429 1988-12-19
JP31842988A JPH0715669B2 (en) 1988-12-19 1988-12-19 Data transfer device
JP63-318428 1988-12-19
JP63318428A JP2669020B2 (en) 1988-12-19 1988-12-19 Data transfer device
US45199089A 1989-12-18 1989-12-18
US87369492A 1992-04-21 1992-04-21
US08/115,754 US5414816A (en) 1988-12-19 1993-09-03 Data transfer apparatus having means for controlling the difference in speed between data input/output ports and memory access

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US87369492A Continuation 1988-12-19 1992-04-21

Publications (1)

Publication Number Publication Date
US5414816A true US5414816A (en) 1995-05-09

Family

ID=26569363

Family Applications (1)

Application Number Title Priority Date Filing Date
US08/115,754 Expired - Lifetime US5414816A (en) 1988-12-19 1993-09-03 Data transfer apparatus having means for controlling the difference in speed between data input/output ports and memory access

Country Status (3)

Country Link
US (1) US5414816A (en)
EP (1) EP0374764B1 (en)
DE (1) DE68929288T2 (en)

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5570381A (en) * 1995-04-28 1996-10-29 Mosaid Technologies Incorporated Synchronous DRAM tester
US5649231A (en) * 1994-01-25 1997-07-15 Fujitsu Limited Storage control method and apparatus having a buffer storage for transferring variable amounts of data to a main storage based on current system load
US5659799A (en) * 1995-10-11 1997-08-19 Creative Technology, Ltd. System for controlling disk drive by varying disk rotation speed when buffered data is above high or below low threshold for predetermined damping period
US5701514A (en) * 1994-04-01 1997-12-23 International Business Machines Corporation System providing user definable selection of different data transmission modes of drivers of an I/O controller transmitting to peripherals with different data transmission rate
US5724609A (en) * 1994-01-25 1998-03-03 Fujitsu Limited Apparatus for transfer-controlling data by direct memory access
US5819053A (en) * 1996-06-05 1998-10-06 Compaq Computer Corporation Computer system bus performance monitoring
US5878280A (en) * 1993-09-23 1999-03-02 Philips Electronics North America Corp. Data buffering system for plural data memory arrays
US5991835A (en) * 1994-11-22 1999-11-23 Teac Corporation Peripheral data storage device in which time interval used for data transfer from relatively fast buffer memory to relatively slower main memory is selected in view of average of time intervals during which data blocks were recently received from host
US6038621A (en) * 1996-11-04 2000-03-14 Hewlett-Packard Company Dynamic peripheral control of I/O buffers in peripherals with modular I/O
US20020062415A1 (en) * 2000-09-29 2002-05-23 Zarlink Semiconductor N.V. Inc. Slotted memory access method
US6408348B1 (en) 1999-08-20 2002-06-18 International Business Machines Corporation System, method, and program for managing I/O requests to a storage device
US6407983B1 (en) * 1998-02-20 2002-06-18 Adc Telecommunications, Inc. Circuit and method for shaping traffic in a virtual connection network
WO2014105352A1 (en) * 2012-12-31 2014-07-03 Sandisk Technologies Inc. Storage device and method for reallocating storage device resources based on an estimated fill level of a host buffer
US20140195701A1 (en) * 2013-01-10 2014-07-10 Skymedi Corporation Time-sharing buffer access system
US10248451B2 (en) * 2015-01-23 2019-04-02 Red Hat Israel, Ltd. Using hypervisor trapping for protection against interrupts in virtual machine functions
US11609870B2 (en) * 2018-12-04 2023-03-21 Rambus lnc. Off-module data buffer

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9569352B2 (en) 2013-03-14 2017-02-14 Sandisk Technologies Llc Storage module and method for regulating garbage collection operations based on write activity of a host
US9471254B2 (en) 2014-04-16 2016-10-18 Sandisk Technologies Llc Storage module and method for adaptive burst mode
US9990158B2 (en) 2016-06-22 2018-06-05 Sandisk Technologies Llc Storage system and method for burst mode management using transfer RAM

Citations (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3516090A (en) * 1965-05-21 1970-06-02 Gen Electric Current limiting circuit breaker with independent acting high speed opening means
US3639909A (en) * 1970-01-26 1972-02-01 Burroughs Corp Multichannel input/output control with automatic channel selection
US3883656A (en) * 1971-11-11 1975-05-13 Ciba Geigy Corp Pharmaceutical preparations for the treatment of hypertonia
US4130864A (en) * 1976-10-29 1978-12-19 Westinghouse Electric Corp. Priority selection circuit for multiported central functional unit with automatic priority reduction on excessive port request
US4145755A (en) * 1975-10-15 1979-03-20 Tokyo Shibaura Electric Co., Ltd. Information transferring apparatus
US4171536A (en) * 1976-05-03 1979-10-16 International Business Machines Corporation Microprocessor system
US4258418A (en) * 1978-12-28 1981-03-24 International Business Machines Corporation Variable capacity data buffer system
US4400771A (en) * 1975-12-04 1983-08-23 Tokyo Shibaura Electric Co., Ltd. Multi-processor system with programmable memory-access priority control
JPS58223861A (en) * 1982-06-23 1983-12-26 Nippon Telegr & Teleph Corp <Ntt> Data double recording system of input and output controller
US4423482A (en) * 1981-06-01 1983-12-27 Sperry Corporation FIFO Register with independent clocking means
US4571671A (en) * 1983-05-13 1986-02-18 International Business Machines Corporation Data processor having multiple-buffer adapter between a system channel and an input/output bus
US4591973A (en) * 1983-06-06 1986-05-27 Sperry Corporation Input/output system and method for digital computers
US4642797A (en) * 1983-11-10 1987-02-10 Monolithic Memories, Inc. High speed first-in-first-out memory
US4644463A (en) * 1982-12-07 1987-02-17 Burroughs Corporation System for regulating data transfer operations
JPS62297963A (en) * 1986-06-18 1987-12-25 Fujitsu Ltd Allocating circuit for time slot
US4788638A (en) * 1985-12-13 1988-11-29 Hitachi, Limited Data transfer apparatus between input/output devices and main storage with channel devices being of a concentrated type and stand-alone type
US4805094A (en) * 1986-08-27 1989-02-14 American Telephone & Telegraph Company Multi-channel memory access circuit
US4807121A (en) * 1984-06-21 1989-02-21 Cray Research, Inc. Peripheral interface system
US4821170A (en) * 1987-04-17 1989-04-11 Tandem Computers Incorporated Input/output system for multiprocessors
US4831523A (en) * 1986-10-31 1989-05-16 Bull Hn Information Systems Inc. Multiple DMA controller chip sequencer
US4839791A (en) * 1986-03-08 1989-06-13 Nec Corporation Input/output buffer system
US4841475A (en) * 1985-10-01 1989-06-20 Hitachi, Ltd. Data transfer system and method for channels with serial transfer line
US4860193A (en) * 1986-05-22 1989-08-22 International Business Machines Corporation System for efficiently transferring data between a high speed channel and a low speed I/O device
US4991084A (en) * 1988-02-05 1991-02-05 International Business Machines Corporation N×M round robin order arbitrating switching matrix system
US5163134A (en) * 1988-02-19 1992-11-10 Hitachi, Ltd. Method and apparatus for controlling data writing in magnetic recording subsystem
US5164939A (en) * 1988-03-17 1992-11-17 Kabushiki Kaisha Toshiba Packet switching device

Patent Citations (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3516090A (en) * 1965-05-21 1970-06-02 Gen Electric Current limiting circuit breaker with independent acting high speed opening means
US3639909A (en) * 1970-01-26 1972-02-01 Burroughs Corp Multichannel input/output control with automatic channel selection
US3883656A (en) * 1971-11-11 1975-05-13 Ciba Geigy Corp Pharmaceutical preparations for the treatment of hypertonia
US4145755A (en) * 1975-10-15 1979-03-20 Tokyo Shibaura Electric Co., Ltd. Information transferring apparatus
US4400771A (en) * 1975-12-04 1983-08-23 Tokyo Shibaura Electric Co., Ltd. Multi-processor system with programmable memory-access priority control
US4171536A (en) * 1976-05-03 1979-10-16 International Business Machines Corporation Microprocessor system
US4130864A (en) * 1976-10-29 1978-12-19 Westinghouse Electric Corp. Priority selection circuit for multiported central functional unit with automatic priority reduction on excessive port request
US4258418A (en) * 1978-12-28 1981-03-24 International Business Machines Corporation Variable capacity data buffer system
US4423482A (en) * 1981-06-01 1983-12-27 Sperry Corporation FIFO Register with independent clocking means
JPS58223861A (en) * 1982-06-23 1983-12-26 Nippon Telegr & Teleph Corp <Ntt> Data double recording system of input and output controller
US4644463A (en) * 1982-12-07 1987-02-17 Burroughs Corporation System for regulating data transfer operations
US4571671A (en) * 1983-05-13 1986-02-18 International Business Machines Corporation Data processor having multiple-buffer adapter between a system channel and an input/output bus
US4591973A (en) * 1983-06-06 1986-05-27 Sperry Corporation Input/output system and method for digital computers
US4642797A (en) * 1983-11-10 1987-02-10 Monolithic Memories, Inc. High speed first-in-first-out memory
US4807121A (en) * 1984-06-21 1989-02-21 Cray Research, Inc. Peripheral interface system
US4841475A (en) * 1985-10-01 1989-06-20 Hitachi, Ltd. Data transfer system and method for channels with serial transfer line
US4788638A (en) * 1985-12-13 1988-11-29 Hitachi, Limited Data transfer apparatus between input/output devices and main storage with channel devices being of a concentrated type and stand-alone type
US4839791A (en) * 1986-03-08 1989-06-13 Nec Corporation Input/output buffer system
US4860193A (en) * 1986-05-22 1989-08-22 International Business Machines Corporation System for efficiently transferring data between a high speed channel and a low speed I/O device
JPS62297963A (en) * 1986-06-18 1987-12-25 Fujitsu Ltd Allocating circuit for time slot
US4805094A (en) * 1986-08-27 1989-02-14 American Telephone & Telegraph Company Multi-channel memory access circuit
US4831523A (en) * 1986-10-31 1989-05-16 Bull Hn Information Systems Inc. Multiple DMA controller chip sequencer
US4821170A (en) * 1987-04-17 1989-04-11 Tandem Computers Incorporated Input/output system for multiprocessors
US4991084A (en) * 1988-02-05 1991-02-05 International Business Machines Corporation N×M round robin order arbitrating switching matrix system
US5163134A (en) * 1988-02-19 1992-11-10 Hitachi, Ltd. Method and apparatus for controlling data writing in magnetic recording subsystem
US5164939A (en) * 1988-03-17 1992-11-17 Kabushiki Kaisha Toshiba Packet switching device

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
Patent Abstracts of Japan, vol. 12, No. 192 (P 712) (3039) 4 Jun. 1988 & JP,A,62 297 963 (Fujitsu) 25 Dec. 1987 (abstract). *
Patent Abstracts of Japan, vol. 12, No. 192 (P-712) (3039) 4 Jun. 1988 & JP-A-69 297 963 (Fujitsu) 25 Dec. 1987 (abstract).
Patent Abstracts of Japan, vol. 8, No. 82 (P 266)(1519) 14 Apr. 1984 & JP A 58 223861 (Nippon Denshin) 26 Dec. 1983 (abstract). *
Patent Abstracts of Japan, vol. 8, No. 82 (P-266)(1519) 14 Apr. 1984 & JP-A-58223 861 (Nippon Denshin) 26 Dec. 1983 (abstract).

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5878280A (en) * 1993-09-23 1999-03-02 Philips Electronics North America Corp. Data buffering system for plural data memory arrays
US5649231A (en) * 1994-01-25 1997-07-15 Fujitsu Limited Storage control method and apparatus having a buffer storage for transferring variable amounts of data to a main storage based on current system load
US5724609A (en) * 1994-01-25 1998-03-03 Fujitsu Limited Apparatus for transfer-controlling data by direct memory access
US5701514A (en) * 1994-04-01 1997-12-23 International Business Machines Corporation System providing user definable selection of different data transmission modes of drivers of an I/O controller transmitting to peripherals with different data transmission rate
US5991835A (en) * 1994-11-22 1999-11-23 Teac Corporation Peripheral data storage device in which time interval used for data transfer from relatively fast buffer memory to relatively slower main memory is selected in view of average of time intervals during which data blocks were recently received from host
US5570381A (en) * 1995-04-28 1996-10-29 Mosaid Technologies Incorporated Synchronous DRAM tester
US5659799A (en) * 1995-10-11 1997-08-19 Creative Technology, Ltd. System for controlling disk drive by varying disk rotation speed when buffered data is above high or below low threshold for predetermined damping period
US5819053A (en) * 1996-06-05 1998-10-06 Compaq Computer Corporation Computer system bus performance monitoring
US6038621A (en) * 1996-11-04 2000-03-14 Hewlett-Packard Company Dynamic peripheral control of I/O buffers in peripherals with modular I/O
US6407983B1 (en) * 1998-02-20 2002-06-18 Adc Telecommunications, Inc. Circuit and method for shaping traffic in a virtual connection network
US6980565B2 (en) 1998-02-20 2005-12-27 Adc Telecommunications, Inc. Circuit and method for shaping traffic in a virtual connection network
US6408348B1 (en) 1999-08-20 2002-06-18 International Business Machines Corporation System, method, and program for managing I/O requests to a storage device
US20020062415A1 (en) * 2000-09-29 2002-05-23 Zarlink Semiconductor N.V. Inc. Slotted memory access method
WO2014105352A1 (en) * 2012-12-31 2014-07-03 Sandisk Technologies Inc. Storage device and method for reallocating storage device resources based on an estimated fill level of a host buffer
CN104903841A (en) * 2012-12-31 2015-09-09 桑迪士克科技股份有限公司 Storage device and method for reallocating storage device resources based on an estimated fill level of a host buffer
US9703527B2 (en) 2012-12-31 2017-07-11 Sandisk Technologies Llc Storage device and method for reallocating storage device resources based on an estimated fill level of a host buffer
CN104903841B (en) * 2012-12-31 2018-01-05 桑迪士克科技有限责任公司 Estimation filling rank for Intrusion Detection based on host buffer redistributes the storage device and method of storage device resource
US20140195701A1 (en) * 2013-01-10 2014-07-10 Skymedi Corporation Time-sharing buffer access system
US8938561B2 (en) * 2013-01-10 2015-01-20 Skymedi Corporation Time-sharing buffer access system
US10248451B2 (en) * 2015-01-23 2019-04-02 Red Hat Israel, Ltd. Using hypervisor trapping for protection against interrupts in virtual machine functions
US11609870B2 (en) * 2018-12-04 2023-03-21 Rambus lnc. Off-module data buffer

Also Published As

Publication number Publication date
DE68929288D1 (en) 2001-05-10
EP0374764A2 (en) 1990-06-27
EP0374764A3 (en) 1992-11-19
EP0374764B1 (en) 2001-04-04
DE68929288T2 (en) 2001-11-15

Similar Documents

Publication Publication Date Title
US5414816A (en) Data transfer apparatus having means for controlling the difference in speed between data input/output ports and memory access
US4598363A (en) Adaptive delayed polling of sensors
US4654632A (en) Analog-to-digital converter
US5696940A (en) Apparatus and method for sharing first-in first-out memory space between two streams of data
US4481572A (en) Multiconfigural computers utilizing a time-shared bus
US4437157A (en) Dynamic subchannel allocation
US4554628A (en) System in which multiple devices have a circuit that bids with a fixed priority, stores all losing bids if its bid wins, and doesn&#39;t bid again until all stored bids win
US4658349A (en) Direct memory access control circuit and data processing system using said circuit
JP2577865B2 (en) Vector processing apparatus and control method thereof
US4742446A (en) Computer system using cache buffer storage unit and independent storage buffer device for store through operation
US3848233A (en) Method and apparatus for interfacing with a central processing unit
US5594878A (en) Bus interface structure and system for controlling the bus interface structure
GB2085624A (en) A coupling equipment for the control of access of data processors to a data line
US4918597A (en) Adaptive interface for transferring segmented message between device and microcomputer on line division multiplexed bus
US5944788A (en) Message transfer system and control method for multiple sending and receiving modules in a network supporting hardware and software emulated modules
US7380027B2 (en) DMA controller and DMA transfer method
US5999969A (en) Interrupt handling system for message transfers in network having mixed hardware and software emulated modules
US5745731A (en) Dual channel FIFO circuit with a single ported SRAM
US5983266A (en) Control method for message communication in network supporting software emulated modules and hardware implemented modules
EP0118670A2 (en) Priority system for channel subsystem
JP2669020B2 (en) Data transfer device
EP0378422B1 (en) Look ahead bus transfer request
US5842003A (en) Auxiliary message arbitrator for digital message transfer system in network of hardware modules
JPS6333185B2 (en)
JPH08194602A (en) Buffer length varying type access controller

Legal Events

Date Code Title Description
STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12