JPH03152657A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To equalize the access time by providing P bits to each memory request to add the time required for transmission of the memory request and the waiting time to the P bits and then outputting the final P bits to a memory in order of larger bit values. CONSTITUTION:The processors 1-4 are provided with the registers 11, 21, 31 and 41 to which the priority information (P bits) are previously and freely set. When a system is started, the initial value is set by an OS via an initial value table of a memory. At a 1st selection part 100, a memory request buffer A 101 inputs a memory request and a memory request buffer B 102 adds the time required for transfer of data to the buffer B 102 from a memory request buffer B 202 to a memory request 220. The memory requests which are inputted to the B 102 from the A 101 are outputted in order of earlier arrivals to the part 100. When these requests are outputted at one time, a P-bit comparator 104 compares the P bits with each other. Then the preference is given to the larger P bit. The 2nd and 3rd selection parts 200 and 300 also have same operations as the part 100.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a multiprocessor system for an information processing device, and more particularly to a memory request output control method in a multiprocessor system.

Conventional technology Conventionally, in this type of memory request output control method, memory requests do not have priority information, and the priority order of memory request output in each selection section is determined in principle on a first-come, first-served basis. In this method, it is determined in advance that memory requests for processor outputs that are close to memory are given priority.

The drawbacks of the conventional memory request output control method described above will be explained with reference to FIGS. 2, 3, and 4. FIG. 2 is a block diagram showing a multiprocessor system using a conventional memory request output control method having one memory and four processors 1 to 4. Each selection unit 10, 20.30 includes memory request buffers A and B that can hold two systems of memory requests, respectively, and a memory request issuing circuit 11 that outputs memory requests.
゜21.31. In this memory request issuing circuit, memory requests are output to the selector on a first-come, first-served basis, and if they arrive at the same time, priority is given to the processor closest to the memory 5.

3 and 4 are time charts showing operations in the multiprocessor system shown in FIG. 2, assuming that each processor creates and outputs memory requests as continuously as possible.

In FIG. 3, each number within a rectangle indicates a memory request number; for example, 3.2 means the second memory request number output from the third processor. Further, diagonal lines indicate a state in which it is impossible to output a memory request.

Figure 4 shows the example of the time chart shown in Figure 3.
The time required for each memory request to arrive at the memory 5 after it is generated by the processor is shown, and the number in parentheses represents the time. Note that memory request numbers 1.1-1.6, 2.1-2.3, and 3.1 are omitted.

As is clear from Figure 3.4, the time required for a memory request from the processor output to be input to the memory is longer as the processor is located farther from the memory, and the memory access time for each processor is longer. Processors have the disadvantage of being uneven. Another drawback is that the priority settings are fixed, making it difficult to change the system such as increasing the memory access priority for a specific processor.

OBJECTS OF THE INVENTION An object of the present invention is to provide a multiprocessor system in which the memory access times of each processor can be made substantially equal.

Another object of the present invention is to provide a multiprocessor system in which the priority of memory access for a particular processor can be increased and the system can be changed.

Structure of the Invention A multiprocessor system according to the present invention includes first to nth processors that each generate a memory request by adding predetermined priority information, and memory requests of the nth and n-1th processors in accordance with the priority order. An n-1 selection unit that alternatively outputs the memory request of the k-th (k is any natural number satisfying 1≦k<n-1) processor and a selection output of the +11 selection. a common memory that receives the selection output of the first selection section as a memory request; and priority information setting means that can freely change the settings of each of the priority information;
Each of the ~n-1st selection units includes a memory request issuing unit that selectively outputs these memory requests according to the priority information of the input two systems of memory requests, and a memory request issuing unit that outputs memory requests that are suppressed from being output. and means for adding a preset value to the priority information each time the output is suppressed to generate a new memory request, and the first selection unit selects a memory request output from the +11 selection. When this is the case, the present invention is characterized by comprising means for adding a value corresponding to the transfer time from the +11 selection to the priority information at the time of inputting the priority information to the selection unit.

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention. For the sake of explanation, the number of processors is assumed to be four. Each of these processors 1 to 4 is provided with registers 11, 21, 31, and 41 in which priority information (referred to as P bit) can be set in advance. The initial value of the equal register is set by O8. In addition, in response to a command input from the console 7, the service processor 6 rewrites the initial value table on the memory, and during system operation, generates an interrupt instruction requesting each processor 1 to 4 to update the value of the register. The interrupt updates the register values of each processor according to the values in the initial value table in memory. During system operation, each processor adds the value of each register 11, 21, 31, 41 to the P bit when generating a memory request.

As a means for holding memory requests whose output from the memory request issuing circuit has been suppressed in the first to third selection units, a memory request buffer A and a memory buffer B are provided, each of which can hold memory requests input in two ways.

First, in the first selection unit 100, the memory request buffer A iot receives the memory request 10 from the first processor, and the memory request buffer B 102 inputs the memory request 10 from the first processor.
The memory request 220, which is the selection output of 00, is input.

However, at this time, regarding the memory request 220, it is assumed that a value corresponding to the time required for data transfer from the memory request buffer B2O2 to the memory request buffer B102 is added to the P bit by the P bit addition circuit AlO3.

The memory request issuing circuit 103 outputs one of the memory requests inputted from the memory request buffer Al01 and the memory request buffer B 102 to the memory 5 if the memory 5 is capable of accepting the memory request. The output priority of the memory requests at this time is on a first-come, first-served basis to the first selection unit 100, and when they are simultaneous, the values of each P bit are compared by the priority comparison circuit 104, and the one with the larger P bit value is prioritized. do. At this time, it is predetermined in advance that if the values are equal, priority will be given to the memory request output from the memory request buffer A 101.

In the priority addition circuit 810B, for the memory request output from the memory request buffer A 101 or the memory request buffer 8102, the value of one P bit is not larger than the value of the other P bit, or the memory 5 accepts the memory request. For a memory request whose output was suppressed from the memory request issuing circuit 103 due to an impossible state, a value corresponding to the time during which the output was suppressed is added to the P bit, and the memory request is processed. Buffer A 1
01 or the memory request buffer B 102 again.

Second selection section 200. The third selection unit 300 is the first selection unit 10
Operates in the same way as 0. However, the second selection section 200
The memory request 20 of the processor 2 and the memory request 330 which is the selection output of the third selection section 300 are input, and the memory request is outputted to the first selection section 100. Third selection part 3
00 is the memory request 30 from the third processor 3 and the fourth
The memory request 40 from the processor 4 is input, and the memory request is output to the second selection section 200. Also, the third
It is assumed that the selection unit 300 does not have the P-bit addition circuit A, and does not add to the P-bit when the memory request 40 is input.

In the multiprocessor system described above, the time charts in FIGS. 5 and 6 show the operation on the assumption that each processor creates and outputs memory requests as continuously as possible. At this time, the priority addition circuit A receives +2. It is assumed that priority addition circuit B performs addition of +1.

In the example of FIGS. 5 and 6, registers 1.
i, 21. .

This is the case where the initial values of the P bits in 31.41 are all "0".

In FIG. 5, each number within a rectangle indicates a memory request number as in FIG. 3, and diagonal lines indicate a state in which the memory request cannot be output. Further, the numbers in parentheses represent the values of the P bits, and the larger the value, the higher the priority, and the higher the priority, the higher the priority, the higher the priority, the higher the priority will be selectively output.

FIG. 6 shows the time required from the processor output of each memory request to the arrival at the memory in the example of the time chart shown in FIG. 5, and is shown in parentheses. Note that memory request numbers 1.1 to 1.3, 2.1 to 2.3, 3.
1 to 3.2 and 4.1 to 4.2 are omitted.

As is clear from FIGS. 5 and 6, the time it takes for each processor output memory request to reach the memory is approximately averaged. Looking at FIG. 5, the closer the processor is to the memory, the longer the memory request output cannot be output. If the situation is impossible, it is possible to take measures such as adding a value corresponding to the time during which the output was suppressed to the P bit.

Figure 7.8 shows that in order to give the highest priority to the first processor 1, "5° is given in advance as the P bit initial value to the register 11, and the registers 21 and 3 of the other processors are
1.41 shows an operation time chart when "0" is given. As is clear from FIG. 7.8, memory access by the first processor 1 is given top priority.

Effects of the Invention As described above, according to the present invention, each memory request has a P bit, and the time required for the memory request to be transmitted and the time the memory request is waited for are added to the P bit, Based on this final size comparison of the P bits, priority is given to outputting the larger P bits to the memory, making it possible to achieve approximately average access time for all memory requests from each processor. effective.

Furthermore, by making the initial value of the P bit value freely changeable, the priority can be changed as desired, which has the effect of improving the flexibility of the system.

[Brief explanation of the drawing]

Figure 1 is a system block diagram of an embodiment of the present invention, Figure 2 is a block diagram of a conventional multiprocessor system, and Figure 3 is a block diagram of a conventional multiprocessor system.
4 are time charts showing the operation of the conventional system shown in FIG. 2, and FIGS. 5 to 8 are time charts showing the operation of the embodiment of the present invention. Explanation of symbols of main parts 1 to 4...Processor 5...Memory

Claims (1)

[Claims] (1) The first to nth processors each generate a memory request by adding predetermined priority information;
and an (n-1)th selection unit that selectively outputs the memory request of the (n-1)th processor according to the priority order;
(all natural numbers satisfying k<n-1) A k-th selection unit that selectively outputs the memory request of the processor and the selection output of the k+1 selection unit, and a common unit that accepts the selection output of the first selection unit as a memory request. It includes a memory and a priority information setting means that can freely change the setting of each of the priority information, and each of the first to n-1 selection units selects the priority information according to the input priority information of the two systems of memory requests. memory request issuing means for alternatively outputting equal memory requests; and means for adding a preset value for each suppressed memory request to the priority information to generate a new memory request. When the memory request is the memory request output from the k+1 selection section, the k-th selection section selects the k-th selection section upon input to the k-th selection section.
A multiprocessor system comprising means for adding a value corresponding to a transfer time from a +1 selection section to the priority information.