JPH07219671A - Processor chip for parallel computer - Google Patents

Abstract

PURPOSE:To place the processor chip for parallel computers in operation with a clock which has cycles specific times as short as an inputted clock. CONSTITUTION:Each of processor chips 103 constituting a parallel computer system is provided with a frequency divider 201 which divides the frequency of the system clock 102 and a frequency division number storage ROM 202 which stores its frequency division number. When the processor chip 103 is actuated, the frequency division number stored in the frequency division number storage ROM 202 is transferred to the frequency divider 201, which divides the frequency of the system clock according to the frequency division number, so that each respective processor chip 10 is placed in operation at a different period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor chip mounted in a parallel computer system, and more particularly to a processor chip for a parallel computer which can be operated with a clock having a cycle of a predetermined multiple of an input clock.

[0002]

2. Description of the Related Art Due to the limit of speedup of a single processor and the demand for high-speed processing of a large amount of data, for example, SIMD (sing
le instruction-stream multiple data-stream; a method in which each processor executes the same instruction for different data), MIMD (multiple instruction-stream multipl)
Computers of various parallel processing methods such as e data-stream; a method in which each processor independently executes individual instructions) have been developed and put into practical use.

By the way, the clock of the above-mentioned parallel computer is a basic signal for system operation. Generally, a clock signal (system clock) generated from a clock generator external to each processor chip is supplied to each processor chip. It is realized by. The cycle of this clock generator is determined in consideration of the operable clock cycle of the processor chip. More specifically, it is determined by register transfer, memory read / write time, and the like.

[0004]

However, there are variations in the operable clock cycle of the processor chip described above. Therefore, it is necessary to match the system clock cycle of the parallel computer with the longest operable clock cycle of the processor chip to be used. As a result,
There is a problem that the system clock of the parallel computer must be slowed down, the available processor chips are limited, and the yield is deteriorated.

An object of the present invention is to realize a processor chip that operates with a clock having a cycle that is a predetermined multiple of an input clock, and use the processor chip to mix processor chips with different operable clock cycles (grades). The parallel computer can be configured.

[0006]

To achieve the above object, a parallel computer processor chip of the present invention comprises at least means for dividing an input clock and means for storing a division number. When the processor chip is activated, the stored frequency division number is set in the frequency division means,
The input clock is frequency-divided according to the set frequency division number, and the processor chip is operated with a clock having a cycle of a predetermined multiple of the input clock.

[0007]

The processor chip is provided with a frequency divider for dividing the system clock and a frequency division storage ROM for storing the frequency division number. The frequency division storage ROM is provided when the processor chip is activated.
The frequency division number stored in is transferred to the frequency divider. The processor chip divides the system clock according to the division number and operates in different cycles. When a parallel computer is configured using such processor chips, each processor chip operates by dividing the system clock by the frequency division number set for each processor chip, so that processor chips with different operable clock cycles Mixed parallel computers can be configured.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be specifically described below with reference to the drawings. FIG. 1 shows the configuration of a processor chip of the present invention. The processor chip 103 uses the system clock 1
Frequency divider 201 that divides 02 and RO that stores the number of divisions
It is equipped with M202. In the present invention, the frequency division number storage ROM 202 stores in advance a frequency division number indicating how many times the cycle of the system clock 102 is to be used.

That is, for example, the operable clock period of the processor chip is measured, and from the measurement result, the frequency division number indicating how many times the system clock is used in the processor chip is calculated, and the frequency division number is calculated. Frequency division storage ROM2
Write in 02.

The frequency divider 201 reads the frequency division number in the frequency division number storage ROM 202 when the system is activated, and divides the system clock 102 according to the value. As a result, the processor clock 203 having a cycle that is a predetermined multiple of the cycle of the system clock 102 is generated, and the processor chip 103 uses the generated processor clock 203 to fetch and execute instructions. The arithmetic unit, the control unit, the register file, the memory and the like necessary for the internal configuration of the processor chip are omitted from this figure.

FIG. 2 is a block diagram of a parallel computer system configured using the parallel computer processor chip of the present invention. In the figure, 101 is a clock generator configured by a crystal oscillator circuit, 102 is a system clock output from the clock generator, and 103 is the processor chip described in FIG. When configuring a parallel computer system, a plurality of such processor chips are used.

In the configuration of this embodiment, the same system clock 102 is supplied to each processor chip 103. However, the processor chip 103 uses the supplied system clock 102 as described with reference to FIG. Since each of the processor chips 103 has a function of performing frequency division with a unique frequency division number, it becomes possible for each processor chip 103 to operate with clocks of different cycles.

FIG. 3 shows a specific configuration example of the frequency divider 201. The frequency divider 201 includes a counter 301 that counts the system clock 102, a comparator 302 that compares the value of the counter with the value of the frequency division number setting register 303, and the frequency division number stored in the frequency division number storage ROM 202. Is configured from the frequency division number setting register 303. Also,
The counter 301 includes a register 3011 and a +1 adder 3
012 and a selector 3013.

The system clock 102 is a register 301.
Each time it is input to 1, the +1 adder 3012 and the selector 3
The system clock 102 is counted via 013. The comparator 302 compares the count value of the register 3011 with the value set in the frequency division number setting register 303, and when both are equal, outputs the frequency-divided processor clock 203 via the AND gate 304. To do.
Further, when the comparator 302 outputs a match, the selector 3013 selects “0” by the output and the register 301
Write 0 to 1 and clear register 3011 to zero,
The system clock 102 is counted again in the same manner as described above.

[0015]

As described above, according to the present invention, the processor chip is provided with the means for dividing the input clock and the means for storing the division number. The chip can be operated with a clock having a cycle of a predetermined multiple of the input clock. Moreover, if a parallel computer is configured using such a processor chip,
Since each processor chip operates by dividing the system clock by the division number set for each processor chip, it is possible to configure a parallel computer in which processor chips with different operable clock cycles are mixed, and the number of processors is It is particularly effective when applied to a very large number of MIMD type massively parallel computers of 100 processors or more.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a processor chip of the present invention.

FIG. 2 is a configuration diagram of a parallel computer system configured using the processor chip of the present invention.

FIG. 3 shows a specific configuration example of a frequency divider.

[Explanation of symbols]

 101 clock generator 102 system clock 103 processor chip 201 frequency divider 202 frequency division storage ROM 203 processor clock

Claims (1)

[Claims] 1. A processor chip for a parallel computer, comprising at least a unit for dividing an input clock and a unit for storing a frequency division number, which is stored when the processor chip is activated. A parallel circuit characterized in that a frequency division number is set in the frequency division means, the input clock is frequency-divided according to the set frequency division number, and the processor chip is operated with a clock having a cycle of a predetermined multiple of the input clock. Processor chip for computer.