JPH05257821A - Check sum calculating circuit - Google Patents

Abstract

PURPOSE:To prevent a check sum from being miscalculated even by a calculating circuit composed of hardware even when complicate processing is performed by selecting and supplying two addition clocks, generated at the time of only reading and only writing, from the control signal of an IC memory card. CONSTITUTION:An adder 4 cumulatively adds the data from a data line to the output data of a register 5 and inputs the result to the register 5. The register 5 latches the addition result from the adder 4 with the addition clock signal from a switching circuit 6. The card control signal for the IC memory card 2 consists of the inverse of CE, the inverse of WE, and the inverse of OE, which are combined by gate circuits 7 and 8 to generate a clock signal for reading and a clock signal for writing. Those two signals are selected by the switching circuit 6 according to a switching signal and inputted to the addition clock input of the register 5 of a cumulative adding circuit 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a checksum calculation circuit provided in an interface circuit between an IC memory card and a device connecting the IC memory card.

[0002]

2. Description of the Related Art As a means for checking the reliability of an IC memory card, there is known a method of comparing the checksum value of a part or all of the data blocks of the memory in the card with a value which has been checked in advance. .. That is, by checking the value of the checksum of the data block of the IC memory card in advance, and when reading the data block, the checksum of the data block is calculated and compared with the value checked in advance. This is a method of detecting the data error of the read data block and evaluating the reliability of the data block. Further, in an IC memory card using a rewritable memory such as SRAM, the checksum of the data block changes every time data is written, so it is necessary to calculate the checksum also at the time of writing.
The checksum calculation normally uses a value obtained by adding all the respective data of the data block in relation to the IC memory.

Conventionally, the calculation of the checksum has been carried out by a microcomputer incorporated in the device by software or by a hardware calculation circuit connected to the data line of the IC memory card. Further, the conventional hardware-like calculation circuit cumulatively adds the data each time the IC memory card is accessed.

[0004]

Conventionally, when the checksum calculation is processed by software, flexible processing is possible, but there is a drawback that the processing takes time and the speed becomes slow. In addition, the conventional hardware-based calculation circuit writes data to be written each time the IC memory circuit is accessed, or
Since the data to be read was cumulatively added, it could be used without problems when writing or reading a simple data block, but when complicated processing was required, it was miscalculated and could not be used. For example, when writing a data block to an IC memory card that uses a rewritable memory such as SRAM, the data is read every time one data is written, and the data is written while verifying. Is a process that is usually performed, but in such a case, in a conventional hardware calculation circuit, one data is added twice at the time of writing and at the time of reading for verification, so it is accurate. It will not be possible to obtain such a result.

Therefore, an object of the present invention is to provide a checksum calculation circuit that solves the above problems.

[0006]

To achieve the above object, the present invention relates to an interface circuit between an IC memory card and a device, and a cumulative addition circuit for cumulatively adding data on a data line of the IC memory card, and the IC. From the control signal of the memory card, an addition clock generating means for generating an addition clock generated only when reading the IC memory card and an addition clock generating only when writing to the IC memory card, and two addition clock generating means Means for selecting any one of the addition clocks and supplying it as an addition clock for giving an addition timing to the cumulative addition circuit.

[0007]

According to the present invention, as an addition clock for giving the addition timing of the cumulative addition circuit for calculating the checksum, an addition clock generated only when the IC memory card is read from the control signal of the IC memory card is written. And an addition clock that is generated only at the time of incorporation, and one of these two addition clocks is selected and given to the cumulative addition circuit. By doing so, for example, SRAM
When writing a data block to a rewritable IC memory card using memory, each time one data is written,
Even if data is written while verifying, the checksum will not be miscalculated. That is, if the addition clock generated only at the time of writing is added to the cumulative addition circuit, the addition clock is not added to the cumulative addition circuit even if the data is read at the time of verification, so the calculation result of the cumulative addition circuit does not change. Therefore,
Since cumulative addition is performed only when writing a data block, erroneous checksum calculation does not occur. As mentioned above,
According to the present invention, erroneous calculation of a checksum can be prevented even if a hardware calculation circuit or complicated processing is performed. In cases other than the above example, the checksum can be accurately calculated in the case of general processing by switching the addition clock according to the present invention.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a checksum calculation circuit according to the present invention. The IC memory card 2 is attached to the card connector 3 and is connected to the interface circuit 20 of the main device via the connector 3. In the interface circuit 20, 1 is a cumulative addition circuit, which is composed of an adder 4 for inputting data from the data line 10 and a register 5. The adder 4 cumulatively adds the data from the data line 10 to the output data of the register 5 and inputs it to the register 5. The register 5 latches the addition result from the adder 4 by the addition clock signal from the switching circuit 6. Register 5
Since the cumulative addition result remains, the checksum calculation result can be read by reading this value from the calculation result reading line 12 at an appropriate time. Further, the calculation result can be cleared by clearing the register 5 with the calculation result clear signal. In this embodiment, the IC memory card 2
The card control signal for is composed of an inverted CE signal, an inverted WE signal, and an inverted OE signal, and indicates a chip enable signal, a write enable signal, and an output enable signal of the IC memory card 2, respectively. These signals are combined in the gate circuits 7 and 8 to create a read clock signal and a write clock signal. These two signals are selected by the switching circuit 6 based on the switching signal, and the cumulative addition circuit 1
Input to the addition clock input of the register 5. Reference numeral 11 is a card address line for transmitting a card address signal
Input to the address signal input of the C memory card 2. The signals input to and output from the checksum calculation circuit as described above are input to and output from the processing device in the main device. The processor comprises a CPU, a ROM storing a control program for the CPU, and a RAM having a work area, and controls input / output signals according to the control program.

An operation example of the checksum calculation circuit will be described with reference to FIG. That is, FIG. 2 shows that when a data block is written to and read from a rewritable IC memory card 2 such as an SRAM card,
This checksum calculation circuit calculates the checksum,
The flow which checks a data error is shown.

First, in S1, when a data block is written in the IC memory card 2, the switching signal is set so that the switching circuit 6 outputs the clock signal during writing. Since the clock signal at the time of writing is output only at the time of writing,
Verify data while writing data block
Therefore, the checksum calculation will not be incorrect even if you read it. Next, in S2, immediately before writing the data block, the checksum calculation result, that is, the cumulative addition circuit 1
Clear register 5 of. Then, in S3, when data is written in the data block A, the checksum calculation result of the data block remains in the register 5 of the cumulative addition circuit 1. This is read in S4 and written in a predetermined location (address) of the IC memory card 2 in S5. As a result, when reading the data block, the checksum at the time of writing can be known and compared with the checksum at the time of reading. Then, in S6, the read-out clock signal is output from the switching circuit 6 by the switching signal, the checksum calculation result in the register 5 is cleared in S7, the data of the data block A of the IC memory card 2 is read in S8, and this is read in S9. At the time of reading, the checksum calculation result of the data block obtained in the register 5 is read, the checksum calculation result at the time of writing written from the IC memory card 2 to S5 at S10 is read, and the checksum at the time of writing at S11. The calculation result and the checksum calculation result at the time of reading are compared, and when the two match, it is determined that the data block read in S12 is normal, and when they do not match, it is determined that the data block read in S13 is abnormal. ,finish.

[0011]

As described above, by using the checksum calculation result according to the present invention, it is possible to prevent erroneous checksum calculation at the time of reading or writing, which involves complicated processing of data in the IC memory card.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the same embodiment.

[Explanation of symbols]

 1 Cumulative addition circuit 2 IC memory card 4 Adder 5 Register 6 Switching circuit 7, 8 Gate circuit

Claims (1)

[Claims] 1. An interface circuit between an IC memory card and a device, a cumulative addition circuit for cumulatively adding data on a data line of the IC memory card, and the IC.
From the control signal of the memory card, an addition clock generating means for generating an addition clock generated only when reading the IC memory card and an addition clock generating only when writing to the IC memory card, and two addition clock generating means A checksum calculation circuit, comprising means for selecting any one of the addition clocks and supplying it as an addition clock for giving an addition timing to the cumulative addition circuit.