JPH05250252A - Address generating circuit - Google Patents

Abstract

PURPOSE:To provide the address generating circuit which can generate plural cyclic addresses and can select the address to be used from plural cyclic addresses. CONSTITUTION:This circuit is provided with a comparing circuit 8 which compares values of start address registers 1 to 4 with those of current address registers 5 to 7, an adding circuit 10 which increments values of current address registers 5 to 7, a multiplexer 11 which determines values obtained by incrementing values of current address registers or values of start address registers 1 to 4 as values to be stored in current address registers 5 to 7 in accordance with the value of the comparing circuit 8, a pointer 12 which designates one of plural start address registers 1 to 4, and a pointer register 14 which designates places of start address registers to be used to the pointer 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention In the present invention, in an address generating circuit capable of cyclic addressing, it is not necessary to fix the specification of cyclic addresses from the first to the last, and it is possible to specify from any position to any position. The present invention relates to an address generating circuit that can be used.

[0002]

2. Description of the Related Art In a conventional address generation circuit, when a cyclic address is used, a register for storing three kinds of addresses of a start address, an end address and a current address is used, each address is written in the register, and a memory is accessed. By executing the cyclic address.

[0003]

However, in the above-mentioned conventional configuration, since only one cyclic address can be set, when two or more cyclic addresses are used, a program or the like is used to perform calculations other than at the pointer. There was a problem that the address had to be determined by using the address.

The present invention solves the above-mentioned conventional problems. Even if there are two or more addresses that use a cyclic address, n addresses can be cyclically addressed without using a program or the like. The purpose is to realize a generator circuit.

[0005]

In order to solve the above conventional problems, the address generating circuit according to the present invention has the following configuration. That is, n start address registers, n-1 current address registers, a pointer designating which start address register of the n start address registers is to be used, and what number of the start address register A pointer register that specifies whether to use the start address registers up to the second, a comparison circuit that compares the values of the start address register specified by the pointer and the current address register, and an addition that increments the value of the current address register. And a multiplexer for determining whether to store the incremented value or the start address in the current address register according to the value of the comparison circuit.

[0006]

With the above structure, n cyclic addresses can be realized only by setting data in the address register, and since it has a pointer register, from n cyclic addresses to arbitrary positions. The cyclic addressing of can be realized.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an address generating circuit according to an embodiment of the present invention. As an example, the address generating circuit shown in FIG. 1 is an address generating circuit that can realize three cyclic addresses.

In FIG. 1, reference numerals 1, 2, 3, and 4 are first, second, third, and fourth start address registers, respectively. Reference numerals 5, 6, and 7 are first, second, and third current address registers, respectively. 8 is the start address register 1
4 is a comparison circuit for comparing the values of the current address registers 5 to 7. Reference numeral 9 is an output of the comparison circuit 8.
An adder circuit 10 increments the current address. Reference numeral 11 is a multiplexer for determining whether to store the value obtained by incrementing the value of the current address register or the value of the start address register 1 to 4 in the current address register 5 to 7 according to the value of the comparison circuit 8. Reference numeral 12 is a pointer for designating which of the first, second, third and fourth start address registers 1 to 4 is to be used.
This pointer 12 is the first start address register 1
And the first current address register 5, the second start address register 2 and the second current address register 6, and the third start address register 3 and the third current address register 7 as a set. Reference numeral 13 is an address output line. Reference numeral 14 is a pointer register for designating which start address register is used for the pointer 12.

The operation of the address generating circuit according to this embodiment having the above structure will be described below. Here, for example, the first start address register 1 is "0", the second start address register 2 is "2", the third start address register 3 is "4", and the fourth start address register 4 is Is "7", the first current address register 5 is "0", the second current address register 6 is "3", and the third current address register 7 is "4".
Is input and the pointer register 14 is set to use "1" to "3", the operation will be described.

At the timing of address generation, since the pointer 12 points to the first address register, the cyclic address is performed between the first start address register 1 and the second start address register 2. Here, the value “0” of the first current address register 5 is output to the address output line 13 as an address. Further, in the comparison circuit 8, the value “2” of the second start address register 2 and the first current address register 5
The value "1" obtained by incrementing the value "0" in the adding circuit 10 is compared. At this time, since the output of the adder circuit 10 is smaller, this value “1” is substituted into the first current address register 5.

Next, since the pointer 12 points to the second address register, it becomes a cyclic address between the second start address register 2 and the third start address register 3, and the value of the second current address register 6 " 3 "
Is output to the address output line 13. The comparison circuit 8 compares the value “4” of the third start address register 3 with the output “4” of the adder circuit 10 obtained by incrementing the value “3” of the second current address register 6. At this time, since both are the same, the value "2" of the second start address register 2 is substituted into the second current address register 6.

Next, the pointer 12 points to the third address register, becomes a cyclic address between the third start address register 3 and the fourth start address register 4, and the value "4" of the third current address register 7 Is output to the address output line 13. In the comparison circuit 8, the fourth
The value "7" of the start address register 4 and the output "5" of the adder circuit 10 obtained by incrementing the value "4" of the third current address register 7 are compared. At this time, since the two values are not equal, the output "5" of the adder circuit 10 is substituted into the third current address register 7.

Since the pointer register 14 is set to use 1 to 3, the pointer 12 points to the first start address register 1 and the value "1" of the first current address register 5 is the address. Output line 1
3 is output. The comparison circuit 8 increments the value “2” of the second start address register 2 and the value “1” of the first current address register 5 by the addition circuit 10
The outputs "2" of are compared. At this time, both values are equal, so the value of the first start address register 1 is "0".
Is substituted into the first current address register 5.

By repeating the above, the value of the first current address register 5 is "0"-"1"-"0"-
Repeat “1” to repeat the second current address register 6
Is "3"-"2"-"3"-"2", and the value of the third current address register 7 is "4"-"5"-
It becomes "6"-"4", and the output of the address output line 13 is "0"-"3"-"4"-"1"-"2"-"5"-.
"0"-"3"-"6"-"1"-"2"-"4" is output, and three cyclic addresses are sequentially generated. In this embodiment, a plurality of cyclic addresses can be realized as described above.

Next, assuming that the value of the pointer register 14 is from "2" to "3" and the other conditions are the same as in the above example, regardless of the value of the first start address register 1. , "3"-"4"-"2"-"5"
The value of the address output line 13 changes in the order of- "3"-"6"-"2"-"4". For this reason, it becomes possible to select and use only a necessary portion by forming a plurality of cyclic addresses.

[0016]

According to the present invention, a plurality of cyclic addresses can be realized without software such as a program by using a plurality of start address registers and a current address register, and the number of cyclic addresses up to what number is used. By providing a pointer register that specifies whether or not, it is possible to select an arbitrary set of cyclic addresses from a plurality of cyclic addresses.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an address generation circuit according to an embodiment of the present invention.

[Explanation of symbols]

 1 1st start address register 2 2nd start address register 3 3rd start address register 4 4th start address register 5 1st current address register 6 2nd current address register 7 3rd current address register 8 Comparison circuit 9 Output 10 Addition circuit 11 Multiplexer 12 Pointer 13 Address output line 14 Pointer register

Claims (1)

[Claims] 1. n start address registers, n
-1 current address register, a pointer designating which start address register of the n start address registers is used, and the start address register of which number is used in the pointer portion. Depending on the value of the comparison circuit, a pointer register that specifies whether or not, a comparison circuit that compares the values of the start address register and the current address register specified by the pointer, an addition circuit that increments the value of the current address register, An address generation circuit having a multiplexer for determining whether to store an incremented value or a start address value in a current address register.