JPH05120192A - Ram control circuit - Google Patents

Abstract

PURPOSE:To effectively use the control area of a disconnected channel. CONSTITUTION:This control circuit is provided with such feature that a channel address generation circuit 3 generates a channel address (b), and addresses the channel area of a RAM 1, and a null area address register 6 generates a null area address (c) via an adder 8, and addresses an FW trace area, and furthermore, the RAM 1 is addressed by a RAM address (d) selecting one of the channel address (b) or the null area address (c), and an area other than the channel area is set as the FW trace area, therefore, a disconnected channel area can be effectively used.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a RAM control circuit, particularly a control area used by firmware for each channel.
A RAM control circuit in an input / output control device included in M.

[0002]

2. Description of the Related Art Conventionally, a RAM control circuit of this type is shown in FIG.
, A RAM 10 having a control area for each channel for firmware, an FW channel register 20 showing the channel number currently being executed by the firmware, and an F
A channel address generation circuit 30 for generating a channel address (RAM address) b from the contents of the W channel register 20 and the relative value a of each channel area of the RAM 10 was provided.

In such a RAM control device, the RAM address of the control area for each channel is fixed.

[0004]

SUMMARY OF THE INVENTION The conventional RAM described above.
Since the control circuit has a fixed RAM address in the control area for each channel, there is a drawback in that it is necessary to secure a control area for channels that are not connected.

[0005]

SUMMARY OF THE INVENTION The circuit of the present invention is a RAM control circuit in an input / output control device having a control area used by firmware for executing an input / output operation in a random access memory corresponding to the channel. A relative value of a channel configuration register that stores configuration information, an FW channel register that indicates a channel number that the firmware is currently executing, contents of the channel configuration register and the FW channel register, and a start address of each channel control area of the RAM. A channel address generation circuit that generates an address of the RAM from the final address generation circuit that generates a final address of the channel region of the RAM from the channel configuration register; and an empty area of the RAM that is addressed from the final address generation circuit. Free space to do An area address register, an adder for advancing the contents of the empty area address register, a selector for selecting one of the output of the channel address generation circuit and the adder by a microinstruction. To do.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention.

First, each component will be described. A random access memory (RAM) 1 is a memory that holds an area used by firmware, and has an area of a plurality of words for each channel by the number of channels of the maximum configuration. The FW channel register 2 indicates the channel number currently executed by the firmware, and matches the channel area number of the RAM 1. Channel configuration register 4
Indicates a channel connected to the entire device.
More specifically, it has a 1-bit flag for each channel, and the content when connected is "1".

The channel address generation circuit 3 includes an FW channel address register 2 and a channel configuration register 4.
It is a circuit for calculating the channel address b from each content of the above and the relative value a of the channel area. Further, a channel final address generation circuit 5 for calculating the final address of the channel area from the channel configuration register 4 and an empty area address register 6 showing an empty area address c are provided.

The empty area address register 6 includes an adder 8
The data selected by the free area address register input selector 7 is input from the data added by 1 and the data of the channel final address generation circuit 5. At this time, since the selector 7 is a plus 1 by the adder 8,
When the final address of AM is exceeded, the channel final address register generation circuit 5 is selected, and when it is not exceeded, the output data of the adder 8 is selected.

The selector 9 selects one of the channel address b and the empty area address c, and the selection is performed by a micro instruction. This output is the RAM address d, which indicates the address of RAM1.

In the example of FIG. 1, the maximum configuration is 8 channels, but only 6 channels are connected. For simplicity of explanation, the channel numbers are 2 and 3
2 channels are not connected. RA
Since the channels M2 and M3 are not connected to each other, a region for two channels is unnecessary for M1. Therefore, RAM1
The regions that must be in the region are the channel 0 region to the channel 1 region and the channel region 4 to the channel region 7.

The channel final address e indicates the final address of the channel 7 area which is the area of the final channel. At this time, an empty area from the channel final address e to the final address f is created, and this area is used as the FW trace area. The FW trace area is an area for tracing and holding data that the firmware wants to leave at the time of failure and at the time of evaluation. This region is originally a region of the channel 6 region and the channel 7 region.

The RAM address d at this time will be described.
The RAM address d naturally refers to the address of the RAM 1, and is from the channel 0 area to the channel 1
An area, a channel address pointing from the channel area 4 to the channel 7 area, and an empty area c pointing to the FW trace area are selected by the selector 9 and become the RAM address d.
In this case, the channel address b from the channel 4 area to the channel 7 area is advanced by two channel areas because it can be seen from the contents of the channel configuration register 4 that the channel 2 and the channel 3 are not connected. become.

The channel address b is the FW channel register 2 and the channel configuration register 4 as described in the configuration.
And the relative value a of the channel area are generated by the channel address generation circuit 3. The access area of the RAM 1 in this case is from the start address g to the channel end address e.
Up to.

The free area address c is the output of the adder 8, which is obtained by adding 1 to the content of the free area register 6, so that the channel connected from the channel configuration register 4 is originally corrected. This is due to the channel final address generation circuit 5 for calculating RA in this case
The access area of M1 is from the plus 1 of the channel final address e to the final address f.

Therefore, the unconnected channel area can be used as the FW trace area of the firmware.

[0017]

As described above, the present invention has the effect of effectively utilizing the limited RAM area by releasing the free area when there is a channel that is not connected. In particular, in the case of evaluation and the like, there are few cases where all channels are connected, and since the evaluation is performed for a certain number of channels, the rest can be made as many areas for other purposes as possible.

[Brief description of drawings]

FIG. 1 is a block diagram of a RAM control circuit according to the present invention.

FIG. 2 is a block diagram showing a conventional example.

[Explanation of symbols]

 1, 10 RAM 2, 20 FW channel register 3, 30 channel address generation circuit 4 channel configuration register 5 channel final address generation circuit 6 empty area address register 7 selector 8 adder 9 selector a channel area relative value b channel address c empty Area address d RAM address e Channel final address f Final address g Start address

Claims (1)

[Claims] 1. A channel configuration register for storing channel configuration information in a RAM control circuit in an input / output control device having a control area used by firmware for executing an input / output operation in a random access memory corresponding to a channel, FW indicating the channel number that the firmware is currently executing
A channel register, a channel address generation circuit for generating an address of the RAM from the contents of the channel configuration register and the FW channel register, and the relative value of the start address of each channel control area of the RAM; A final address generation circuit for generating a final address of a RAM channel area, a free area address register for addressing a free area of the RAM from the final address generation circuit, and an addition for incrementing the contents of the free area address register And a selector that selects one of the outputs of the channel address generation circuit and the adder by a microinstruction, the RAM control circuit.