JPH05243571A - Field effect type transistor array - Google Patents

Abstract

PURPOSE:To obtain a field effect transistor array for effectively restricting leakage between source and gate electrodes and between drain and gate electrodes by providing a multi-phase construction for an insulation film of a transistor. CONSTITUTION:A gate electrode G selectively bonded to a FET forming region on the surface of a clear substrate 1 is connected to electrodes x in rows, and the film thickness of an SiO2 film 2 formed on and covering the surface of the substrate 1 and other items is set to the range of about 1000 to 5000 angstroms. And an amorphous silicon layer AS formed and adhered to a strip shape and covering the FET formation region on SiO2 film 2 fully covers the gate electrode G and has a shape extended to the right and left from the gate electrode G. Therefore, an amorphous silicon layer AS is extended between the source and drain electrodes S and D and gate electrode G, thereby forming two layers together with the Si02 film, and the leakage between the gate electrode and source or drain electrode can be restricted thereby enhancing the reliability of each transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor array.

[0002]

2. Description of the Related Art Recently, studies have been made on the use of a field effect transistor (FET) using amorphous silicon as a switching element provided for each pixel of a liquid crystal matrix display panel. This type of liquid crystal matrix panel has full-surface electrodes on one substrate and matrix electrodes on the other substrate to provide FETs at each intersection.
It has a structure in which a display electrode to be a pixel is formed by connecting to T, and a liquid crystal is filled in a gap between these two substrates. Amorphous silicon FETs are advantageous in that they can be uniformly formed on a large transparent substrate and have a large on / off current ratio, and are suitable as switching elements for this type of panel. However, amorphous silicon FE
When a large number of Ts are arranged in a matrix on a transparent glass substrate, between the source / drain electrodes and the gate electrodes, and
There is a risk of leakage at the intersection of the row and column electrodes. That is, conventionally, silicon oxide SiO ₂ or silicon nitride Si ₃ N ₄ is used as an insulating layer interposed between the source / drain electrode and the gate electrode, and by homogenizing the film quality and increasing the film thickness. Efforts have been made to form an insulating layer that does not suffer from the aforementioned drawbacks. However, when silicon nitride is applied as a film at a temperature of about 350 ° C. or higher, a hard one can be manufactured, but it has a drawback that cracks easily occur. Silicon oxide can also be formed by a thermal CVD method at about 500 ° C. or lower, a sputtering method, or a plasma CVD method, but there is a drawback in that even if the film thickness is increased to about 6000Å, leakage still occurs.

When such an amorphous FET is used in a liquid crystal matrix panel and designed with 200 gate lines and 250 drain lines, the number of gate-drain intersections is 50,000. Of these, if one FET leaks, 449 (200 + 249) FETs will be defective. This leak phenomenon is caused by dust in the air, pinholes in the insulating layer, or erosion of amorphous silicon by an etching solution. However, even if measures are taken to eliminate the above-mentioned cause, many leaks still occur if the film quality of the insulating layer is poor. To create an FET array of amorphous silicon on a glass substrate,
Only heat treatment at about 500 ° C. or lower is possible, and there is a limit to strengthening silicon oxide or silicon nitride by heat treatment, and a perfect insulating layer cannot be obtained.

[0004]

SUMMARY OF THE INVENTION The present invention has been made to solve such a drawback, and it is possible to effectively suppress the leak between the source / gate electrode and between the drain / gate electrode of a transistor. A field effect transistor array is provided.

[0005]

A field effect transistor array according to the present invention has an insulating substrate, a plurality of row electrodes formed in parallel on the surface of the insulating substrate, and field effect transistors formed by connecting to the row electrodes. A gate electrode formed in a region, an insulating layer formed to cover the row electrode and the gate electrode, a semiconductor layer formed in at least a region where a field effect transistor is formed on the insulating layer, and a semiconductor layer formed on the semiconductor layer. A source electrode and a drain electrode formed on
A column electrode connected to the drain electrode is provided, and the insulating film has a two-layer structure.

Further, the field effect transistor array of the present invention is formed on an insulating substrate, a plurality of row electrodes formed in parallel on the surface of the insulating substrate, and a region connected to the row electrodes where the field effect transistors are formed. An insulating layer formed of a two-layer structure of a gate electrode, a silicon oxide film, and a silicon nitride film, which is formed to cover the row electrode and the gate electrode, and at least a region where a field effect transistor is formed on the insulating layer. A semiconductor layer formed, a source electrode and a drain electrode formed on the semiconductor layer, a column electrode connected to the drain electrode, and a display electrode connected to the source electrode, wherein the semiconductor layer is the transistor. The film thickness of the insulating film is set to 5000 Å or less by allowing the insulating film to exist together with the insulating film at the position and the intersection of the row electrode and the column electrode. It was done.

[0007]

According to the field effect transistor array of the present invention, since the insulating film of the transistor has a multi-phase structure, even if a pinhole is generated in each layer, the generation position of this pondhole can be the same in each layer. Since the property is extremely small, pinholes penetrating the multi-layered insulating layer are hardly generated, and current leakage between the gate electrode and the source or drain electrode is suppressed.

[0008]

EXAMPLES Examples will be described below with reference to the drawings. 1 and 2, (1) is a transparent substrate such as a glass plate,
(G) is a gate electrode selectively deposited on the FET formation region on the surface of the transparent substrate (1) and is connected to the row electrode (X). These gate electrode (G) and row electrode (X)
Is formed by vapor deposition or sputtering of ITO (Indium Tin Oxide). (2) S _i formed on the substrate (1) surface to cover the gate electrode (G) and row electrodes (X)
O ₂ film, about 25 by thermal CVD or plasma CVD
The film is applied under heating at 0 to 300 ° C. The S _i O ₂ film (2)
The film thickness is set within the range of about 1000 to 5000Å.
This is for the following reasons. That is, the S _i O ₂ film (2), made for example, as thin as about 500Å about the unstable characteristics of the FET, also the dark current at the OFF time ^10-9
-8 A (However, when the gate voltage is 30 V and the drain voltage is 0 V)
And the variation of the obtained current is 10 ^-8 to 10 ^-5 A
It is very unstable. From the viewpoint of stabilizing the characteristics, 10
It is desirable to have a film thickness of about 00Å. On the other hand, the thicker the film, the smaller the leakage current, but the thicker the
Since the threshold voltage becomes high and the current hardly flows, the upper limit of the film thickness is preferably about 5000Å.

[0009] (AS) is a SiO ₂ film (2) amorphous silicon layer which is deposited in the strip over the FET forming region on the amorphous silicon by SiO ₂ film (2) over the entire surface to a plasma CVD method to be After wearing, it is formed into a predetermined pattern by etching. The amorphous silicon layer (AS) has a shape that completely covers the gate electrode (G) and extends to the left and right (FIG. 2) from the gate electrode (G). (S) and (D) are amorphous silicon layers (A
On S), the source / drain electrodes provided at a predetermined interval provided directly above the gate electrode (G),
It is formed by sputtering Al or the like. A part of the column electrode (Y) is also used as the drain electrode (D). (3) is a display electrode made of an ITO film, which is in contact with the source electrode (S).

With this structure, the amorphous silicon layer (AS) extends between the source / drain electrodes (S) (D) and the gate electrode (G), and the SiO ₂ film (2) is formed.
Since the two layers are formed, the leak between the source / drain electrodes (S) (D) and the gate electrode (G) is prevented. Further, since the amorphous silicon layer (AS) is also interposed at the intersections of the row / column electrodes (X) (Y), the current leak between them is also blocked.

In the above embodiment, the insulating film has a thickness of 5000
Was used following the SiO ₂ film monolayer Å, instead of this SiO ₂
It is also possible to use a two-layer structure of the membrane and the Si ₃ N ₄ membrane. In this case, the thickness of the SiO ₂ film is about 1000 to 2000 Å, Si ₃
The film thickness of the N ₄ film is set to about 1000 to 3000Å. Therefore, the total thickness of the insulating film is about 5000 Å or less.

[0012]

As is apparent from the above description, the field effect transistor array of the present invention has a multilayer structure of the insulating film of the transistor, so that the leakage between the gate electrode and the source or drain electrode is suppressed. Therefore, the reliability of each transistor can be improved.

Further, by providing a semiconductor layer in addition to the insulating film between both electrodes at the row / column electrode crossing position, sufficient insulation between the electrodes can be realized while using a thin insulating film.

[Brief description of drawings]

FIG. 1 is a plan view of an embodiment of a field effect transistor array of the present invention,

FIG. 2 is a sectional view taken along the line I-I ′ of the device of the present invention in FIG.

[Explanation of symbols]

1 transparent substrate G gate electrode X row electrode 2 SiO ₂ film AS amorphous silicon layer S source electrode D drain electrode Y column electrode 3 display electrode

Claims (2)

[Claims] 1. An insulating substrate, a plurality of row electrodes formed in parallel on the surface of the insulating substrate, a gate electrode connected to the row electrode in a region where a field effect transistor is formed, the row electrode and a gate. An insulating layer formed to cover the electrode, a semiconductor layer formed on at least a region where a field effect transistor is formed on the insulating layer, a source electrode and a drain electrode formed on the semiconductor layer, and a drain electrode Equipped with a continuous column electrode, the insulating film
A field-effect transistor array having a layered structure. 2. An insulating substrate, a plurality of row electrodes formed in parallel on the surface of the insulating substrate, a gate electrode connected to the row electrode in a region where a field effect transistor is formed, a silicon oxide film and silicon. An insulating layer having a two-layer structure of a nitride film and formed to cover the row electrode and the gate electrode, a silicon semiconductor layer formed on at least a region where a field effect transistor is formed on the insulating layer, and this semiconductor layer The semiconductor device includes a source electrode and a drain electrode formed thereon, and a column electrode connected to the drain electrode, and the semiconductor layer is present together with the insulating film at the transistor position and at the intersection of the row electrode and the column electrode, and the insulation A field-effect transistor array characterized by having a film thickness of about 5000 Å or less.