JPH05243512A - Semiconductor device having digital and analog parts mounted mixedly - Google Patents

Abstract

PURPOSE:To check getting-round of noise from a digital circuit to an analog circuit in CMOS.LSI wherein digital and analog parts are mounted mixedly. CONSTITUTION:A digital part 42 and an analog part 41 are provided on the same semiconductor substrate, and in the analog part 41, a sub-line 2 for fixing a substrate potential is wired in parallel to a grand line 1 and connected to a pad 9. In the digital part 42, a sub-line 4 for fixing the substrate potential is wired in parallel to a grand line 6 and connected to a pad 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog / digital mixed semiconductor device such as a codec.

[0002]

2. Description of the Related Art Semiconductor devices such as CMOS / LSI are
Type or N type conductivity type semiconductor substrate is formed on the other conductivity type island region, and N type MOS transistors and P type MOS transistors are simultaneously formed on the same substrate. In the case of CMOS / LSI, M
The potential of the region (back gate) where the channel is formed under the gate oxide film of the OS transistor is connected to the power supply (VDD) in the P-type transistor and is connected to the ground (GND) in the N-type transistor. This is because the MOS transistor has a substrate effect (back gate effect), and in order to avoid this effect, and because CMOS / LSI always has a thyristor connection, latch up due to the thyristor effect is avoided.

Further, considering that it is necessary to avoid latch-up of these substrates or island regions, it is necessary to connect them to the ground or the power supply with the impedance as low as possible. For this reason, it is usually connected to the low-impedance ground wiring or power wiring at one or more positions within several tens to several hundreds of microns from the MOS transistor.

As described above, in the CMOS / LSI, the back gate must be fixed to a certain potential. Figure 3
FIG. 6 is a plan view showing a conventional semiconductor device. As shown in FIG. 3, in a CMOS / LSI that is a conventional semiconductor device, the island-shaped region is divided into an analog section 41 and a digital section 42. In the analog section 41, the ground line 23 of the metal layer of the analog circuit is connected to the pad 28, and the pad 28 is connected to the ground. Further, the power supply line 24 of the metal layer of the analog circuit is connected to the pad 27, and the power supply of the circuit is supplied to the pad 27. Further, in the digital section 42, the ground line 26 of the metal layer of the digital circuit is connected to the pad 30, and the pad 30 is connected to the ground. Furthermore,
The power supply line 25 of the metal layer of the digital circuit is the pad 29.
, And the circuit power is supplied to the pad 29.

By the way, when an analog circuit and a digital circuit are mixedly mounted on a CMOS / LSI, it is necessary to suppress the sneak of noise from the digital section to the analog section as much as possible. As an effective method, it is possible to separate the power supply on the LSI.

[0006]

However, the CMO
In the power supply that gives the back gate potential of S / LSI,
The island area can be cut off into the digital section and the analog section, which suppresses the sneaking of noise. However, since the board cannot be cut off, it is possible to suppress the sneaking of noise through the board. There is a problem that you cannot do it.

The present invention has been made in view of the above problems, and when a digital circuit and an analog circuit are mixedly mounted on a CMOS / LSI, it is possible to suppress the sneak of noise from the power supply through the substrate. Digital that can
An object is to provide an analog-embedded semiconductor device.

[0008]

According to the present invention, there is provided a digital / analog mixed semiconductor device in which a digital circuit and an analog circuit are provided on the same semiconductor substrate, and at least one conductive type island region is provided. In the semiconductor device, a first power supply is supplied to the digital circuit and the analog circuit, and a second power supply separated from the first power supply is provided inside the digital circuit and the analog circuit. It is characterized in that it is supplied to the semiconductor substrate.

[0009]

In the present invention, the second power source is supplied to the semiconductor substrate in a state of being electrically disconnected from the first power source which is the power source of the circuit. As a result, a predetermined potential can be applied to the semiconductor substrate, and the first power source and the semiconductor substrate can be electrically separated on the semiconductor substrate, and the sneak of noise from the digital circuit to the analog circuit can be suppressed. can do.

[0010]

1 is a plan view showing a semiconductor device according to a first embodiment of the present invention. The present embodiment relates to a CMOS / LSI in which an N-type island-shaped region (hereinafter, also referred to as an N well) is provided on a P-type semiconductor substrate, and the metal wiring layers are the first metal wiring layer 43 and the first metal wiring layer 43. The first metal wiring layer 43 and the second metal wiring layer 4 are composed of two layers including a two-metal wiring layer 44.
Both are connected and wired by the contact 45 with the wiring 4. The semiconductor device according to the embodiment of the present invention is divided into an analog section 41 and a digital section 42 in the island region as in the prior art. In addition, the pads 27, 28, 29 and 30, the ground line 23, described in the prior art,
26 and the power lines 24 and 25 corresponding to the pads 7,
8, 10, 11 and ground lines 1, 6 and power supply lines 3, 5 are similarly configured. Further, in this embodiment, in the analog section 41, the sub-line 2 of the metal layer for fixing the substrate potential of the analog circuit is wired in parallel to the ground line 1 and connected to the pad 9. A power supply for fixing the substrate potential is supplied to the pad 9. Also in the digital section 42, the sub-line 4 of the metal layer for fixing the substrate potential of the digital circuit is wired in parallel with the ground line 6 and connected to the pad 12. A power supply for fixing the substrate potential is supplied to the pad 12. In other words, it is a CMOS LSI having an N well on a P type semiconductor substrate,
The P-type semiconductor substrate is connected to the ground, and the N well is connected to the power supply.

In the semiconductor device configured as described above, the P-type semiconductor substrate or the N well must be connected to the ground or the power supply with the lowest possible impedance in consideration of latch-up, as described in the prior art. In this embodiment, the sub-lines 2 and 4 for fixing the substrate potential are wired in parallel with the ground lines 1 and 6 with a low-impedance metal layer and connected to the P-type semiconductor substrate in the vicinity of the N-type MOS transistor. Therefore, a stable potential is applied to the P-type semiconductor substrate with low impedance, and the circuit power source and the P-type semiconductor substrate are connected to each other without connecting the circuit ground and the P-type semiconductor substrate on the LSI.
The semiconductor substrate is electrically separated from the semiconductor substrate. The separated power source is connected outside the LSI.

Therefore, since the P-type semiconductor substrate is electrically separated from the power source of the circuit and is connected by the power source for fixing the substrate potential which gives a stable potential and causes less noise, the P-type semiconductor substrate is connected. Via the digital circuit 42
It is possible to suppress noise from flowing into the analog circuit 41.

FIG. 2 is a plan view showing a semiconductor device according to the second embodiment of the present invention. In the second embodiment,
Similar to the first embodiment, the analog section 4 is used for the island region.
1 and the digital section 42, and the metal wiring layer is also the first
The metal wiring layer 43, the second metal wiring layer 44, and their contacts 45 are formed. Also, pad 1
8, 19, 21, 22 and ground lines 13, 17 and power supply lines 15, 16 are wired as in the first embodiment. Further, in this embodiment, the common pad 20 is used without dividing the wiring for the substrate potential fixing sub-line 14 into the analog portion 41 and the digital portion 42. In the first embodiment, P is provided on the wiring between the ground 1 of the analog circuit and the ground 6 of the digital circuit.
Since there is no contact with the semiconductor substrate, the grounds 1 and 6 of the analog circuit and the digital circuit can be electrically separated completely on the LSI. Therefore, in the first embodiment, the wiring of the sub-line 2 of the analog section 41 and the wiring of the sub-line 4 of the digital section 42 are separated, but this effect is small. Therefore, in this embodiment, the wiring of the sub-line 14 for fixing the substrate potential of the analog circuit and the digital circuit is shared by using only the pad 20. As a result, the number of LSI pins can be reduced.

The semiconductor device according to the first embodiment of the present invention is a P-type semiconductor substrate and an N-well CMOS / LSI.
However, similar effects can be obtained in a CMOS / LSI in which a P-type island-shaped region (P well) is formed on an N-type semiconductor substrate.

[0015]

As described above, in the digital / analog mixed CMOS / LSI according to the present invention, the second power supply for fixing the potential of the semiconductor substrate is supplied to the semiconductor substrate, so that the latch-up is prevented. Strong and less sneak of noise through the board. As a result, an LSI such as a digital / analog mixed high-precision codec that has not been realized in the past can be obtained.

[Brief description of drawings]

FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a plan view showing a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a plan view showing a conventional semiconductor device.

[Explanation of symbols]

1, 6, 13, 17, 23, 26; Ground lines 2, 4, 14; Sub-lines for fixing substrate potential 3, 5, 15, 16, 24, 25; Power supply lines 7, 8, 9, 10, 11, 12, 18, 19, 20, 2
1, 22, 27, 28, 29, 30; pad 43; first metal wiring layer 44; second metal wiring layer 45; contact between first metal wiring layer and second metal wiring layer

Claims (1)

[Claims] 1. A semiconductor device in which a digital circuit and an analog circuit are provided on the same semiconductor substrate and at least one conductive type island region is provided, wherein the digital circuit and the analog circuit have a first configuration. A digital / analog mixed mounting characterized in that a power source is supplied and a second power source separated from the first power source is supplied to the semiconductor substrate inside the digital circuit and the analog circuit. Semiconductor device.