JPH05242015A - コンピュータシステムと、そのシステムメモリと入力／出力デバイス間の転送データを記憶する方法 - Google Patents

コンピュータシステムと、そのシステムメモリと入力／出力デバイス間の転送データを記憶する方法

Info

Publication number
JPH05242015A
JPH05242015A JP4317365A JP31736592A JPH05242015A JP H05242015 A JPH05242015 A JP H05242015A JP 4317365 A JP4317365 A JP 4317365A JP 31736592 A JP31736592 A JP 31736592A JP H05242015 A JPH05242015 A JP H05242015A
Authority
JP
Japan
Prior art keywords
bus
data
memory
input
interface unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4317365A
Other languages
English (en)
Japanese (ja)
Inventor
Aldereguia Alfred
アルフレード・アルデレギア
Amini Nader
ナダー・アミニ
Richard Louis Horne
リチャード・ルイス・ホーン
Terence J Lohman
テレンス・ジョセフ・ローマン
Ngokku Toran Kang
カング・ンゴック・トラン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPH05242015A publication Critical patent/JPH05242015A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
JP4317365A 1992-01-02 1992-11-26 コンピュータシステムと、そのシステムメモリと入力／出力デバイス間の転送データを記憶する方法 Pending JPH05242015A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/816,203 US5255374A (en) 1992-01-02 1992-01-02 Bus interface logic for computer system having dual bus architecture
US816203 1992-01-02

Publications (1)

Publication Number Publication Date
JPH05242015A true JPH05242015A (ja) 1993-09-21

Family

ID=25219957

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4317365A Pending JPH05242015A (ja) 1992-01-02 1992-11-26 コンピュータシステムと、そのシステムメモリと入力／出力デバイス間の転送データを記憶する方法

Country Status (10)

Country Link
US (1) US5255374A (US20100012521A1-20100121-C00001.png)
EP (1) EP0553563A1 (US20100012521A1-20100121-C00001.png)
JP (1) JPH05242015A (US20100012521A1-20100121-C00001.png)
KR (1) KR960012356B1 (US20100012521A1-20100121-C00001.png)
CN (1) CN1029169C (US20100012521A1-20100121-C00001.png)
AU (1) AU652707B2 (US20100012521A1-20100121-C00001.png)
MY (1) MY109414A (US20100012521A1-20100121-C00001.png)
NZ (1) NZ245346A (US20100012521A1-20100121-C00001.png)
SG (1) SG44432A1 (US20100012521A1-20100121-C00001.png)
TW (1) TW243508B (US20100012521A1-20100121-C00001.png)

Families Citing this family (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2744154B2 (ja) * 1991-10-24 1998-04-28 株式会社東芝 バスシステム
WO1993019424A1 (en) * 1992-03-18 1993-09-30 Seiko Epson Corporation System and method for supporting a multiple width memory subsystem
US5497466A (en) * 1992-07-17 1996-03-05 Texas Instruments Inc. Universal address generator
US5745791A (en) * 1992-09-16 1998-04-28 Intel Corporation System for interfacing first and second components having different data path width by generating first and second component address to read data into buffer
US5450547A (en) * 1992-10-01 1995-09-12 Xerox Corporation Bus interface using pending channel information stored in single circular queue for controlling channels of data transfer within multiple FIFO devices
US5495585A (en) * 1992-10-16 1996-02-27 Unisys Corporation Programmable timing logic system for dual bus interface
US5442754A (en) * 1992-12-04 1995-08-15 Unisys Corporation Receiving control logic system for dual bus network
US5550989A (en) * 1993-05-28 1996-08-27 International Business Machines Corporation Bridge circuit that can eliminate invalid data during information transfer between buses of different bitwidths
US5522050A (en) * 1993-05-28 1996-05-28 International Business Machines Corporation Bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus
US5687371A (en) * 1993-09-27 1997-11-11 Intel Corporation Selection from a plurality of bus operating speeds for a processor bus interface during processor reset
US5551006A (en) * 1993-09-30 1996-08-27 Intel Corporation Low cost writethrough cache coherency apparatus and method for computer systems without a cache supporting bus
US5682498A (en) * 1993-11-12 1997-10-28 Intel Corporation Computer system with dual ported memory controller and concurrent memory refresh
JPH07152721A (ja) * 1993-11-29 1995-06-16 Mitsubishi Electric Corp マイクロコンピュータ
US5446869A (en) * 1993-12-30 1995-08-29 International Business Machines Corporation Configuration and RAM/ROM control of PCI extension card residing on MCA adapter card
US5835960A (en) * 1994-01-07 1998-11-10 Cirrus Logic, Inc. Apparatus and method for interfacing a peripheral device having a ROM BIOS to a PCI bus
US5805927A (en) * 1994-01-28 1998-09-08 Apple Computer, Inc. Direct memory access channel architecture and method for reception of network information
US5655151A (en) * 1994-01-28 1997-08-05 Apple Computer, Inc. DMA controller having a plurality of DMA channels each having multiple register sets storing different information controlling respective data transfer
US5828856A (en) * 1994-01-28 1998-10-27 Apple Computer, Inc. Dual bus concurrent multi-channel direct memory access controller and method
US5557757A (en) * 1994-02-02 1996-09-17 Advanced Micro Devices High performance integrated processor architecture including a sub-bus control unit for generating signals to control a secondary, non-multiplexed external bus
US5761450A (en) * 1994-02-24 1998-06-02 Intel Corporation Bus bridge circuit flushing buffer to a bus during one acquire/relinquish cycle by providing empty address indications
TW321744B (US20100012521A1-20100121-C00001.png) * 1994-04-01 1997-12-01 Ibm
US5559969A (en) * 1994-08-09 1996-09-24 Unisys Corporation Method and apparatus for efficiently interfacing variable width data streams to a fixed width memory
US5577230A (en) * 1994-08-10 1996-11-19 At&T Corp. Apparatus and method for computer processing using an enhanced Harvard architecture utilizing dual memory buses and the arbitration for data/instruction fetch
US5524235A (en) * 1994-10-14 1996-06-04 Compaq Computer Corporation System for arbitrating access to memory with dynamic priority assignment
CA2160500C (en) * 1994-11-30 1999-11-09 Amy Kulik Pci/isa bridge having an arrangement for responding to pci bridge address parity errors for internal pci slaves in the pci/isa bridge
US5613162A (en) * 1995-01-04 1997-03-18 Ast Research, Inc. Method and apparatus for performing efficient direct memory access data transfers
US6044166A (en) * 1995-01-17 2000-03-28 Sarnoff Corporation Parallel-pipelined image processing system
US5564027A (en) * 1995-04-20 1996-10-08 International Business Machines Corporation Low latency cadence selectable interface for data transfers between busses of differing frequencies
US5704058A (en) * 1995-04-21 1997-12-30 Derrick; John E. Cache bus snoop protocol for optimized multiprocessor computer system
US5793996A (en) * 1995-05-03 1998-08-11 Apple Computer, Inc. Bridge for interconnecting a computer system bus, an expansion bus and a video frame buffer
US5805843A (en) * 1996-02-01 1998-09-08 Qualcomm Incorporated Microprocessor bus interface unit for interfacing an N-bit microprocessor bus to an M-bit memory device
US5752260A (en) * 1996-04-29 1998-05-12 International Business Machines Corporation High-speed, multiple-port, interleaved cache with arbitration of multiple access addresses
US5758166A (en) * 1996-05-20 1998-05-26 Intel Corporation Method and apparatus for selectively receiving write data within a write buffer of a host bridge
US5815675A (en) * 1996-06-13 1998-09-29 Vlsi Technology, Inc. Method and apparatus for direct access to main memory by an I/O bus
US5845107A (en) * 1996-07-03 1998-12-01 Intel Corporation Signaling protocol conversion between a processor and a high-performance system bus
US6523080B1 (en) 1996-07-10 2003-02-18 International Business Machines Corporation Shared bus non-sequential data ordering method and apparatus
US5970253A (en) * 1997-01-09 1999-10-19 Unisys Corporation Priority logic for selecting and stacking data
US5822766A (en) * 1997-01-09 1998-10-13 Unisys Corporation Main memory interface for high speed data transfer
US5915126A (en) * 1997-08-12 1999-06-22 International Business Machines Corporation Computer system memory controller and method of burst data ordering translation
US6032212A (en) * 1997-08-14 2000-02-29 Goode; Jeff Device and method for interfacing PCI and VMEbus with a byte swapping circuit
EA002886B1 (ru) 1997-11-13 2002-10-31 Хайперспейс Коммьюникейшнз, Инк. Система пересылки файлов
KR100290092B1 (ko) * 1997-11-19 2001-05-15 박종섭 지연 응답신호 처리 입출력 버스 인터페이스 장치
US6687865B1 (en) 1998-03-25 2004-02-03 On-Chip Technologies, Inc. On-chip service processor for test and debug of integrated circuits
US6611891B1 (en) * 1998-11-23 2003-08-26 Advanced Micro Devices, Inc. Computer resource configuration mechanism across a multi-pipe communication link
KR100606698B1 (ko) * 1999-03-16 2006-07-31 엘지전자 주식회사 인터페이스 장치
US7051218B1 (en) 2001-07-18 2006-05-23 Advanced Micro Devices, Inc. Message based power management
US7725528B1 (en) 2002-03-06 2010-05-25 Rockwell Automation Technologies, Inc. System and methodology providing optimized data exchange with industrial controller
KR100449721B1 (ko) * 2002-05-20 2004-09-22 삼성전자주식회사 서로 다른 데이터 버스 폭을 갖는 장치들을 위한인터페이스 및 이를 이용한 데이터 전송방법
KR100450680B1 (ko) * 2002-07-29 2004-10-01 삼성전자주식회사 버스 대역폭을 증가시키기 위한 메모리 컨트롤러, 이를이용한 데이터 전송방법 및 이를 구비하는 컴퓨터 시스템
JP2004164579A (ja) * 2002-09-24 2004-06-10 Sharp Corp データバス幅変換装置およびデータ処理装置
US7152138B2 (en) * 2004-01-30 2006-12-19 Hewlett-Packard Development Company, L.P. System on a chip having a non-volatile imperfect memory
US7320045B2 (en) * 2004-02-05 2008-01-15 Research In Motion Limited Automatic detection of the bit width of a data bus
JP2006251916A (ja) * 2005-03-08 2006-09-21 Fujitsu Ltd Ｄｍａ転送システム及びｄｍａ転送方法
KR100723496B1 (ko) * 2005-08-11 2007-06-04 삼성전자주식회사 통합 ｆｉｆｏ 메모리를 사용하는 다중-레이트 입력데이터의 동기화기 및 방법
US8386682B2 (en) * 2010-06-30 2013-02-26 Intel Corporation Method, apparatus and system for maintaining transaction coherecy in a multiple data bus platform
CN102375787A (zh) * 2010-08-12 2012-03-14 鸿富锦精密工业（深圳）有限公司 利用内存窗口实现接口的系统及方法
CN105550145B (zh) * 2015-12-09 2018-05-08 天津国芯科技有限公司 一种用于单芯片系统内双总线间的传输同步器

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5697121A (en) * 1979-12-29 1981-08-05 Fujitsu Ltd Bus control system
JPH02140853A (ja) * 1988-11-21 1990-05-30 Yamaha Corp バス幅変換回路

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4371928A (en) * 1980-04-15 1983-02-01 Honeywell Information Systems Inc. Interface for controlling information transfers between main data processing systems units and a central subsystem
IT1206331B (it) * 1983-10-25 1989-04-14 Honeywell Inf Systems Architettura di sistema di elaborazione dati.
JPS61139866A (ja) * 1984-12-11 1986-06-27 Toshiba Corp マイクロプロセツサ
US4703420A (en) * 1985-02-28 1987-10-27 International Business Machines Corporation System for arbitrating use of I/O bus by co-processor and higher priority I/O units in which co-processor automatically request bus access in anticipation of need
US4683534A (en) * 1985-06-17 1987-07-28 Motorola, Inc. Method and apparatus for interfacing buses of different sizes
US4831520A (en) * 1987-02-24 1989-05-16 Digital Equipment Corporation Bus interface circuit for digital data processor
AU598101B2 (en) * 1987-02-27 1990-06-14 Honeywell Bull Inc. Shared memory controller arrangement
EP0288649B1 (en) * 1987-04-22 1992-10-21 International Business Machines Corporation Memory control subsystem
GB2211326B (en) * 1987-10-16 1991-12-11 Hitachi Ltd Address bus control apparatus
US5003465A (en) * 1988-06-27 1991-03-26 International Business Machines Corp. Method and apparatus for increasing system throughput via an input/output bus and enhancing address capability of a computer system during DMA read/write operations between a common memory and an input/output device
US5003463A (en) * 1988-06-30 1991-03-26 Wang Laboratories, Inc. Interface controller with first and second buffer storage area for receiving and transmitting data between I/O bus and high speed system bus
US5146564A (en) * 1989-02-03 1992-09-08 Digital Equipment Corporation Interface between a system control unit and a service processing unit of a digital computer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5697121A (en) * 1979-12-29 1981-08-05 Fujitsu Ltd Bus control system
JPH02140853A (ja) * 1988-11-21 1990-05-30 Yamaha Corp バス幅変換回路

Also Published As

Publication number Publication date
EP0553563A1 (en) 1993-08-04
SG44432A1 (en) 1997-12-19
KR960012356B1 (ko) 1996-09-18
KR930016886A (ko) 1993-08-30
MY109414A (en) 1997-01-31
TW243508B (US20100012521A1-20100121-C00001.png) 1995-03-21
US5255374A (en) 1993-10-19
AU2979592A (en) 1993-07-08
CN1029169C (zh) 1995-06-28
AU652707B2 (en) 1994-09-01
CN1074051A (zh) 1993-07-07
NZ245346A (en) 1995-09-26

Similar Documents

Publication Publication Date Title
JPH05242015A (ja) コンピュータシステムと、そのシステムメモリと入力／出力デバイス間の転送データを記憶する方法
US5265211A (en) Arbitration control logic for computer system having dual bus architecture
US5544346A (en) System having a bus interface unit for overriding a normal arbitration scheme after a system resource device has already gained control of a bus
US5644729A (en) Bidirectional data buffer for a bus-to-bus interface unit in a computer system
US5659696A (en) Method and apparatus for determining address location and taking one of two actions depending on the type of read/write data transfer required
JP2988501B2 (ja) パリティエラーを検出するコンピュータシステム及びその動作方法
US5761533A (en) Computer system with varied data transfer speeds between system components and memory
EP1032880B1 (en) Method and apparatus for switching between source-synchronous and common clock data transfer modes in a multiple agent processing system
US5966728A (en) Computer system and method for snooping date writes to cacheable memory locations in an expansion memory device
JPH0727494B2 (ja) キャッシュ・スヌープ／データ無効化機能を有するコンピュータ・システム
JP3420114B2 (ja) データ転送方式
JPH11232180A (ja) データ処理装置
KR100454652B1 (ko) 하이파이버스시스템의주기억장치
WO1991003022A1 (en) Peripheral i/0 bus and programmable bus interface for computerized data acquisition
JPH09185573A (ja) 入出力バスインタフェース制御方式