JPH0523503U - Surge absorber with built-in resistor - Google Patents

Surge absorber with built-in resistor

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Publication number
JPH0523503U
JPH0523503U JP7768591U JP7768591U JPH0523503U JP H0523503 U JPH0523503 U JP H0523503U JP 7768591 U JP7768591 U JP 7768591U JP 7768591 U JP7768591 U JP 7768591U JP H0523503 U JPH0523503 U JP H0523503U
Authority
JP
Japan
Prior art keywords
resistor
varistor
surge absorber
built
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7768591U
Other languages
Japanese (ja)
Inventor
大助 高木
俊紀 天野
清司 坂井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP7768591U priority Critical patent/JPH0523503U/en
Publication of JPH0523503U publication Critical patent/JPH0523503U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】 【目的】 バリスタ素子と抵抗素子を内蔵したサージア
ブソーバにおいて、多数の部品の抵抗体の形成を一度に
行なえ、又、抵抗形成後の抵抗値の調整が容易にでき、
一定の抵抗値を得ることができるサージアブソーバを提
供することを目的とする。 【構成】 内部電極9,10を形成した複数のバリスタ
グリーンシートを圧着焼成した積層体に内部電極9,1
0と導通する外部電極6,8を形成したバリスタ部品5
と、絶縁基板1とからなり、この絶縁基板1の表面に抵
抗体4及びこの抵抗体4の両端部に連なる一対の電極
2,3が形成され、絶縁基板1上の電極2,3と前記バ
リスタ部品5の外部電極6,7とを接続導通させた抵抗
内蔵サージアブソーバである。
(57) [Summary] [Purpose] In a surge absorber with a built-in varistor element and resistance element, the resistors of many parts can be formed at once, and the resistance value after resistance formation can be adjusted easily.
An object of the present invention is to provide a surge absorber capable of obtaining a constant resistance value. [Structure] A plurality of varistor green sheets having internal electrodes 9 and 10 formed thereon are pressure-bonded and fired to form a laminated body, and the internal electrodes 9 and 1 are formed.
Varistor component 5 formed with external electrodes 6 and 8 that conduct with 0
And a pair of electrodes 2 and 3 connected to both ends of the resistor 4 are formed on the surface of the insulating substrate 1. This is a surge absorber with a built-in resistor in which the external electrodes 6 and 7 of the varistor component 5 are electrically connected.

Description

【考案の詳細な説明】[Detailed description of the device]

【0001】[0001]

【産業上の利用分野】[Industrial applications]

この考案は、ラインに侵入する電圧サージと電流サージを吸収除去する抵抗内 蔵サージアブソーバ、更に詳しくは電圧サージを抑制するバリスタ素子と電流サ ージを抑制する抵抗素子を一つのチップ部品で構成したサージアブソーバにおけ る抵抗体の形成に関するものである。 This invention consists of a resistor built-in surge absorber that absorbs and removes voltage surges and current surges that enter the line, and more specifically, a varistor element that suppresses voltage surges and a resistor element that suppresses current surges are composed of a single chip component. It is related to the formation of resistors in the surge absorber.

【0002】[0002]

【従来の技術】[Prior Art]

例えば、ICの入力端子等、外来サージにより素子が破壊しやすい個所のサー ジ保護としては、電圧サージを抑制するバリスタ素子と電流サージを抑制する抵 抗素子を組合せた回路が採用されている。 For example, a circuit combining a varistor element that suppresses a voltage surge and a resistor element that suppresses a current surge is employed as surge protection for a portion where the element is easily destroyed by an external surge, such as an IC input terminal.

【0003】 ところで、バリスタ素子と抵抗素子にそれぞれ別個の部品を用いて回路を構成 すると、プリント基板への実装に手間と時間がかかり、作業コストが高くつき、 スペース的にも広い面積が必要になるため、一つのチップ部品でバリスタ素子と 抵抗素子を構成した抵抗内蔵サージアブソーバが考案されている。By the way, if a circuit is configured by using separate parts for a varistor element and a resistance element, it takes time and labor to mount them on a printed circuit board, the work cost is high, and a large area is required in terms of space. Therefore, a surge absorber with a built-in resistor has been devised, which consists of a varistor element and a resistance element in one chip component.

【0004】 図5に示すチップ状抵抗内蔵サージアブソーバは、内部電極を設けたバリスタ グリーンシートを複数枚積層し、圧着焼成してチップ状の積層体11を形成し、 この積層体11に対して両端部及び中間部の外面に外部電極6,7,8を形成し 、積層体11の上端面の外部電極6,7間に抵抗ペーストを印刷することにより 抵抗体12を形成する。The chip-shaped resistor built-in surge absorber shown in FIG. 5 is obtained by stacking a plurality of varistor green sheets provided with internal electrodes and press-bonding and firing to form a chip-shaped laminated body 11. The external electrodes 6, 7, 8 are formed on the outer surfaces of both ends and the intermediate portion, and the resistor 12 is formed by printing a resistance paste between the external electrodes 6, 7 on the upper end surface of the laminated body 11.

【0005】 両端の外部電極6,7は、抵抗体12と導通し、一方の外部電極6は更にバリ スタ素子を構成する内部電極の一方側と導通すると共に、中間の外部電極8は内 部電極の他方側と導通することになり、複数の内部電極の積層部分でバリスタ素 子が形成され、又、積層体11上に塗布焼付けた抵抗体12で抵抗素子が形成さ れ、これによって一つのチップ状積層体11に、図7の等価回路で示すように、 バリスタ素子Zと抵抗素子Rを備えた抵抗内蔵サージアブソーバが得られること になる。The external electrodes 6 and 7 at both ends are electrically connected to the resistor 12, one external electrode 6 is electrically connected to one side of an internal electrode which constitutes a varistor element, and the intermediate external electrode 8 is an internal part. Conduction is established with the other side of the electrode, a varistor element is formed at the laminated portion of the plurality of internal electrodes, and a resistive element is formed by the resistive element 12 coated and baked on the laminated body 11, whereby a single element is formed. As shown in the equivalent circuit of FIG. 7, a surge absorber with a built-in resistor including a varistor element Z and a resistance element R can be obtained in one chip-shaped laminated body 11.

【0006】 次に、図6に示す抵抗内蔵サージアブソーバは、抵抗素子をチップ状積層体の 内部電極の一部として組込んで一体焼成したものであり、表面に抵抗体13を両 端部に達するように塗布形成したセラミックグリーンシート(バリスタグリーン シートでもよい)を内部電極9,10を塗布形成したバリスタグリーンシートに 付加し、各シートを上下に重ね合わせて積層体11aを形成し、外部電極6,7 ,8を形成すれば、チップ状積層体11aの内部にバリスタ素子Zと抵抗素子R を内蔵した図7で示す等価回路の抵抗内蔵サージアブソーバが得られることにな る。Next, the surge absorber with a built-in resistor shown in FIG. 6 is one in which a resistance element is incorporated as a part of the internal electrode of the chip-shaped laminated body and integrally fired, and the resistor 13 is formed on the surface at both ends. A ceramic green sheet (which may be a varistor green sheet) formed by coating so as to reach is added to the varistor green sheet formed by coating the internal electrodes 9 and 10, and the sheets are vertically stacked to form a laminated body 11a. By forming 6, 7, and 8, it is possible to obtain a resistance built-in surge absorber of the equivalent circuit shown in FIG. 7 in which the varistor element Z and the resistance element R are built in the chip-shaped laminated body 11a.

【0007】[0007]

【考案が解決しようとする課題】[Problems to be solved by the device]

ところで、上記の図5及び図6に示す抵抗内蔵サージアブソーバは、どちらも スクリーン印刷等により抵抗体12,13を形成して抵抗素子を得ているため、 抵抗素子の抵抗値はこの抵抗体12,13の厚みや形状により左右される。 By the way, in the above surge absorbers with built-in resistors shown in FIGS. 5 and 6, the resistance elements 12 and 13 are formed by screen printing or the like to obtain resistance elements. Therefore, the resistance value of the resistance element is , 13 depending on the thickness and shape.

【0008】 そのため、製品の抵抗値を安定して供給するには、抵抗体の形成時における膜 の厚み、はみ出し、焼成時の抵抗体界面でのにじみ等を制御しなくてはならず、 その管理が非常に困難である。Therefore, in order to stably supply the resistance value of the product, it is necessary to control the thickness of the film during the formation of the resistor, the protrusion, the bleeding at the resistor interface during firing, and the like. Very difficult to manage.

【0009】 更に、抵抗体を形成すべきチップバリスタの積層体は非常に小さく、この素子 に直接印刷するという作業は非常に困難である。Further, the laminated body of the chip varistor for forming the resistor is very small, and the work of directly printing on this element is very difficult.

【0010】 この考案は上記のような課題を解決するためになされたものであり、多数の部 品の抵抗体の形成が一度にでき、又、抵抗体形成後の抵抗値の調整が容易にでき 、一定の抵抗値を得ることができる抵抗内蔵サージアブソーバを提供することを 目的とする。The present invention has been made to solve the above problems, and resistors of a large number of components can be formed at one time, and the resistance value can be easily adjusted after the resistors are formed. It is an object of the present invention to provide a surge absorber with a built-in resistor that can obtain a constant resistance value.

【0011】[0011]

【課題を解決するための手段】[Means for Solving the Problems]

上記のような課題を解決するため、この考案は、内部電極を形成した複数のバ リスタグリーンシートを圧着焼成した積層体に内部電極と導通する外部電極を形 成したバリスタ部品と、表面に抵抗体及びこの抵抗体の両端部に連なる一対の電 極が形成された絶縁基板とからなり、この絶縁基板上の電極と前記バリスタ部品 の外部電極とを接続導通させた抵抗内蔵サージアブソーバである。 In order to solve the above problems, the present invention proposes a varistor component that forms an external electrode that is electrically connected to the internal electrode in a laminated body obtained by pressure-bonding and firing a plurality of varistor green sheets having internal electrodes, and a resistor on the surface. A surge absorber with a built-in resistor, which is composed of a body and an insulating substrate on which a pair of electrodes connected to both ends of the resistor is formed, and which connects and conducts an electrode on the insulating substrate and an external electrode of the varistor component.

【0012】[0012]

【作用】[Action]

抵抗体は、バリスタ部品とは別の絶縁基板面上に形成されており、この抵抗体 に連なる電極とバリスタ部品の外部電極が導通して抵抗素子とバリスタ素子を内 蔵したサージアブソーバを構成しているので、抵抗体の形成がバリスタ部品とは 別の絶縁基板上で行なえ、抵抗の形成が容易であり、又、抵抗形成後の抵抗値の チェック、修正が早くかつ、容易に行なうことができる。 The resistor is formed on the surface of the insulating substrate that is different from the varistor component, and the electrode connected to this resistor and the external electrode of the varistor component are electrically connected to form a surge absorber containing the resistor and varistor components. Therefore, the resistor can be formed on an insulating substrate that is different from the varistor part, and the resistor can be easily formed.In addition, the resistance value can be checked and corrected after the resistor is formed quickly and easily. it can.

【0013】[0013]

【実施例】【Example】

以下、この考案の実施例を添付図面の図1乃至図4に基づいて説明する。尚、 従来例と同一の部分は同一の符号を付して説明する。 Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1 to 4 of the accompanying drawings. The same parts as those in the conventional example will be described with the same reference numerals.

【0014】 図1において、1はアルミナからなる絶縁基板であり、部品ごとにカッティン グする前の母基板の状態にある。この絶縁基板上に1対の電極2,3を複数組印 刷、焼付け等の手段により全面に並べて形成し、さらにこの電極2,3の両方に 達する抵抗体4を、同じく印刷、焼付け等の手段によって形成する。In FIG. 1, reference numeral 1 denotes an insulating substrate made of alumina, which is in a state of a mother substrate before cutting each component. A plurality of pairs of electrodes 2 and 3 are formed on the insulating substrate side by side by means of printing, baking or the like, and the resistor 4 reaching both of the electrodes 2 and 3 is also formed by printing or baking. Formed by means.

【0015】 その後、絶縁基板1上で、抵抗体4に対し、レーザートリミングにより電極の 形状を整えて抵抗値を調整し、一定の抵抗値が得られるようにする。After that, on the insulating substrate 1, the shape of the electrode of the resistor 4 is adjusted by laser trimming to adjust the resistance value so that a constant resistance value can be obtained.

【0016】 次に、チップバリスタ5を図2に示すように、絶縁基板1上にマウントする。 チップバリスタ5は内部電極を形成したバリスタグリーンシートを複数枚積層し たものを圧着焼成して形成され、内部電極と導通する外部電極6,8と内部電極 と導通しない外部電極7を有する。この場合、チップバリスタ5の外部電極6, 7をそれぞれ絶縁基板1上の電極2,3と接続するように配置する。Next, the chip varistor 5 is mounted on the insulating substrate 1 as shown in FIG. The chip varistor 5 is formed by pressure-bonding and firing a plurality of laminated varistor green sheets having internal electrodes formed thereon, and has external electrodes 6 and 8 that are electrically connected to the internal electrodes and external electrodes 7 that are not electrically connected to the internal electrodes. In this case, the external electrodes 6 and 7 of the chip varistor 5 are arranged so as to be connected to the electrodes 2 and 3 on the insulating substrate 1, respectively.

【0017】 マウントの方法としては、先に絶縁基板1上の抵抗体4上に接着剤を塗布し、 チップバリスタ5を接着した後、フロー半田付けを行ない、チップバリスタ5の 外部電極6,7と絶縁基板1上の電極2,3とを半田付けすればよい。As a mounting method, an adhesive is first applied to the resistor 4 on the insulating substrate 1 and the chip varistor 5 is adhered thereto, and then flow soldering is performed to form the external electrodes 6, 7 of the chip varistor 5. The electrodes 2 and 3 on the insulating substrate 1 may be soldered.

【0018】 又、別の方法としては、絶縁基板1上にチップバリスタ5を配置した後、リフ ロー半田付けにて各電極を半田付けしてもよい。As another method, after arranging the chip varistor 5 on the insulating substrate 1, each electrode may be soldered by reflow soldering.

【0019】 絶縁基板1上にチップバリスタ5を接続した後、各チップバリスタ5ごとに絶 縁基板1の母基板を分割し、図3に示すようなチップバリスタ5と、抵抗体4を 有する絶縁基板1とを重ね合わせて構成した抵抗内蔵サージアブソーバ部品を得 る。After connecting the chip varistor 5 on the insulating substrate 1, the mother substrate of the insulating substrate 1 is divided for each chip varistor 5, and the insulation having the chip varistor 5 and the resistor 4 as shown in FIG. A surge absorber component with a built-in resistor is obtained by stacking it with the board 1.

【0020】 図4はこの抵抗内蔵サージアブソーバの断面図であり、チップバリスタ5は、 端部に達する内部電極9を形成したバリスタグリーンシートと、両側部に達する 内部電極10を形成したバリスタグリーンシートを複数枚積層して構成されてお り、チップバリスタ5の一方の内部電極9と導通する外部電極6は、絶縁基板1 の電極2と接続導通している。他方の内部電極10は外部電極8と導通する。又 、外部電極7は、絶縁基板1の電極3と接続導通している。FIG. 4 is a cross-sectional view of the surge absorber with a built-in resistor. The chip varistor 5 includes a varistor green sheet having internal electrodes 9 reaching the ends and a varistor green sheet having internal electrodes 10 reaching both sides. An external electrode 6 which is electrically connected to one of the internal electrodes 9 of the chip varistor 5 is connected and electrically connected to the electrode 2 of the insulating substrate 1. The other inner electrode 10 is electrically connected to the outer electrode 8. Further, the external electrode 7 is electrically connected to the electrode 3 of the insulating substrate 1.

【0021】 こうしてこの考案に係る抵抗内蔵サージアブソーバは、図7に示す等価回路を 形成することになる。尚、外部電極6はサージ入力側につながれ、外部電極7は サージから保護すべきIC等とつながれ、8はアース端子となり、電源側から侵 入する電圧サージをバリスタ素子Zで抑制し、電流サージは抵抗素子Rで抑制す る。The surge absorber with a built-in resistor according to the present invention thus forms an equivalent circuit shown in FIG. The external electrode 6 is connected to the surge input side, the external electrode 7 is connected to an IC or the like to be protected from the surge, and 8 serves as a ground terminal. The voltage surge invading from the power supply side is suppressed by the varistor element Z, and the current surge is suppressed. Is suppressed by the resistance element R.

【0022】 尚、この考案に係る抵抗内蔵サージアブソーバは上記の実施例のものに限定さ れず、チップバリスタの内部電極の積層数およびシート数等、適宜変形して実施 することができる。The surge absorber with a built-in resistor according to the present invention is not limited to the one in the above embodiment, but may be implemented by appropriately modifying the number of laminated internal electrodes and the number of sheets of the chip varistor.

【0023】[0023]

【考案の効果】[Effect of the device]

以上のように、この考案によると、抵抗内蔵サージアブソーバの抵抗体がチッ プバリスタの外部電極と接続される絶縁基板上に形成されているので、抵抗体の 形成が絶縁基板上で行なえ、チップバリスタの形成とは別の工程で行なえるため 、作成が短期間で済む。又、絶縁基板上でレーザートリミング等の手段により、 抵抗体の形状を調整でき、容易に一定の抵抗値を得ることができる。 As described above, according to the present invention, the resistor of the surge absorber with a built-in resistor is formed on the insulating substrate that is connected to the external electrode of the chip varistor, so that the resistor can be formed on the insulating substrate and the chip varistor It can be created in a short period because it can be performed in a process different from the process of forming. Further, the shape of the resistor can be adjusted on the insulating substrate by means such as laser trimming, and a constant resistance value can be easily obtained.

【0024】 更に、実施例の如く、母基板状態の絶縁基板上に抵抗体を複数個同時に作成し ておけば、抵抗の形成、調整、及びチップバリスタとの半田付けも一括してする ことができるので、分割前における作業性が向上するという効果もある。Further, if a plurality of resistors are simultaneously formed on the insulating substrate in the mother substrate state as in the embodiment, it is possible to collectively perform resistance formation, adjustment, and soldering with the chip varistor. Therefore, there is also an effect that workability before the division is improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】絶縁基板上に抵抗体を形成した斜視図である。FIG. 1 is a perspective view of a resistor formed on an insulating substrate.

【図2】絶縁基板上にチップバリスタを配置した斜視図
である。
FIG. 2 is a perspective view in which a chip varistor is arranged on an insulating substrate.

【図3】この考案に係るサージアブソーバの斜視図であ
る。
FIG. 3 is a perspective view of a surge absorber according to the present invention.

【図4】この考案に係るサージアブソーバの断面図であ
る。
FIG. 4 is a sectional view of a surge absorber according to the present invention.

【図5】従来のサージアブソーバの斜視図である。FIG. 5 is a perspective view of a conventional surge absorber.

【図6】従来のサージアブソーバの他の例の断面図であ
る。
FIG. 6 is a cross-sectional view of another example of a conventional surge absorber.

【図7】抵抗内蔵サージアブソーバの回路図である。FIG. 7 is a circuit diagram of a surge absorber with a built-in resistor.

【符号の説明】[Explanation of symbols]

1 絶縁基板 2,3 電極 4 抵抗体 5 チップバリスタ 6,7,8 外部電極 9,10 内部電極 1 Insulating substrate 2,3 Electrode 4 Resistor 5 Chip varistor 6,7,8 External electrode 9,10 Internal electrode

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】 内部電極を形成した複数のバリスタグリ
ーンシートを圧着焼成した積層体に内部電極と導通する
外部電極を形成したバリスタ部品と、表面に抵抗体及び
この抵抗体の両端部に連なる一対の電極が形成された絶
縁基板とからなり、この絶縁基板上の電極と前記バリス
タ部品の外部電極とが接続導通している抵抗内蔵サージ
アブソーバ。
1. A varistor component in which an external electrode is formed on a laminated body obtained by pressure-bonding and firing a plurality of varistor green sheets having internal electrodes formed thereon, a resistor on the surface, and a pair connected to both ends of the resistor. A surge absorber with a built-in resistor in which the electrodes on the insulating substrate are connected to the external electrodes of the varistor component for electrical connection.
JP7768591U 1991-08-30 1991-08-30 Surge absorber with built-in resistor Pending JPH0523503U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7768591U JPH0523503U (en) 1991-08-30 1991-08-30 Surge absorber with built-in resistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7768591U JPH0523503U (en) 1991-08-30 1991-08-30 Surge absorber with built-in resistor

Publications (1)

Publication Number Publication Date
JPH0523503U true JPH0523503U (en) 1993-03-26

Family

ID=13640755

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7768591U Pending JPH0523503U (en) 1991-08-30 1991-08-30 Surge absorber with built-in resistor

Country Status (1)

Country Link
JP (1) JPH0523503U (en)

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