JPH05226467A - Chip dividing method of semiconductor wafer - Google Patents
Chip dividing method of semiconductor waferInfo
- Publication number
- JPH05226467A JPH05226467A JP1264792A JP1264792A JPH05226467A JP H05226467 A JPH05226467 A JP H05226467A JP 1264792 A JP1264792 A JP 1264792A JP 1264792 A JP1264792 A JP 1264792A JP H05226467 A JPH05226467 A JP H05226467A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor wafer
- dicing
- adhesive tape
- chips
- dividing method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Dicing (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体ウェハーのチッ
プ分割方法に関し、特にエアーブリッジ配線を有する半
導体装置を含む半導体ウェハーに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for dividing a semiconductor wafer into chips, and more particularly to a semiconductor wafer including a semiconductor device having air bridge wiring.
【0002】[0002]
【従来の技術】従来の半導体ウェハーのチップ分割方法
は、図3(a)に示すように半導体ウェハー1を粘着性
テープ2に張付け、次に図3(b)に示すようにダイシ
ング装置により半導体ウェハー1をハーフカット状態に
し保護テープ3をはる。次に図3(c)のようなローラ
6で半導体ウェハー1を挾みながらブレーキングをおこ
なって図3(e)に示すように粘着性テープ2を引き伸
ばしてチップ7の分割をおこなっている。また、第二の
分割方法としては、図4(a)に示すように半導体ウェ
ハー1を粘着性テープ2に張付け、次に図4(b)に示
すようにダイシング装置により半導体ウェハー1をハー
フカット状態にし保護テープ3をはる。次に図4(c)
のような針状治具4により粘着性テープ2の裏側より擦
ることによりブレイキングをおこなって粘着性テープ2
を引きのばしてチップ7の分割をおこなっている。2. Description of the Related Art In the conventional chip dividing method for a semiconductor wafer, a semiconductor wafer 1 is attached to an adhesive tape 2 as shown in FIG. 3 (a), and then a semiconductor is cut by a dicing device as shown in FIG. 3 (b). The wafer 1 is put into a half-cut state and the protective tape 3 is attached. Next, the semiconductor wafer 1 is sandwiched by rollers 6 as shown in FIG. 3C, and the adhesive tape 2 is extended to divide the chip 7 as shown in FIG. 3E. As a second dividing method, the semiconductor wafer 1 is attached to the adhesive tape 2 as shown in FIG. 4 (a), and then the semiconductor wafer 1 is half-cut by a dicing device as shown in FIG. 4 (b). And put the protective tape 3 on. Next, FIG. 4 (c)
The adhesive tape 2 is broken by rubbing it from the back side of the adhesive tape 2 with a needle jig 4 such as
Is extended to divide the chip 7.
【0003】[0003]
【発明が解決しようとする課題】上述した従来の半導体
ウェハーのチップ分割方法において、エアーブリッジ配
線を有する半導体装置の半導体ウェハーをダイシング装
置を用いてハーフカット状態にした後、ローラで挾みブ
レーキングを行う際に、エアーブリッジ配線を潰した
り、壊したりして歩留を落とすという問題点がある。ま
た、第二の分割方法においては、ブレーキングを行う際
にチップの汚れ、カケ、キズにより外観不良が歩留を落
とす問題点がある。In the conventional method of dividing a semiconductor wafer into chips described above, a semiconductor wafer of a semiconductor device having an air bridge wiring is half-cut using a dicing device and then sandwiched by a roller for braking. However, there is a problem that the yield is reduced by crushing or destroying the air bridge wiring. Further, in the second division method, there is a problem in that a defective appearance causes a drop in yield due to dirt, chips, and scratches on the chip during braking.
【0004】[0004]
【課題を解決するための手段】本発明の半導体ウェハー
のチップ分割方法は、半導体ウェハーを粘着性テープに
張り付ける工程と、半導体ウェハーをセミフルカット状
態にダイシングする工程と、針状の治具を少なくとも一
つ以上用いて連続的に半導体ウェハーのダイシング跡を
裏側から突き上げブレーキングする工程と、粘着性テー
プを引き伸ばす工程とを有する。A method of dividing a semiconductor wafer into chips according to the present invention comprises a step of attaching a semiconductor wafer to an adhesive tape, a step of dicing the semiconductor wafer into a semi-full cut state, and a needle-shaped jig. The method includes a step of continuously pushing up the dicing trace of the semiconductor wafer from the back side by using at least one or more and braking, and a step of stretching the adhesive tape.
【0005】[0005]
【実施例】次に本発明について図面を参照して説明す
る。図1は、本発明の第1の実施例の半導体ウェハーの
チップ分割方法を示す工程図である。図1(a)に示す
ように半導体ウェハー1を粘着性テープ2に張り付け
る。次に、図1(b)に示すようにダイシング装置によ
り半導体ウェハー1をセミフルカット状態にカッティン
グし、保護テーブ3をはる。つぎに図1(c)に示すよ
うに連続的に並んでいる針状治具4を用いて、図1
(g)に示すような経路で順次、半導体ウェハー1の裏
側からダイシング跡5’を針状治具4で連続的に突き上
げることによりブレーキングを行い、同様に図1(d)
に示す工程で図1(h)に示すように直交する方向に針
状治具4でブレーキングを行い、次に図1(f)に示す
ように粘着性テープ2を引き伸ばし、チップ7を分割す
る。本実施例によりブレーキングによる外観不良を12
%程度低減することができた。The present invention will be described below with reference to the drawings. FIG. 1 is a process drawing showing a method of dividing a semiconductor wafer into chips according to a first embodiment of the present invention. The semiconductor wafer 1 is attached to the adhesive tape 2 as shown in FIG. Next, as shown in FIG. 1B, the semiconductor wafer 1 is cut into a semi-full cut state by a dicing device, and the protective tape 3 is attached. Next, as shown in FIG. 1C, the needle jigs 4 arranged continuously are used to
Braking is performed by successively pushing up the dicing marks 5'from the back side of the semiconductor wafer 1 with the needle jig 4 in the route as shown in FIG.
In the step shown in FIG. 1B, braking is performed in the direction orthogonal to the needle jig 4 as shown in FIG. 1H, and then the adhesive tape 2 is stretched as shown in FIG. To do. According to this embodiment, the appearance defect due to braking is 12
It was possible to reduce by about%.
【0006】図2は、本発明の第2の実施例の半導体ウ
ェハーのチップ分割方法を示す工程図である。図2
(a)に示すように半導体ウェハー1を粘着性テープ2
に張り付ける。次に図2(b)に示すようにダイシング
装置により半導体ウェハー1をセミフルカット状態にカ
ッティングし保護テープ3をはる。つぎに図2(c)に
示すように連続的に並んでいる針状治具4を用いて、図
2(g),(h)に示すような経路で半導体ウェハー1
の裏側からダイシング跡5’を針状治具4を直線状に連
動させてオリエンテーション・フラットに平行方向及び
垂直方向につき上げることによりブレーキングを行い、
次に図2(f)に示すように粘着性テープ2を引き伸ば
し、チップ7を分割する。本実施例によりブレーキング
による外観不良を12%程度低減することができた。FIG. 2 is a process diagram showing a method of dividing a semiconductor wafer into chips according to a second embodiment of the present invention. Figure 2
As shown in (a), the semiconductor wafer 1 is attached to the adhesive tape 2
Stick to. Next, as shown in FIG. 2B, the semiconductor wafer 1 is cut into a semi-full cut state by a dicing device, and the protective tape 3 is attached. Next, using the needle jigs 4 that are continuously arranged as shown in FIG. 2C, the semiconductor wafer 1 is routed as shown in FIGS. 2G and 2H.
Braking is performed by raising the dicing trace 5'from the back side of the needle by moving the needle jig 4 linearly and raising it in the parallel and vertical directions to the orientation flat.
Next, as shown in FIG. 2F, the adhesive tape 2 is stretched to divide the chip 7. According to this example, the appearance defect due to braking could be reduced by about 12%.
【0007】[0007]
【発明の効果】以上、説明したように本発明によれば、
エアーブリッジ配線を有する半導体装置のブレーキング
の際のエアーブリッジ配線の潰れおよび壊れをなくすこ
とができて、ブレーシングによる外観不良を低減するこ
とができるという効果がある。As described above, according to the present invention,
It is possible to prevent the air bridge wiring from being crushed and broken during braking of the semiconductor device having the air bridge wiring, and to reduce appearance defects due to bracing.
【図1】本発明の第1の実施例のチップ分割方法を示す
工程図(a)〜(h)である。FIG. 1 is a process diagram (a) to (h) showing a chip dividing method according to a first embodiment of the present invention.
【図2】本発明の第2の実施例のチップ分割方法を示す
工程図(a)〜(h)である。FIG. 2 is a process diagram (a) to (h) showing a chip dividing method according to a second embodiment of the present invention.
【図3】従来のチップ分割方法を示す工程図(a)〜
(e)である。FIG. 3 is a process diagram (a) showing a conventional chip dividing method.
(E).
【図4】従来の他のチップ分割方法を示す工程図(a)
〜(e)である。FIG. 4 is a process diagram (a) showing another conventional chip dividing method.
~ (E).
1 半導体ウェハー 2 粘着性テープ 3 保護テープ 4 針状治具 5 ダイシング跡 5’ ダイシング跡(裏面) 6 ローラ 7 チップ 1 Semiconductor Wafer 2 Adhesive Tape 3 Protective Tape 4 Needle Jig 5 Dicing Trace 5'Dicing Trace (Back) 6 Roller 7 Chip
Claims (1)
ける工程と、該半導体ウェハーをセミフルカット状態に
ダイシングする工程と、針状治具を少なくとも一つ以上
用いて連続的に該半導体ウェハーのダイシング跡を裏側
から突き上げブレーキングする工程と、粘着性テープを
引き伸ばす工程とを有する半導体ウェハーのチップ分割
方法。1. A step of attaching a semiconductor wafer to an adhesive tape, a step of dicing the semiconductor wafer into a semi-full cut state, and a dicing trace of the semiconductor wafer continuously using at least one or more needle jigs. A method of dividing a semiconductor wafer into chips, which comprises a step of pushing up the substrate from the back side and braking, and a step of stretching the adhesive tape.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1264792A JPH05226467A (en) | 1992-01-28 | 1992-01-28 | Chip dividing method of semiconductor wafer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1264792A JPH05226467A (en) | 1992-01-28 | 1992-01-28 | Chip dividing method of semiconductor wafer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05226467A true JPH05226467A (en) | 1993-09-03 |
Family
ID=11811161
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1264792A Withdrawn JPH05226467A (en) | 1992-01-28 | 1992-01-28 | Chip dividing method of semiconductor wafer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05226467A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2749794A1 (en) * | 1996-06-13 | 1997-12-19 | Charil Josette | Semiconductor slab sample cutting tool for laser manufacture |
KR19990017672A (en) * | 1997-08-25 | 1999-03-15 | 윤종용 | Semiconductor chip package manufacturing method |
US7888237B2 (en) | 2007-11-05 | 2011-02-15 | Samsung Electronics Co., Ltd | Method of cutting semiconductor wafer, semiconductor chip apparatus, and chamber to cut wafer |
-
1992
- 1992-01-28 JP JP1264792A patent/JPH05226467A/en not_active Withdrawn
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2749794A1 (en) * | 1996-06-13 | 1997-12-19 | Charil Josette | Semiconductor slab sample cutting tool for laser manufacture |
KR19990017672A (en) * | 1997-08-25 | 1999-03-15 | 윤종용 | Semiconductor chip package manufacturing method |
US7888237B2 (en) | 2007-11-05 | 2011-02-15 | Samsung Electronics Co., Ltd | Method of cutting semiconductor wafer, semiconductor chip apparatus, and chamber to cut wafer |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990408 |