JPH05226363A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a manufacturing method by which a thin film transistor having an offset structure can be easily manufactured when a large-sized substrate is used. CONSTITUTION:The offset structure of a thin film transistor is formed by selectively forming an insulting film 105 on gate wiring 104 only. Therefore, a thin film transistor having a high on/off ratio can be formed without using any complicated process when a large-sized substrate is used. In addition, all processes can be carried out at 450 deg.C and a low-cost substrate can be utilized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a semiconductor device on an insulating amorphous material and its manufacturing method.

[0002]

2. Description of the Related Art Recently, large-sized, high-resolution liquid crystal display panels, high-speed, high-resolution contact-type image sensors, and three-dimensional ICs.
In order to meet such needs, there is a demand for a technique for forming a high-performance semiconductor element on an insulating amorphous substrate such as glass or quartz or an insulating amorphous material such as SiO 2.

As such a semiconductor device using amorphous silicon or polycrystalline silicon as an element material, good results have been obtained in terms of variations in characteristics of each device and yield. In particular, the one using polycrystalline silicon as the element material has a relatively high movement due to the technique of melting and recrystallization by laser light and the technique of solid phase growing amorphous silicon to form a polycrystalline silicon film of large grain size. A device having a certain degree can be manufactured relatively easily. Therefore, L
It has become possible to be applied as a switching element or a driving element of a CD or an image sensor.

[0004]

However, in recent years, due to the high definition of liquid crystal panels and the application to SRAM, there has been a demand for an element which has not only an on-current but also an off-leakage and a higher breakdown voltage. There is.

An LDD (lightly doped drain) structure is known as a structure for realizing such characteristics as a MOS transistor. This structure is usually formed by a method of implanting low-concentration impurity ions after forming the gate electrode, forming sidewalls around the gate electrode, and again implanting high-concentration impurity ions. It is a thing.

In the process of manufacturing the LDD structure as described above, the length of the low-concentration drain region depends directly on the width of the side wall, and in order to uniformly form the side wall, it is very difficult to form the side wall over the entire substrate. Uniform etching is required. However, in application to a liquid crystal panel or the like, it is necessary to fabricate an element on a large substrate of, for example, 20 cm square, and it is very difficult to perform uniform etching on such a whole substrate. Further, since the substrate is an insulator, damage due to etch back is likely to occur. In order to form a more uniform side wall, it is necessary to perform a heat treatment at a relatively high temperature after forming the SiO2 film, which is the material thereof, which is also not preferable when using a large substrate.

Therefore, for use in such a field, after performing low-concentration ion implantation, a resist is formed on a portion to be left as a low-concentration region, and then high-concentration impurity ion implantation is performed. The process of doing so is being considered. However, in such a process, since the above-mentioned resist formation is performed completely separately from the step of forming the gate electrode, the accuracy of the alignment becomes a problem. Especially when a large substrate is used, it is often difficult to perform alignment with high accuracy on the entire substrate due to subtle deformation or warpage of the substrate due to heat treatment or the like.

As described above, there is a demand for a process capable of easily manufacturing a thin film transistor having an offset structure or an LDD structure on a large substrate.

Therefore, the present invention is to solve such a problem, and an object thereof is to form a thin film transistor having an offset structure or an LDD structure on a large-sized substrate by a simple process.

[0010]

According to a method of manufacturing a semiconductor device of the present invention, 1) a semiconductor device in which a channel region of an insulated gate semiconductor device is formed of a semiconductor mainly composed of silicon, silicon containing a channel region is used. Source / drain formed on at least a part of the polycrystalline semiconductor layer mainly containing silicon, including a polycrystalline semiconductor layer doped with impurities such as boron, a gate insulating film, a gate electrode, and the channel region At least a thin film forming a region is provided.

2) A method of manufacturing an insulated gate semiconductor device is characterized by including a step of selectively forming an insulating film on a gate electrode.

3) The semiconductor according to claim 1, wherein in the step of forming the thin film forming the source / drain regions, the thin film is selectively formed under the condition that the thin film is not formed at least on the insulator. Device manufacturing method.

[0013]

FIG. 1 is a process sectional view showing an example of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 1A shows a step of forming a polycrystalline silicon layer 102, a gate insulating film 103 and a gate wiring layer 104 on an insulating substrate 101.

As the insulating substrate 101, there is used a borosilicate glass (Corning 7059) substrate having a SiO2 layer formed on the surface by sputtering.

As a method of forming the polycrystalline silicon layer 102, a plasma CVD method (PCVD method) is used, and a film is formed at a substrate temperature of 400 ° C. to a film thickness of about 400 Å.
Monosilane (SiH4) was used as a reaction gas, and the film was formed by diluting it with hydrogen to 1%. Raw gas 0.5 ~
By diluting with hydrogen in the range of 4% to form a film, 450 ° C
It is possible to form a polycrystalline silicon film at the following temperature. It is possible to form a film of polycrystalline silicon up to a substrate temperature of about 200 ° C., but it is desirable to set it to 300 ° C. or higher in order to obtain good film quality. Disilane (Si2H4) may be used as the source gas. In addition to silane, disilane, and hydrogen as a raw material gas, an appropriate amount of a reaction gas containing an element such as fluorine (F) or chlorine (Cl) is mixed to form polycrystalline silicon at a faster film forming rate. A film can be formed and the film formation time can be shortened. As an example of film forming conditions, as reaction gases, monosilane, dichlorosilane (SiH2Cl2),
Hydrogen is used, and the mixing ratio is, for example, silane: dichlorosilane = 1: 20 to 1: 200, silane: hydrogen = 1: 10.
In the range of 0 to 1: 1000, the substrate temperature is 300 ° C to 4
When the temperature is about 50 ° C., good results are obtained. It is desirable that the film thickness of the polycrystalline silicon be 500 Å or less in order to reduce the off current of the formed thin film transistor and cause Vth (threshold voltage) to occur. Especially 50-350
Good characteristics can be obtained in the range of Å.

After forming a pattern on the polycrystalline silicon layer, a gate insulating film 102 is formed. Gate insulating film 10
As a method of forming No. 3, a magnetron sputtering method using SiO 2 as a target is used, and the substrate temperature is set to 300 ° C. in an argon atmosphere added with 10% oxygen.
The film is formed with a film thickness of about 00Å. The amount of oxygen added to argon is appropriately 3 to 20%, and in the range of 5 to 15%, a gate film having a low interface state density and a high breakdown voltage can be formed. Further, if the partial pressure of oxygen is increased at the initial stage of film formation to 15 to 50%, it is possible to form a gate film having a lower interface state density. It is possible to form a gate film having a high breakdown voltage when the substrate temperature is higher to some extent, but when the temperature exceeds 400 ° C., the characteristics of the manufactured element are significantly deteriorated, so the temperature is set to 250 to 350 ° C. Is appropriate. However, the gate insulating film may be formed at a substrate temperature of 400 to 450 ° C. on the assumption that plasma treatment is performed in an atmosphere containing hydrogen in the step after forming the interlayer insulating film.

After forming the gate insulating film 103, a gate wiring layer 104 is formed. A plasma CVD method is used as a method for forming the gate wiring layer, and the substrate temperature is 350 ° C.
Therefore, the film is formed to a film thickness of about 4000Å. Monosilane is used as the reaction gas, and the film is formed by diluting it with hydrogen to 1%. Further, here, as a doping gas, hydrogen-based phosphine (PH3) having a concentration of 2000 ppm is added by about 1/3 of the flow rate of monosilane,
The film is being formed. Similar to the case of forming the polycrystalline silicon 102, the film formation rate can be increased by performing the film formation under the condition that an appropriate amount of a reaction gas containing fluorine or chlorine is added.

FIG. 1B shows a step of selectively forming an insulating film on the gate wiring layer. 1 in the figure
Reference numeral 05 is an insulating film selectively formed on the gate wiring layer. The insulating film 105 is an amorphous silicon nitride film (Si2N3: H) formed by the plasma CVD method, and the substrate temperature is 3
A film of about 4000 Å is formed at 50 ° C. As the reaction gas, monosilane and ammonia (NH3) are used, and the film is formed by diluting with hydrogen to 3%. By forming a film by diluting the source gas concentration with hydrogen in the range of 0.5 to 7%, the film can be formed selectively only on the gate wiring layer 105. It is possible to perform such film formation at a substrate temperature in the range of 200 to 400 ° C., but it is desirable to set it to 350 ° C. or higher in order to obtain good film quality. Dichlorosilane was used as a reaction gas at a flow rate of 1:10 with respect to the silane flow rate.
By adding about 1:20, the amorphous silicon nitride film can be selectively formed in a wider range. Such selective formation of an amorphous silicon nitride film can be performed not only when using polycrystalline silicon as the gate wiring layer 105 but also when using a metal such as titanium (Ti) or aluminum (Al). It is possible. In addition to SiO2, PSG or BPSG can be used as a base for selective film formation. When BPSG is used, a silicon nitride film is selectively formed under the widest range of conditions. It is possible. Further, performing plasma treatment in an atmosphere containing argon or nitrogen before film formation is effective for stable and selective film formation.

FIG. 1C shows a step of removing the gate insulating film except the lower portion of the gate wiring 104 and the insulating film 105 formed on the gate wiring, and further removing the insulating film 105. ..

The gate insulating film is removed by wet etching with hydrofluoric acid. If the dimensional accuracy of the source and drain offset regions is required, dry etching may be used. In that case, since the insulating film 105 is thicker than the gate insulating film 103, it is not always necessary to perform selective etching with respect to the silicon oxide film and the silicon nitride film, and there is selectivity between silicon and silicon oxide. The conditions are sufficient.

The insulating film 105 is removed by wet etching with hot phosphoric acid.

FIG. 1D shows a step of forming a portion of the polycrystalline silicon layer 102 from which the gate insulating film is removed and a silicon layer 106 selectively doped with impurities on the gate wiring.

As a method for forming the impurity-doped silicon layer 106, a plasma CVD method was used, and a 500 Å film was formed at a substrate temperature of 300 ° C. Monosilane, dichlorosilane, and hydrogen were used as the reaction gas, and the mixing ratio was silane, dichlorosilane, and hydrogen = 1: 30: 200.
Was formed as. As the doping gas, hydrogen-based phosphine having a concentration of 2000 ppm is used, and is added about 1/3 of the silane flow rate. A silicon layer in which impurities are selectively doped can be formed on silicon in a flow ratio of silane and dichlorosilane = 1: 20 to 1: 200 and a flow ratio of silane and hydrogen is 1:50 to 1: 300. In addition to phosphine, diborane (B2H6), arsine (AsH3), or the like can be used as the doping gas. In order to stably form an impurity-doped polycrystalline silicon film only on polycrystalline silicon, it is also effective to perform cleaning with ammonia hydrogen peroxide or plasma treatment in an atmosphere containing hydrogen before forming the film. ..

Since the gate insulating film is left not only directly under the gate wiring 104 but also in the peripheral portion, the gate wiring and the source are selectively formed only on silicon.
The drain region is not short-circuited, and by adjusting the size of this region, an offset region can be provided between the gate wiring and the source / drain region.
Thus, the off-state current of the manufactured thin film transistor can be reduced. The size of the offset region can be controlled independently of the thickness of the gate wiring layer by changing the thickness of the insulating film 105. In order to manufacture a thin film transistor having a high on / off ratio, 100
It is desirable to set 0 to 5000Å, and especially 1300 to
Good results can be obtained with 2500Å. However, when anisotropic dry etching is used for etching the gate insulating film 103, a better result is obtained by setting it to 300 to 1500 Å.

FIG. 1E shows a completed state of the thin film transistor. After forming a silicon layer doped with impurities, an interlayer insulating film 107 is formed, a contact hole is formed, and then an aluminum wiring layer 108 is formed.

As a method for forming the interlayer insulating film 107, a sputtering method using silicon oxide as a target is used, and 4000 Å is formed at a substrate temperature of 280 ° C. Cleaning with ammonia-hydrogen peroxide mixture and light etching with hydrofluoric acid before film formation are effective in improving the yield. Further, by performing plasma treatment in an atmosphere containing hydrogen after forming the interlayer insulating film 107, characteristics of the manufactured thin film transistor can be improved. In the case of performing the above plasma treatment, it is desirable to perform annealing at a temperature of about 300 to 350 ° C. in order to suppress variations in the threshold voltage and the like of the manufactured thin film transistors.

A normal photo-etching process is used to form the contact hole, and silicon is used to form the aluminum wiring.
A sputtering method using an aluminum-silicon-copper target containing approximately 5% is used. After forming the aluminum wiring 108, annealing is performed at 250 to 300 ° C. to reduce variations in the characteristics of the manufactured thin film transistors.

In this embodiment, all steps are performed at 400 ° C.
It can be performed below (450 ° C. or lower depending on conditions), and many kinds of materials can be selected for the substrate 101. Of course, it is also effective when using highly heat resistant glass, quartz glass, or a silicon substrate having higher heat resistance.

FIG. 2 is a process sectional view showing another example of the method of manufacturing a semiconductor device according to the embodiment of the present invention.

FIG. 2A shows a step of forming a polycrystalline silicon layer 202, a gate insulating film 203 and a gate wiring layer 204 on a quartz substrate 201.

As a method of forming the polycrystalline silicon layer 202, the LPCVD method (low pressure CVD method) is used, and the film is formed at a set temperature of 590 ° C. to about 1200 Å. Monosilane is used as the source gas. As a method for forming a polycrystalline silicon film, a plasma CVD method using monosilane as a source gas, an LPCVD method at a low temperature of 520 to 540 ° C., and an LPCVD method using disilane at a lower temperature are used.
The amorphous silicon film formed by the CVD method, the vapor deposition method, or the like is formed into 55
A higher quality polycrystalline silicon film can be obtained by solid phase growth method in which crystallization is performed by annealing at a temperature of 0 to 750 ° C., or non-single crystal silicon film formed by the same method is recrystallized by laser. It is also possible to use the method described above.

After forming a pattern on the polycrystalline silicon layer 202, a gate insulating film 203 is formed by thermal oxidation. The film thickness is 1200Å by dry oxidation at 1150 ° C. After forming the gate insulating film 202, the gate wiring layer 2
04 is deposited. As the film forming method of the gate wiring layer 204, the LPCVD method is used, and after forming 6000Å film, N + diffusion is performed to reduce the resistance.

FIG. 2B shows a step of selectively forming an insulating film on the gate wiring 204. In the figure, 205 is an insulating film selectively formed on the gate wiring. The insulating film 205 is a silicon nitride film formed by the LPCVD method. Monosilane, dichlorosilane, and ammonia are used as the reaction gas, and the substrate temperature is 800 ° C.
The film is formed at about 000Å. By adding a gas containing fluorine or chlorine to the reaction gas and performing film formation at low pressure,
The silicon nitride film can be selectively formed only on the gate wiring. Of course, it is also possible to form a silicon nitride film by the plasma CVD method as in the embodiment shown in FIG.

FIG. 2C shows a step of forming the source / drain regions 206 by the ion implantation method. Since the insulating film layer 205 is formed over the gate wiring 204, an offset region is formed between the gate wiring and the source / drain regions, so that off current, which is a problem in thin film transistor characteristics, can be reduced. You can Alternatively, an LDD structure may be formed by performing low-concentration ion implantation before forming the insulating film layer 205. The length of the offset region can be controlled by the film thickness of the insulating film layer 205, and can be controlled separately from the shape of the gate wiring layer 204. In order to form a thin film transistor having a high on / off ratio, it is desirable that the film thickness of the insulating film layer 205 be 500 to 5000 Å, and particularly 1000 to 2000 Å will give good results.

FIG. 2 (d) shows a completed state of the thin film transistor.

After ion implantation, an interlayer insulating film is formed,
After forming the contact holes, an aluminum wiring layer is formed.

AP is used as a method for forming the interlayer insulating film 207.
400 at 480 ° C using the CVD method (normal pressure CVD method)
0Å Deposition is performed. In order to stabilize the interlayer insulating film and activate the impurities introduced by ion implantation, 90
Annealing is performed at 0 ° C. for 5 hours. After the annealing, plasma treatment in an atmosphere containing hydrogen is effective in improving the characteristics of the manufactured thin film transistor. In the case of performing the above plasma treatment, it is preferable to perform annealing at a temperature of about 300 to 350 ° C. in order to suppress variations in characteristics such as threshold voltage of manufactured thin film transistors.

A normal photo-etching process is used to form the contact hole, and a sputtering method using an aluminum-silicon-copper target is used to form the aluminum wiring. After the aluminum wiring 208 is formed, annealing is performed at 250 to 300 ° C. to reduce variations in characteristics of the manufactured thin film transistors.

The use of the steps described above is particularly effective for obtaining good off characteristics in a process using a high quality polycrystalline silicon film produced by a solid phase growth method or a method such as laser annealing. is there.

Further, although an example of manufacturing a thin film transistor is shown here, the method for manufacturing a semiconductor device of the present invention can be applied to all insulated gate type semiconductor elements.

[0042]

As described above, according to the present invention, a thin film transistor having an offset structure or an LDD structure can be formed by a simple process even on a large substrate. It is also possible to configure the entire process at a low temperature of 450 ° C or lower, using borosilicate glass (Corning 7
(059 etc.) can be formed on a relatively inexpensive glass substrate. As a result, it has become possible to manufacture a large-sized, high-resolution liquid crystal display panel, a large-sized, high-speed, high-resolution contact image sensor, a three-dimensional IC, etc. at low cost.

[Brief description of drawings]

FIG. 1 is a process sectional view showing an example of a manufacturing process of a semiconductor device according to an embodiment of the invention.

FIG. 2 is a process sectional view showing another example of the manufacturing process of the semiconductor device according to the embodiment of the invention.

[Explanation of symbols]

 101, 201 Insulating amorphous material 102, 202 Polycrystalline silicon layer 103, 203 Gate insulating film 104, 204 Gate electrode 105, 205 Insulating film layer 106, 206 Impurity-doped polycrystalline silicon layer 107, 207 Interlayer insulating layer 108, 208 wiring layer

Claims (3)

[Claims] 1. A semiconductor device in which a channel region of an insulated gate semiconductor device is formed of a semiconductor containing silicon as a main component, and a polycrystalline semiconductor layer and a gate mainly containing silicon containing a channel region and doped with impurities such as boron. A semiconductor device, comprising: an insulating film, a gate electrode, and at least a thin film forming a source / drain region formed on at least a part of a polycrystalline semiconductor layer mainly containing silicon including the channel region. 2. A method of manufacturing an insulated gate semiconductor device, comprising the step of selectively forming an insulating film on a gate electrode. 3. The semiconductor according to claim 1, wherein in the step of forming the thin film forming the source / drain regions, the thin film is selectively formed under the condition that the thin film is not formed at least on the insulator. Device manufacturing method.