JPH06181311A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a CMOS thin film transistor at the prescribed temperature or lower by a method wherein by providing a first conductive thin film constituting a source and drain region on the lower side of a part of a polycrystalline semiconductor layer and also by providing another thin film constituting a, source and rain region, having a conductivity the opposite to the first conductivity, on the upper side of the above-mentioned thin film. CONSTITUTION:A polycrystalline silicon layer 103 is formed on an impurity- doped silicon polycrystalline layer 102 using a CVD method. After a gate insulating film 104, a gate wiring layer 105 and an interlayer insulating film have been formed on the polycrystalline silicon layer 103, an aperture part is provided on the thin film which constitutes the source and drain region of the interlayer insulating film 108 and the gate insulating film 104. An impurity-doped silicon layer 107 is formed on the aperture part, and a source and drain part is provided. As a result, all proceses can be conducted at a low temperature of 450 deg.C or lower, and many kinds of materials can be selected as a substrate 101.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a semiconductor device on an insulating amorphous material and its manufacturing method.

[0002]

2. Description of the Related Art In recent years, active attempts have been made to form high-performance TFTs (thin film transistors) using polycrystalline silicon as an element material at low temperature on a low-melting glass substrate. In particular, borosilicate glass (7059 manufactured by Corning Co., Ltd.), which is cheaper than a quartz substrate, is used as the substrate, and the maximum temperature of the process is 4
CMO with high mobility and high on / off ratio below 50 ° C
Practical application of a low-temperature process for producing an S-type poly-Si TFT is desired.

A conventional method for forming a CMOS type poly-Si TFT is, for example, the 1990 International Electroton Deviation Meeting.
Technical Digest (1990 Interna
regional Electron Devices M
eating Technical Digest),
pp. As seen in 843 and the like, a method of forming a source / drain region by ion implantation by a self-alignment method using a gate electrode as a mask is widely used.

[0004]

However, in such a conventionally used TFT structure and manufacturing method, the ion-implanted source / drain regions are formed, so that the crystallinity of the source / drain regions deteriorates. 450
Since heat treatment at a low temperature of ℃ or less cannot sufficiently recover such deterioration of crystallinity, an off-leakage current due to an electron / hole pair generation current at the drain end is generated, There is a problem that a high on / off ratio cannot be obtained. Therefore, the present invention provides a device structure capable of forming a more practical CMOS thin film transistor at a low temperature of about 450 ° C. or less, and a method for manufacturing the same.

[0005]

In order to solve the above-mentioned problems, a semiconductor device of the present invention is a polycrystalline semiconductor layer mainly composed of silicon containing a channel region and doped with impurities such as boron, A gate insulating film, a gate electrode having a side wall, and a thin film forming a source / drain region having a first conductivity under at least a part of a polycrystalline semiconductor layer mainly containing silicon including the channel region. At least a thin film forming a source / drain region having conductivity opposite to the first conductivity is provided above at least a part of the region of the polycrystalline semiconductor layer.

A method of manufacturing a semiconductor device according to the present invention is
A step of forming a polycrystalline semiconductor thin film having a first conductivity, and a polycrystalline semiconductor mainly composed of silicon including a channel region on the polycrystalline semiconductor thin film having a first conductivity and doped with impurities such as boron Forming a layer,
A step of forming a gate insulating film on the polycrystalline semiconductor layer including the channel region, a step of forming a gate electrode, and a conductivity opposite to the first conductivity on the polycrystalline semiconductor layer including the channel region. In the step of forming a polycrystalline semiconductor thin film having a conductivity opposite to that of the first conductivity, it has a step of forming a polycrystalline semiconductor thin film having a conductivity opposite to that of the first conductivity. Is characterized in that the polycrystalline semiconductor thin film having conductivity is selectively formed under the condition that the polycrystalline semiconductor thin film is not formed on the insulating material.

[0007]

FIG. 1 is a process sectional view showing an example of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 1 (a) shows a state in which an impurity-doped polycrystalline silicon layer 102 and polycrystalline silicon layer 103 are formed on an insulating substrate 101. The impurity-doped silicon layer 102 forms the source / drain layers of the P-type thin film transistor to be manufactured, and the polycrystalline silicon layer forms the channel regions of the P-type and N-type thin film transistors.

As the insulating substrate 101, APC is provided on the surface.
A borosilicate glass substrate having an NSG layer formed by the VD method (atmospheric pressure CVD method) is used.

As a method for forming the impurity-doped silicon layer 102, a plasma CVD method was used, and a film was formed at a substrate temperature of 400.degree. Silane (SiH4) and fluorinated silane (SiF4) were used as the reaction gas, and the film was formed at a mixing ratio of silane, fluorinated silane, and hydrogen = 1: 30. As a doping gas, an argon-based 20
Diborane (B2H6) having a concentration of 00 ppm is used, and is added about 1/4 of the flow rate of fluorinated silane. It is possible to form an impurity-doped polycrystalline silicon film having good characteristics in a flow rate ratio of silane and silane fluoride = 1: 20 to 1: 100. Further, disilane (Si2H6) may be used instead of silane. In that case, a polycrystalline silicon film having good characteristics can be formed by setting the flow rate ratio to fluorinated silane in the range of 1: 5 to 1:30. Although it is possible to form a polycrystalline silicon film at a low substrate temperature of about 300 ° C., it is preferably 350 ° C. or higher.

Similarly, by forming a film while diluting the source gas (silane, disilane, fluorinated silane, etc.) with hydrogen in the range of 0.5 to 5%, good characteristics can be obtained at a low temperature of 450 ° C. or lower. A polycrystalline silicon film can be formed.
Although it is possible to form a polycrystalline silicon film as a substrate temperature up to a low temperature of about 200 ° C., it is desirable to set it to 300 ° C. or higher in order to obtain good film quality. Further, as a raw material gas, in addition to silane, disilane, and hydrogen, an appropriate amount of a reaction gas containing an element such as fluorine (F) and chlorine (Cl) is mixed, so that polycrystalline silicon is formed at a higher film-forming rate. A film can be formed and the film formation time can be shortened. As an example of film forming conditions, silane, dichlorosilane, and hydrogen are used as the reaction gas, and the mixing ratio is, for example,
Silane: dichlorosilane = 1: 20 to 1: 200,
When the substrate temperature is about 300 ° C. to 450 ° C. in the range of silane: hydrogen = 1: 20 to 1: 100, a polycrystalline silicon film having good characteristics can be formed.

Impurity-doped polycrystalline silicon layer 10
After forming a pattern on the second layer by a photo-etching process, a polycrystalline silicon layer 103 is formed.

As a film forming method for the polycrystalline silicon layer 103, a plasma CVD method is used. Under the same film forming conditions as those for the impurity-doped silicon layer 102, argon-based 30 ppm diborane is used as a source gas (silane). , Disilane, fluorinated silane).
A film is formed by adding about 5%. The characteristics of the P-type and N-type thin film transistors to be manufactured can be made uniform by adding about 0.1 to 5% of such a doping gas to the flow rate of the source gas.

Before the formation of the polycrystalline silicon film 103, light etching with hydrofluoric acid and plasma treatment in a hydrogen atmosphere are performed. Such treatment is effective in suppressing the leak current when the thin film transistor to be manufactured is off.

FIG. 1B shows an N-type transistor of the interlayer insulating film 108 and the gate insulating film 104 after the gate insulating film 104, the gate wiring layer 105 and the interlayer insulating film 108 are formed on the polycrystalline silicon layer 103. 2 shows a state in which an opening is provided in the region where the source / drain is formed.

As a method of forming the gate insulating film 104,
Using a magnetron sputtering method targeting SiO2, in an argon atmosphere containing 10% oxygen,
The substrate temperature was set to 350 ° C., and 1500 Å film was formed. The amount of oxygen added to argon is appropriately 3 to 20%, and 5 to 1
A gate film having a particularly high breakdown voltage can be formed within the range of 5%. It is possible to form a gate film having a higher breakdown voltage when the substrate temperature is higher to some extent, but it is suitable to set the temperature to 250 to 400 ° C. In addition, as a method for forming the gate insulating film 203, ECR using silane and oxygen as source gases
A thin film transistor having good characteristics can also be manufactured by using an (electron cyclotron resonance) CVD method.

The gate wiring layer 105 is a polycrystalline silicon film and is formed by the plasma CVD method under the same film forming conditions as the impurity-doped silicon layer 102. As a doping gas, arsenic-based 2000 ppm phosphine (PH3) is added by about 1/3 of the flow rate of the source gas to form a film. After film formation, a pattern is formed by a photoetching process.

The interlayer insulating film 108 is an NSG film, which is formed by a low pressure CVD method using silane and oxygen as source gases.
A 800 nm film is formed at a substrate temperature of 430 ° C. afterwards,
Openings are formed in the regions serving as the source / drain of the N-type thin film transistor by photoetching.

In the P-type thin film transistor, an offset region of about 0.2 μm is provided between the gate wiring layer 105 and the impurity-doped silicon layer 102 in order to reduce the leak when turned off. Although the offset amount is about 0.1 μm, the effect of reducing the leak at the time of off is recognized,
From the relationship between the margin at the time of alignment and the characteristics at the time of ON, 0.
It is suitable to set it to 2 to 0.5 μm.

FIG. 1 (c) shows a state in which an impurity-doped silicon layer 107 is formed in the opening formed in FIG. 1 (b). Impurity-doped silicon layer 10
Reference numeral 7 is a source / drain portion of an N-type thin film transistor.

The silicon layer 107 doped with impurities is
It was formed by using a plasma CVD method under the same film forming conditions as the impurity-doped silicon layer 102. As a doping gas, arsenic-based 2000 ppm phosphine (PH3) is added by about 1/3 of the flow rate of the source gas to form a film. After the film formation, the polycrystalline silicon film 107 doped with impurities in the portion other than the opening formed in FIG. 1B is removed by using a photoetching process.

FIG. 1D shows a completed state of the thin film transistor.

After forming the pattern of the silicon film 107 doped with impurities, plasma treatment is performed in a hydrogen atmosphere to improve the characteristics of the thin film transistor. This treatment is effective when the hydrogen concentration is about 10% or more,
Alternatively, it may be performed after the pattern of the wiring layer 109 is formed.

After forming a contact hole in the P-type thin film transistor by a photo-etching process, silicon is deposited on the contact hole.
The wiring layer 109 is formed by a sputtering method using an aluminum-silicon-copper target containing approximately 5%. After the pattern of the wiring layer 109 is formed by the photoetching process, the temperature is set to 250 ° C. in a nitrogen atmosphere containing about 10% hydrogen.
Annealing at 300 ° C. is performed to stabilize the characteristics and contact characteristics of the thin film transistor.

FIG. 2 is a process cross-sectional view showing another example of the method for manufacturing a semiconductor device according to the embodiment of the present invention.

FIG. 2 (a) shows a state in which an impurity-doped polycrystalline silicon layer 202 and polycrystalline silicon layer 203 are formed on an insulating substrate 201.

The impurity-doped silicon layer 202 forms the source / drain layers of the P-type thin film transistor to be manufactured, and the polycrystalline silicon layer 203 forms the channel regions of the P-type and N-type thin film transistors.
It is formed by using the same method as the impurity-doped silicon layer 102 and the polycrystalline silicon layer 103 shown in (a).

FIG. 2B shows a state in which the gate insulating film 204 and the gate wiring layer 205 are formed on the polycrystalline silicon layer 203.

The gate insulating film 204 and the gate wiring layer 20
5 is formed by forming the gate insulating film 1 shown in FIG.
04 and the gate wiring layer 105, the same method is used.

FIG. 2C shows a state in which a side wall 206 is formed on the gate wiring layer 205 and then an impurity-doped silicon layer 207 is formed on the polycrystalline silicon layer 203 by selective film formation of polycrystalline silicon. Is. The impurity-doped silicon layer 207 forms the source / drain regions of the N-type thin film transistor to be manufactured.

The side wall 206 is formed by forming a oxide film by a low pressure CVD method using silane and oxygen as source gases, then covering a region where a P-type thin film transistor is to be formed with resist, and performing anisotropic etching. It is formed by etching the oxide film.

As a method of forming the silicon layer 207 doped with impurities, a plasma CVD method is used and a substrate temperature of 350 is used.
A 2000 Å film was formed at ℃. Monosilane or dichlorosilane is used as the source gas, and the mixing ratio is, for example, silane:
Dichlorosilane is 1:50, and the film is formed by diluting it with hydrogen to about 20%. Argon-based 2000 ppm phosphine as a doping gas is added to about 1/3 of the flow rate of the source gas. Monosilane: dichlorosilane = 1: 20 to 1: 200
By diluting these source gases with hydrogen to 50% or less to form a film, the polycrystalline silicon can be selectively formed only on the polycrystalline silicon. The substrate temperature is 200
It is possible to form a film from about 0 ° C, but it is desirable to set the temperature to 300 ° C or higher in order to obtain a good film quality.

In order to stably form an impurity-doped polycrystalline silicon film only on the polycrystalline silicon, RCA cleaning is performed before the film formation. In addition to this, plasma treatment in an atmosphere containing hydrogen and light etching with hydrofluoric acid are also effective for stable selective film formation.

FIG. 2D shows a completed state of the thin film transistor.

After forming the silicon layer 207 doped with impurities, the interlayer insulating film 208 is formed by the low pressure CVD method. Silane and oxygen are used as a source gas, and a film having a thickness of 800 nm is formed at a substrate temperature of 430 ° C. After that, a contact hole is formed by a photoetching process. Wet etching using hydrofluoric acid is used for etching the contact holes.

After the interlayer insulating film 208 is formed, plasma treatment is performed in a hydrogen atmosphere to improve the characteristics of the thin film transistor to be manufactured. This step may be performed after forming the pattern of the wiring layer 209.

After forming the contact hole, the wiring layer 209 is formed by the sputtering method. Wiring layer formation is shown in Figure 1.
The same method as the wiring layer 109 shown in (d) is used. After the pattern is formed by the photo-etching process, the characteristics of the thin film transistor and the contact characteristics are stabilized by annealing at 250 to 300 ° C. in a nitrogen atmosphere containing about 10% hydrogen.

In this embodiment, all steps are performed at 450 ° C.
This can be done below, and many types of materials can be selected for the substrates 101 and 201. As the substrate, other glass substrates having higher heat resistance (4
It is also possible to use (a material having a heat resistance of 50 ° C. or more), quartz glass having a higher heat resistance, or a silicon substrate having an insulating film formed on the surface.

In this embodiment, the case where the source / drain of the P-type thin film transistor is formed has been described above.
By changing the doping gas, phosphine or arsine is added as a doping gas when the impurity-doped silicon layers 102 and 202 are formed, and diborane is added as a doping gas when the impurity-doped silicon layers 107 and 207 are formed. Thus, the source / drain of the N-type thin film transistor can be formed first.

[0040]

As described above, according to the present invention, a practical CMOS type polycrystalline silicon thin film transistor is provided.
It became possible to form at a low temperature of about 50 ° C. or less.
Therefore, it becomes possible to form a CMOS circuit having practical characteristics on a relatively inexpensive glass substrate, and a large high-resolution liquid crystal display panel, a large high-speed high-resolution contact image sensor, or a tertiary The original IC etc. can be manufactured at low cost.

[Brief description of drawings]

FIG. 1 is a process cross-sectional view showing an example of a manufacturing process of a semiconductor device according to an embodiment of the invention.

FIG. 2 is a process sectional view showing another example of the method for manufacturing the semiconductor device in the example of the present invention.

[Explanation of symbols]

101, 201 ... Substrate 102, 202 ... Impurity-doped silicon layer 103, 203 ... Polycrystalline silicon layer 104, 204 ... Gate insulating film 105, 205 ... Gate wiring layer 206 ... -Sidewalls 107, 207 ... Impurity-doped silicon layers 108, 208 ... Interlayer insulating films 109, 209 ... Wiring layers

Claims (3)

[Claims] 1. A semiconductor device in which a channel region of an insulated gate semiconductor device is formed of a polycrystalline semiconductor containing silicon as a main component, and a polycrystalline semiconductor layer containing silicon containing the channel region as a main component and doped with impurities such as boron. A gate insulating film, a gate electrode, and at least a thin film forming a source / drain region having the first conductivity under at least a part of the polycrystalline semiconductor layer mainly containing silicon including the channel region. A semiconductor device comprising at least a thin film of a source / drain region having a conductivity opposite to the first conductivity above at least a part of the region of the polycrystalline semiconductor layer. 2. A method of manufacturing a semiconductor device, wherein a channel region of an insulated gate semiconductor device is formed of a polycrystalline semiconductor mainly containing silicon, and a step of forming a polycrystalline semiconductor thin film having a first conductivity. And a step of forming a polycrystalline semiconductor layer mainly composed of silicon including a channel region on the polycrystalline semiconductor thin film having the first conductivity and doped with impurities such as boron, and the polycrystalline semiconductor including the channel region. Forming a gate insulating film on the layer, forming a gate electrode, and forming a polycrystalline semiconductor thin film having conductivity opposite to the first conductivity on the polycrystalline semiconductor layer including the channel region. A method of manufacturing a semiconductor device, comprising the steps of: 3. In the step of forming a polycrystalline semiconductor thin film having a conductivity opposite to the first conductivity, the polycrystalline semiconductor thin film having a conductivity opposite to the first conductivity is insulating. 3. The method for manufacturing a semiconductor device according to claim 2, wherein the film is selectively formed on the material of claim 1 under the condition that the film is not formed.