JP2002025972A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable an epitaxial layer to be easily and selectively formed through a method different from a selective epitaxial growth method and to reduce labor required for maintaining a device. SOLUTION: An element isolating region 2 and a well layer 3 are formed on a silicon substrate 1, and then a silicon layer 6 of low-impurity concentration is deposited on a region including the element isolating region 2 and an active region 5 through a CVD method. At this point, a single crystal silicon is epitaxially grown on the active region 5 in which the silicon substrate 1 is exposed, but an amorphous silicon is grown on the element isolating region 2. Thereafter, by the use of etchant containing a hydrofluoric acid and a nitric acid, only the amorphous silicon formed in the element isolating region 2 is selectively removed by etching, and the single crystal silicon formed in the active region 5 is hardly etched. By this setup, an epitaxial layer is formed only in the active region 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which a semiconductor layer is selectively formed only on a region of a semiconductor substrate surface where a single crystal semiconductor surface is exposed.

[0002]

2. Description of the Related Art It is generally known that an undesired phenomenon called a short channel effect appears in a MOS type field effect transistor (MOSFET) as its gate dimension becomes shorter. As a means for suppressing the short channel effect, a method of epitaxially growing a silicon layer having an extremely low impurity concentration in a channel region of a MOSFET has been proposed.

As the device size of a MOSFET decreases, the threshold voltage V
th has a large statistical variation (mismatch), and the mismatch of the threshold voltage Vth causes a malfunction in circuit operation.
This is a hindrance when configuring a circuit using the. As a means for suppressing the mismatch of the threshold voltage Vth, a method of epitaxially growing a silicon layer having an extremely low impurity concentration in a channel region of a MOSFET has been proposed.

The step of epitaxially growing a silicon layer having an extremely low impurity concentration is performed, for example, as follows. That is, as shown in FIG. 7A, a known LOCOS or S
After forming an element isolation region 52 by a method such as TI (shallow trench isolation) and forming an N-well or P-well layer 53, the silicon substrate 51 other than the active region, that is, other than the element isolation region 52 is exposed. After a silicon oxide film is formed as a sacrificial oxide film in the region where it is, ions such as boron for threshold voltage adjustment are implanted. Then, the silicon oxide film is removed.

As a result, a boron ion-doped layer 54 for adjusting the threshold voltage is formed (FIG. 7B). Thereafter, only the surface of the silicon substrate 51 in the active region is exposed, and the low impurity concentration silicon layer 55 is selectively epitaxially grown only on the surface of the silicon substrate 51 in the active region (FIG. 7C).

Here, this selective epitaxial growth is performed by:
In order to suppress the diffusion of impurities from the already doped silicon substrate 51, it must be performed at a low temperature of 850 [° C.] or less.
-CVD) equipment. For example, using a UHV-CVD apparatus having an ultimate vacuum of 1E-8 [Torr] or less, using disilane gas or a mixed gas of disilane gas and chlorine at a temperature of 600 ° C. to 850 ° C.

Then, after a gate insulating film is formed, a gate electrode is formed by known lithography and etching using polysilicon as a material. In many cases, refractory metal silicide is further formed on the polysilicon in order to reduce the electric resistance of the gate electrode. After that, after the source and drain regions are formed and the insulating film is formed, a wiring process using a metal material is performed.

Further, in order to suppress the short channel effect of the MOSFET, it is necessary to make the source / drain diffusion layers shallow to form shallow junctions (shallow junctions). However, when a salicide step of forming metal silicide by applying a metal such as titanium or cobalt to the silicon surface of the source / drain region is performed, silicon from the surface to a certain depth in the region is consumed. It is difficult to form a shallow junction. Therefore, a method called raised source / drain is used.

That is, as shown in FIG.
A gate insulating film 58 is formed on the substrate 1 in accordance with a known procedure, a gate electrode 57 is formed thereon, low-concentration ion implantation is performed, a sidewall spacer 59 is formed, and high-concentration ion implantation is performed again. Is performed to form source / drain regions 60 composed of high concentration and low concentration diffusion regions (FIG. 8A). Thereafter, the surface of the silicon substrate 51 is exposed only in the source / drain region 60, and a silicon layer 61 is grown in this region by selective epitaxial growth (FIG. 8B). Then, the silicon layer 61 is used for silicon consumed in the salicide process to form a silicide 62 of, for example, cobalt (FIG. 8C).

The selective epitaxial growth on the source / drain region 60 is also performed in the same manner as in the above-described selective epitaxial growth on the channel region.
V-CVD) devices and the like are used. That is, for example, UHV-CVD with an ultimate vacuum of 1E-8 [Torr] or less
Using an apparatus, using disilane gas or a mixed gas of disilane gas and chlorine, from 600 ° C. to 850 ° C.
Temperature.

[0011]

However, the above U
In order to perform selective epitaxial growth on the above-described channel region or selective epitaxial growth on the source / drain regions using an HV-CVD apparatus, it is necessary to selectively perform epitaxial growth only on a specific region, and accuracy is required. , Has become difficult to control.

Attempts have also been made to perform selective epitaxial growth in a CVD apparatus using dichlorosilane or dichlorosilane and hydrochloric acid gas. However, in this case, it is difficult to deposit a silicon film at a low temperature, The gas, especially hydrochloric acid gas, corrodes metal parts in the system and causes metal contamination, so that a great deal of labor is required for maintenance of the apparatus.

Accordingly, the present invention has been made in view of the above-mentioned conventional unsolved problems, and can be easily and selectively applied only to a portion where the surface of a semiconductor substrate is exposed without using a chlorine-based gas. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of forming an epitaxial silicon layer on a substrate.

[0014]

In order to achieve the above object, a method of manufacturing a semiconductor device according to claim 1 of the present invention comprises:
A non-selective CVD method is used for a first region where the surface of the single crystal semiconductor layer formed over the semiconductor substrate is exposed and a second region where the surface of the single crystal semiconductor layer is not exposed. And a selective etching step of selectively etching and removing only the semiconductor layer formed on the second region among the semiconductor layers deposited in the deposition step. It is characterized by:

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device, the first region is a region where the surface of the single crystal silicon layer is exposed, and the second region is a silicon oxide film or a silicon nitride film. A region where the insulating film of the film is exposed, wherein the depositing step comprises epitaxially growing single crystal silicon in the first region using a non-selective CVD method, and forming an amorphous film in the second region. A step of depositing silicon, wherein the selective etching step is a step of selectively etching and removing only the amorphous silicon layer formed on the second region by wet etching with an etchant containing hydrofluoric acid and nitric acid. It is characterized by being.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device, the first region is a region where the surface of the single crystal silicon layer is exposed, and the second region is a silicon oxide film or a silicon nitride film. In a region where the insulating film of the film is exposed, the depositing step comprises depositing amorphous silicon in the first and second regions using a non-selective CVD method, and then annealing the first and second regions. A step of crystallizing only the amorphous silicon layer deposited on the second region, wherein the selective etching step is an amorphous silicon layer formed on the second region by wet etching using an etchant containing hydrofluoric acid and nitric acid. It is characterized in that it is a step of selectively etching and removing only.

According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device according to the second or third aspect, the composition of the etching solution is hydrofluoric acid (containing 49% by weight of HF). 0.5-1.5% by volume, water 5-
15 vol% nitric acid (70 wt% HNO ₃ containing) 30-5
0 volume% and acetic acid 30-50 volume%.

Further, a method of manufacturing a semiconductor device according to claim 5 is the method of manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the semiconductor device is a semiconductor device forming an analog circuit. It is characterized by. According to the first to fifth aspects of the present invention, the first region where the single crystal semiconductor surface is exposed and the second region where the single crystal semiconductor surface is not exposed because it is covered with an insulator or the like. In a semiconductor substrate such as a silicon substrate or an SOI substrate in which a single-crystal silicon layer is formed on an insulating substrate, both the first region where the single-crystal semiconductor surface is exposed and the second region where the single-crystal semiconductor surface is not exposed A semiconductor layer is deposited on both of the regions by a non-selective CVD method, and thereafter, only the semiconductor layer deposited on the second region is selectively etched and removed. A layer will be formed.

That is, for example, when depositing a semiconductor layer, a semiconductor layer is epitaxially grown in a first region where a single crystal semiconductor surface such as a single crystal silicon layer is exposed, and a silicon oxide film or a silicon nitride film is insulated. In a second region such as a film where the single crystal semiconductor surface is not exposed, a semiconductor layer is deposited so as to form an amorphous silicon layer. Further, for example, after depositing an amorphous silicon layer in the first and second regions, this is annealed to remove only the amorphous silicon layer in the first region where the single crystal semiconductor surface such as a single crystal silicon layer is exposed. Crystallization and the like are performed.

Then, for example, etching is performed using an etching solution containing hydrofluoric acid and nitric acid, and the composition of the etching solution is 0.5 to fluoric acid (containing 49% by weight of HF).
1.5% by volume, 5 to 15% by volume of water, nitric acid (70% by weight H
NO ₃ content) 30-50% by volume, acetic acid 30-50% by volume
By doing so, only the amorphous silicon layer is selectively removed, that is, only the silicon layer in the second region where the single crystal semiconductor surface is not exposed is selectively removed, and silicon is removed only in the first region. A layer will be formed.

Therefore, the semiconductor layer can be easily formed only in the first region where the surface of the semiconductor substrate is exposed by selectively etching the semiconductor layer after the non-selective formation of the semiconductor layer. And can be realized without using a chlorine-based gas.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. First, a first embodiment will be described. In the first embodiment, a silicon layer is epitaxially grown only in a channel region of a MOSFET.

As shown in FIG. 1, first, a silicon substrate 1
The element isolation region 2 is formed by a known method such as LOCOS or STI (Shallow Trench Isolation).
Is formed, and an N-well layer or a P-well layer 3 is formed (FIG. 1A). Then, a silicon oxide film as a sacrificial oxide film is formed in the active region 4, that is, in a region other than the element isolation region 2 where the silicon substrate 1 is exposed. After performing the ion implantation for adjustment, the silicon oxide film is removed. Thus, a boron ion-doped layer 5 for adjusting the threshold voltage is formed in the active region 4.
(B)).

The MOSFET in the silicon substrate 1 is formed by this well formation and ion implantation for adjusting the threshold voltage.
The active region 4 has a concentration of 1E16 [cm ⁻³ ] to 1
An impurity layer of a type corresponding to the implanted ions, including an N-type or P-type impurity of E18 [cm ^-3 ] or both of them, is formed. Next, a hydrofluoric acid treatment is performed to expose only the surface of the silicon substrate 1 in the active region 4, and then the silicon substrate 1 is introduced into a low-pressure CVD apparatus, and H ₂ (hydrogen) at 800 ° C. to 850 ° C. 2) The natural oxide film on the active region 4 is removed by annealing.

Next, silane or disilane or a mixed gas containing these gases is used as a raw material at a pressure of 0.01.
0.5 [Torr] from [Torr], temperature 350
The first pressure is reduced by the low pressure CVD method from [° C] to 600 [° C].
Non-selectively in both the active region 4 as the region and the element isolation region 2 as the second region.
[Nm] to 100 [nm], impurity concentration 1E14 [c
m ⁻³ ] is deposited (deposition step).

The impurity concentration in the low impurity concentration silicon layer 6 is preferably as low as possible.
m ^-3 ] or less. At this time, in the active region 4 where the silicon substrate 1 is exposed, single crystal silicon 7 grows epitaxially from the underlying silicon substrate 1, but the silicon substrate 1 is not exposed and the surface is made of SiO ₂ or the like. Amorphous silicon 8 grows in the formed element isolation region 2 (FIG. 1C).

The means for depositing the low impurity concentration silicon layer 6 for carrying out the present invention is not limited to the low pressure CVD method. Low pressure RTP method, UHV-CVD
Or normal pressure CVD. Next, hydrofluoric acid (H
F) and etching using a silicon etching solution containing nitric acid (HNO ₃ ) and amorphous silicon formed in the element isolation region 2 without substantially etching the single crystal silicon 7 formed in the active region 4. Only eight portions are selectively etched and removed. Thus, a low impurity concentration silicon layer 9 is formed only in the active region 4 (FIG. 1D) (selective etching step).

The preferred composition of the silicon etchant is 0.5 to 1.5 vol% of hydrofluoric acid (containing 49 wt% HF), 5 to 15 vol% of water, and 30 to 50 nitric acid (containing 70 wt% HNO ₃ ). % By volume, and 30 to 50% by volume of acetic acid.
Further, a more preferable composition of the silicon etching solution is 0.92% by volume of hydrofluoric acid (containing 49% by weight of HF), 8.18% by volume of water, and nitric acid (containing 70% by weight of HNO ₃ ) 4.
5.45% by volume and 45.45% by volume of acetic acid.

In the steps after the step of forming the low impurity concentration silicon layer 9 on the active region 4,
In order to suppress the diffusion of impurities from the doped silicon substrate 1 to the low-impurity-concentration epitaxial silicon layer 9, all the steps are performed at 850 ° C. or lower, preferably 75 ° C.
0 ° C. or lower low-temperature furnace treatment or 850 ° C.
RTA when performing heat treatment at a temperature exceeding [° C]
(Rapid Thermal Processor) The processing is performed in a short time of 3 minutes or less using a device.

Under this condition, following the step of forming the low impurity concentration silicon layer 9, for example, 2 [n] is thermally oxidized at 850 ° C. or lower, preferably 750 ° C. or lower.
m] to 40 [nm] is formed as the gate insulating film 10 as a gate insulating film 10 (FIG. 2A). In practicing the present invention, the gate insulating film 10 is not limited to a silicon oxide film, but may be any one of a silicon nitride film, a silicon nitride oxide film, a metal oxide film, and the like, or a multilayer film obtained by laminating them. good.

Then, polysilicon used as a gate material is deposited by a known method, and impurities are introduced into the deposited polysilicon layer 11 by ion implantation of phosphorus or boron or phosphorus treatment using phosphorus oxychloride ( FIG. 2 (b). Next, known lithography and etching are performed to pattern the gate electrode 12 (FIG. 2).
(C)). Needless to say, the length of the gate electrode 12 formed as a result depends on the process generation to which the invention is applied and the convenience of circuit design.
m] to 10.0 [μm]. This 0.1
If it is in the range of [μm] to 10.0 [μm], it can be used for an analog circuit generally required.

Further, a refractory metal silicide may be formed on the gate electrode 12 for the purpose of reducing the electric resistance of the gate electrode 12. Next, by a known method,
After implanting N ⁻ ions to form a low concentration diffusion region 13, a sidewall spacer 14 is formed, and N ⁺ ions are further implanted.
Ion implantation is performed to form the high-concentration diffusion region 15 to form source and drain regions (FIG. 2D).

Activation of the doped impurities is performed at a temperature of 950.
The heat treatment is performed by a short-time heat treatment using an RTA (rapid thermal processor) device for not less than [° C.] and not more than 1150 [° C.] for not less than 20 seconds and not more than 3 minutes. Finally, the steps after the well-known interlayer insulating film formation and metal wiring formation are performed. As described above, by performing the above steps, non-selective low-impurity-concentration silicon deposition and selective etching are performed without using selective epitaxial growth, so that the low-impurity-concentration silicon layer 9 is formed only in the active region 4.
Can be formed epitaxially.

Therefore, by non-selectively performing low impurity concentration silicon deposition, single crystal silicon 7 and amorphous silicon 8 are formed, and hydrofluoric acid (H
By etching using a silicon etchant containing F) and nitric acid (HNO ₃ ), only the amorphous silicon 8 is etched and the active region 4 is etched.
Since the single-crystal silicon 7 remains only in this case, the single-crystal silicon 7 can be easily formed as compared with the case where selective epitaxial growth is performed. Further, the control conditions for forming the low-impurity-concentration silicon layer 9 are not strict as compared with the case of performing selective epitaxial growth, so that the temperature condition can be set lower.

Further, since it can be carried out without using a chlorine-based gas, it is possible to avoid requiring a large amount of labor for mechanical maintenance. In the MOSFET thus formed, a silicon layer having a low impurity concentration is epitaxially grown in the active region 4.
Even if the gate size is short, the short channel effect is suppressed and the variation of the threshold voltage Vth, that is, the mismatch is also suppressed. Therefore, a fine MOSFET can be obtained, and a mismatch between MOSFETs is reduced, so that a highly accurate analog circuit can be obtained.

Next, a second embodiment of the present invention will be described. In the second embodiment, a low impurity concentration amorphous silicon layer is deposited and then annealed to crystallize the amorphous silicon.
The same parts as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

That is, as shown in FIG. 3A, an element isolation region 2 is formed on a silicon substrate 1 by a known method such as LOCOS or STI (shallow trench isolation), and an N well layer is formed. Or P-well layer 3
Is formed, the threshold voltage Vth is applied to the active region 4.
By performing ion implantation for adjustment, a boron-doped layer 5 for adjusting threshold voltage is formed.

By ion implantation used for the well formation and the threshold voltage Vth adjustment, the MO
The active region 4 of the SFET has a concentration of 1E16 [c
An impurity layer of a type corresponding to the introduced impurities, including N-type or P-type impurities from m ^-3 ] to 1E18 [cm ^-3 ], or both, is formed. Next, after exposing only the surface of the silicon substrate 1 in the active region 4 by hydrofluoric acid treatment, the silicon substrate 1 is introduced into a low-pressure CVD apparatus, and H ₂ (hydrogen) annealing is performed at 800 ° C. to 850 ° C. As a result, the natural oxide film on the active region 4 is removed.

Next, silane was used as a raw material gas at a pressure of 0.1
0.5 [Torr] from [Torr], temperature 500
By a low-pressure CVD method from [° C.] to 550 [° C.], both the active region 4 and the element isolation region 2 are non-selectively and non-selectively film thicknesses from 20 [nm] to 100 [nm] and impurity concentration 1E14 [cm ^{− 3} ] The following low impurity concentration amorphous silicon layer 6a is deposited. The impurity concentration in the low impurity concentration silicon layer 6a is preferably as low as possible, and is preferably 1E13 [cm ^-3 ] or less.

In practicing the present invention, the source gas for depositing the amorphous silicon 6a is not limited to silane gas, but may be, for example, disilane. Next, at a temperature of 500 ° C. to 550 ° C., time 1
Annealing from 0 minutes to 100 hours is performed to crystallize the amorphous silicon in contact with the active region 4, that is, to perform solid-layer epitaxial growth (FIG. 3B).

At this time, in the amorphous silicon layer (single crystal region 7a) on the active region 4 which is in contact with the surface of the single crystal silicon substrate 1, the underlying silicon substrate 1 becomes a seed for crystallization, and crystallization proceeds rapidly. But other SiO
Crystallization hardly occurs in the amorphous silicon layer (amorphous region 8a) on the element isolation region 2 formed by ₂ or the like, and amorphous silicon remains.

Next, hydrofluoric acid (HF) and nitric acid (HNO ₃ )
Is etched with a silicon etching solution containing the following. Only the amorphous silicon portion 8a formed in the element isolation region 2 is selectively etched without substantially etching the single crystal silicon portion 7a formed in the active region 4, Remove. Thus, the low impurity concentration silicon layer 9a is formed only in the active region 4 (FIG. 3C).

The preferred composition of the silicon etching liquid is 0.5 to 1.5 vol% of hydrofluoric acid (containing 49 wt% HF), 5 to 15 vol% of water, and 30 to 50 nitric acid (containing 70 wt% HNO ₃ ). % By volume, and 30 to 50% by volume of acetic acid.
Further, a more preferable composition of the silicon etching solution is 0.92% by volume of hydrofluoric acid (containing 49% by weight of HF), 8.18% by volume of water, and nitric acid (containing 70% by weight of HNO ₃ ) 4.
5.45% by volume and 45.45% by volume of acetic acid.

Thereafter, processing is performed in the same manner as after the step of FIG. 2A of the first embodiment. in this way,
By performing the above steps, a low-impurity-concentration silicon layer 9 is epitaxially formed only in the active region 4 by non-selective low-impurity-concentration amorphous silicon deposition, crystallization annealing, and selective etching without using selective epitaxial growth. it can.

Therefore, in this case, the same operation and effect as those of the first embodiment can be obtained. In addition, even if the MOSFET thus formed has a short gate size, the short channel effect can be obtained. It is possible to suppress the mismatch of the threshold voltage Vth. Next, a third embodiment of the present invention will be described.

In the third embodiment, the present invention is applied to a raised source / drain technique of a source / drain region. That is, as shown in FIG. 4, an element isolation film (L) is formed on a silicon substrate 21 by a known method.
After forming an OCOS 22 and a well layer (not shown), a gate insulating film 26 is formed, a gate material is deposited thereon, and these are patterned to form a gate electrode 25. Then, low-concentration ion implantation is performed, subsequently, sidewall spacers 27 are formed, and high-concentration ion implantation is performed again to form the source and drain regions 28 of the LDD structure.
Is formed (FIG. 4A).

Next, by hydrofluoric acid treatment, the active region, that is, the silicon substrate 21 other than the element isolation region 22 is formed.
After exposing the surface of the silicon substrate 21 only in the area where the silicon substrate 21 is exposed, the silicon substrate 21 is introduced into a low-pressure CVD apparatus, and H ₂ (hydrogen) annealing is performed at 800 ° C. to 950 ° C. The natural oxide film on the drain region 28 is removed.

Next, silane or disilane or a mixed gas containing these gases is used as a raw material at a pressure of 0.01.
0.5 [Torr] from [Torr], temperature 350
The silicon layer 29 having a film thickness of 20 [nm] to 200 [nm] is non-selectively formed on the entire surface of the wafer including the source / drain regions 28 by a low pressure CVD method of [° C.] to 600 [° C.].
Is deposited.

At this time, in the source / drain region 28 where the silicon substrate 21 is exposed, single crystal silicon 30 grows epitaxially from the underlying silicon substrate 21, but the silicon substrate 21 is not exposed, Amorphous silicon 31 grows in other regions covered with ₂ or SiN (FIG. 4B). The means for depositing the silicon layer 29 for carrying out the present invention includes:
It is not limited to the low pressure CVD method. Decompression RTP
Method, UHV-CVD method, or normal pressure CVD method.

Next, hydrofluoric acid (HF) and nitric acid (HNO ₃ )
Is etched using a silicon etching solution containing, and the amorphous silicon portion 31 formed in the other region is selectively etched without substantially etching the single crystal silicon portion 30 formed in the source / drain region 28. And remove. Thus, the silicon layer 32 is formed only in the source / drain regions 28 (FIG. 4C).

The preferred composition of the silicon etching solution is 0.5 to 1.5 vol% of hydrofluoric acid (containing 49 wt% HF), 5 to 15 vol% of water, and 30 to 50 nitric acid (containing 70 wt% HNO ₃ ). % By volume, and 30 to 50% by volume of acetic acid.
Further, a more preferable composition of the silicon etching solution is 0.92% by volume of hydrofluoric acid (containing 49% by weight of HF), 8.18% by volume of water, and nitric acid (containing 70% by weight of HNO ₃ ) 4.
5.45% by volume and 45.45% by volume of acetic acid.

Next, metal silicide 3 is formed in the source / drain region 28 according to a known salicide technique.
3. For example, cobalt silicide is formed. That is,
For example, by forming a metal film (cobalt) on the wafer and then performing a heat treatment, the silicon layer 32 of the source / drain region 28 is silicided, and then a metal film other than the source / drain region 28 remaining unreacted is selected. Removed. As a result, the metal silicide 33 is formed only in the source / drain regions 28, and a salicide transistor is formed.

Then, the steps after the well-known interlayer insulating film formation and metal wiring formation are performed. As described above, the silicon layer 32 can be formed only in the source / drain region 28 by the non-selective silicon deposition and the selective etching without performing the selective epitaxial growth through the above steps. Therefore, in this case as well, it can be formed more easily than in the past, and can be formed at a lower temperature.

Further, since it can be carried out without using a chlorine-based gas, it is possible to avoid requiring a large amount of labor for mechanical maintenance. Next, a fourth embodiment of the present invention will be described. In the fourth embodiment, a low impurity concentration amorphous silicon layer is deposited and then annealed to crystallize the amorphous silicon. The same parts as those in the third embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

That is, as shown in FIG. 5, similarly to the third embodiment, an element isolation film (LOCOS) 22 is formed on a silicon substrate 21 by a known method, and a well layer (not shown) is formed. Then, a gate electrode 25 is formed by forming a gate insulating film 26 and a gate material. And
After the low-concentration ion implantation, the sidewall spacers 27 are formed, and the high-concentration ion implantation is performed to form the source / drain diffusion layers 28 (FIG. 5A).

Next, after exposing only the surface of the silicon substrate 21 in the source / drain regions 28 by hydrofluoric acid treatment, the silicon substrate 21 is introduced into a low-pressure CVD apparatus, and
The natural oxide film on the source / drain regions 28 is removed by H ₂ (hydrogen) annealing at 0 ° C. to 950 ° C. Next, silane was used as a source gas, and a pressure of 0.1 [T
orr] to 0.5 [Torr] and a low pressure CVD method at a temperature of 500 [° C.] to 550 [° C.].
An amorphous silicon layer 29a of [nm] to 200 [nm] is deposited (FIG. 5B).

In practicing the present invention, the source gas for depositing the amorphous silicon layer 29a is not limited to silane gas, but may be disilane, for example. Next, from a temperature of 500 [° C.] to 550
[° C.], annealing for 10 minutes to 100 hours,
The amorphous silicon in contact with the source / drain regions 28 is crystallized. At this time, in the amorphous silicon layer 30a on the source / drain region 28 which is in contact with the surface of the single crystal silicon substrate 21, the underlying silicon substrate becomes a seed for crystallization, and crystallization proceeds rapidly, but other SiO _2, etc. Crystallization hardly occurs in the amorphous silicon layer 31a on the element isolation region formed by
It remains as amorphous silicon.

Next, hydrofluoric acid (HF) and nitric acid (HNO ₃ )
Is etched by using a silicon etching solution containing silicon, and the amorphous silicon portion 31 formed in the other region is hardly etched in the single crystal silicon portion 30a formed in the source / drain region 28.
Only a is selectively etched and removed. As a result, the silicon layer 32a is formed only in the source / drain region 28.
Is formed (FIG. 6A).

The preferred composition of the silicon etching liquid is 0.5 to 1.5 vol% of hydrofluoric acid (containing 49 wt% HF), 5 to 15 vol% of water, and 30 to 50 nitric acid (containing 70 wt% HNO ₃ ). % By volume, and 30 to 50% by volume of acetic acid.
Further, a more preferable composition of the silicon etching solution is 0.92% by volume of hydrofluoric acid (containing 49% by weight of HF), 8.18% by volume of water, and nitric acid (containing 70% by weight of HNO ₃ ) 4.
5.45% by volume and 45.45% by volume of acetic acid.

Then, as in the third embodiment, the steps after FIG. 4D are performed, and a metal silicide, for example, cobalt silicide is formed in the source / drain region 28 by a known salicide technique. 33 are formed (FIG. 6B), and further, an interlayer insulating film forming step, a metal wiring step, and the like are performed. As described above, the silicon layer 32a can be formed only in the source / drain regions 28 by the non-selective silicon deposition and the selective etching without using the selective epitaxial growth.

Therefore, also in this case, the same operation and effect as those of the third embodiment can be obtained. In each of the above embodiments, a case where a silicon substrate is used as a base for forming an element has been described. However, a single crystal silicon layer is formed on an insulating substrate, and this single crystal silicon layer is used as a base for forming an element. It is needless to say that the present invention can be applied to a so-called SOI (silicon-on-insulator) structure.

In each of the above embodiments, the MO
Although the case where the S-type field effect transistor is formed has been described, the invention is not limited to this, and any element having a process of selectively performing epitaxial growth can be applied.

[0063]

As described above, according to the first aspect of the present invention,
According to the invention, the semiconductor layer is deposited on the region where the single crystal semiconductor surface is exposed and the region where the single crystal semiconductor surface is not exposed by the non-selective CVD method, and the single crystal semiconductor surface is exposed. By combining with selective etching of a non-existing region, a semiconductor layer can be selectively formed only in a region where a single crystal semiconductor surface is exposed,
Compared with the case of using a selective epitaxial growth method or the like, the semiconductor device can be formed more easily, and since no chlorine-based gas is used, labor required for device maintenance can be reduced.

[Brief description of the drawings]

FIG. 1 shows a MOS to which a first embodiment of the present invention is applied.
FIG. 4 is a cross-sectional view showing a part of a manufacturing process of a field effect transistor.

FIG. 2 is a continuation of FIG. 1;

FIG. 3 shows a MOS to which the second embodiment of the present invention is applied.
FIG. 4 is a cross-sectional view showing a part of a manufacturing process of a field effect transistor.

FIG. 4 shows a MOS to which the third embodiment of the present invention is applied.
FIG. 4 is a cross-sectional view showing a part of a manufacturing process of a field effect transistor.

FIG. 5 is a continuation of FIG. 4;

FIG. 6 shows a MOS to which a fourth embodiment of the present invention is applied.
FIG. 4 is a cross-sectional view showing a part of a manufacturing process of a field effect transistor.

FIG. 7 is a sectional view showing a part of a manufacturing process of a conventional MOS field effect transistor.

FIG. 8 is a cross-sectional view showing a part of the manufacturing process of the conventional MOS field effect transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 4 Active region 6, 6a Low impurity concentration silicon layer 7, 7a Single crystal silicon 8, 8a Amorphous silicon 9, 9a Low impurity concentration silicon layer 10 Gate insulating film 12 Gate electrode 21 Silicon substrate 25 Gate electrode 26 Gate insulating film 28 Source and drain regions 29,29a Silicon layer 30,30a Single crystal silicon 31,31a Amorphous silicon 32,32a Silicon layer 33 Metal silicide

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/786 H01L 29/78 301P 618A F term (Reference) 5F040 DA06 DA18 DB01 DC01 EC01 EC07 EC13 ED01 ED03 ED04 EE05 EF02 EH02 EK01 EK05 FA03 FB02 FB04 FC06 FC07 FC09 FC19 FC22 5F043 AA11 BB04 5F045 AA06 AB02 AB03 AB04 AB32 AB33 AB34 AC01 AD07 AD08 AD09 AD10 AE17 AE19 AF03 DB03 EB15 HA14 HA15 HA16 5F052 AA11 DA02 DBA EE14 EE32 FF02 FF23 GG02 GG12 GG28 GG32 GG34 GG37 GG44 GG47 GG52 HJ01 HJ13 HJ23 HK05 HK09 HK13 HK21 HK34 HK37 HK40 HM15 NN62 NN65 NN66 PP01 PP10

Claims (5)

[Claims] A first region where a surface of a single crystal semiconductor layer formed over a semiconductor substrate is exposed; and a second region where a surface of the single crystal semiconductor layer is not exposed. A deposition step of depositing a semiconductor layer using a simple CVD method, and a selective etching step of selectively etching and removing only the semiconductor layer formed on the second region among the semiconductor layers deposited in the deposition step And a method of manufacturing a semiconductor device. 2. The first region is a region where a surface of a single crystal silicon layer is exposed, and the second region is a region where an insulating film such as a silicon oxide film or a silicon nitride film is exposed. The depositing step is performed by using the non-selective CVD method.
A step of epitaxially growing single crystal silicon in the region and depositing amorphous silicon in the second region. The selective etching step is performed by wet etching with an etching solution containing hydrofluoric acid and nitric acid. 2. The method according to claim 1, further comprising the step of selectively etching and removing only the amorphous silicon layer formed thereon. 3. The first region is a region where the surface of a single crystal silicon layer is exposed, and the second region is a region where an insulating film such as a silicon oxide film or a silicon nitride film is exposed. The depositing step is performed by using the non-selective CVD method.
And depositing amorphous silicon in the second region, and then crystallizing only the amorphous silicon layer deposited in the first region by annealing. The selective etching process includes hydrofluoric acid and nitric acid 2. The method according to claim 1, further comprising the step of selectively etching and removing only the amorphous silicon layer formed on the second region by wet etching with an etchant. 4. The composition of the etching solution is hydrofluoric acid (49
Wt% HF-containing) 0.5 to 1.5 vol%, water 5-15% by volume, nitric acid (70 wt% HNO ₃ content) 30-50 vol%, characterized in that from 30 to 50 vol% acetic acid A method for manufacturing a semiconductor device according to claim 2. 5. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device forming an analog circuit.
The method for manufacturing a semiconductor device according to any one of the above.