JPH05226356A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the width of a base and, at the same time, to lower the parasitic resistance of the base by simultaneously growing an epitaxial layer and second side wall conductive layer after forming a first side wall conductive layer in the opening of a semiconductor substrate. CONSTITUTION:After successively forming a first insulating layer 2, first conductive layer 3, and second insulating layer 4 on a semiconductor substrate 1 of one conductivity type, an opening 5 is formed to the surface layer of the substrate 1. Then first side wall conductive layer 6 is formed on the side wall of the opening 5 to a height higher than the thickness of the layer 2 and lower than the uppermost edge of the layer 4. Thereafter, an epitaxial base layer 7 of the reverse conductivity type is formed on the surface of the substrate 1 exposed in the opening 5 and, at the same time, a second side wall conductive layer 8 is formed on the surface of the layer 6. Finally, a side wall insulating layer 9 is formed on the surface of the layer 8 and an emitter diffusion layer 11 is formed in the layer 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to an improvement of a method of manufacturing a self-aligned bipolar transistor which is effective for miniaturization of elements.

The advanced information processing society is developing more and more, and the existence of higher speed computers is required. For this purpose, it is desired to increase the speed of integrated circuit elements, which are the basic parts of computers, and to increase the speed of transistors, especially bipolar transistors, which are the constituent elements of these integrated circuit elements.

The present invention is used in these industrial fields.

[0004]

2. Description of the Related Art FIG. 5 is an explanatory view of a conventional example. In the figure, 24 is a silicon (Si) substrate, 25 is the first silicon dioxide.
(SiO ₂ ) film, 26 is polycrystalline silicon (poly Si) film, 27 is second
SiO ₂ film, 28 is an opening, 29 is a sidewall poly-Si film,
30 is an epitaxial base layer.

FIG. 5 shows a sectional structure of a conventional self-aligned bipolar transistor having an extremely shallow epitaxial base layer. As shown in Fig. 5 (a), Si substrate
A first SiO ₂ film 25, a boron-doped poly-Si film 26, and a second SiO ₂ film 27 are sequentially deposited on the surface 24 by a CVD method, and a Si film is formed using a resist film (not shown) as a mask. An opening 28 reaching the surface of the substrate 24 is formed.

Next, as shown in FIG. 5B, the opening 28
In order to connect the epitaxial base layer 30 of the opposite conductivity type on the Si substrate 24 exposed in FIG. The film 29 is selectively grown.

[0007]

In order to operate the bipolar transistor at high speed, it is necessary to improve the cutoff frequency (f _T ) and reduce the parasitic capacitance and the parasitic resistance.

Among these, in the present invention, when attention is paid particularly to the improvement of the cutoff frequency and the reduction of the parasitic resistance of the base due to the reduction of the base width, in order to increase the speed of the bipolar transistor, first, the base width is increased. Is made as thin as possible to shorten the base transit time of the carrier, improve the cutoff frequency, and lower the base parasitic resistance.

However, in the conventional transistor forming technology, there is a trade-off relationship between making the base width thin and making the base parasitic resistance low, and it is not possible to achieve both at the same time.

This is because in the conventional transistor forming technique, the formation of the base layer and the formation of the base extraction electrode are achieved by the same epitaxial polySi forming technique.

That is, as shown in FIG. 5B, in order to reduce the parasitic resistance of the base, the sidewall poly Si film 29 serving as the base extraction electrode is widened so that the sidewall poly Si formed by selective epitaxial growth is used. If the film 29 is made thick, the thickness of the epitaxial base layer 30 is also made thick at the same time.

On the contrary, as shown in FIG. 5C, the epitaxial base layer is formed to have a narrow base width.
When the thickness of 30 is reduced, the width of the side wall poly-Si film 29 of the base extraction electrode is also narrowed and the base parasitic resistance is increased.

Therefore, it is desirable to achieve both and form a faster bipolar transistor. Therefore, the present invention is provided for the purpose of eliminating the above-mentioned drawbacks and ameliorating the problems.

[0014]

FIG. 1 illustrates the principle of the present invention. In the figure, 1 is a semiconductor substrate, 2 is a first insulating layer, 3 is a first conductive layer, 4 is a second insulating layer, 5 is an opening, 6 is a first sidewall conductive layer, and 7 is an epitaxial layer. A base layer, 8 is a second sidewall conductive layer, 9 is a sidewall insulating layer, 10 is a second conductive layer, and 11 is an emitter diffusion layer.

FIG. 1 shows means for solving the problem. As shown in FIG. 1B, first, the first sidewall conductive layer 6 is formed, and then, as shown in FIG. Two
The sidewall conductive layer 8 is formed on the first sidewall conductive layer 6, and at the same time, the epitaxial base layer 7 for forming the base diffusion layer is formed on the semiconductor substrate 1 in the opening 5.

In this way, the width of the base extraction electrode is equal to that of the film thickness of the first sidewall conductive layer 6 and that of the epitaxial base layer 7 formed next, that is, the second sidewall conductive layer 8 grown at the same time. Because it is decided by the sum of thickness,
If the thickness of the first sidewall conductive layer 6 is properly determined, the thickness of the epitaxial base layer 7 can be made sufficiently thin.

Moreover, at the same time, the thickness of the side wall conductive layer 6 + 8, which becomes the base extraction electrode, can be made sufficiently thick. That is, as shown in FIG. 1 (a), the object of the present invention is to arrange a first insulating layer 2, a first conductive layer 3 and a second insulating layer 4 in this order on a semiconductor substrate 1 of one conductivity type. Stacked, the second
Of the insulating layer 4, the first conductive layer 3 and the first insulating layer 2 by etching to form an opening 5 reaching the surface layer of the semiconductor substrate 1, and FIG. As shown, a step of forming the first sidewall conductive layer 6 on the sidewall of the opening 5 to a height higher than that of the first insulating layer 2 and lower than at least the uppermost end of the second insulating layer 4. , Fig. 1 (c)
As shown in FIG. 2, the semiconductor substrate 1 exposed in the opening 5
A step of forming an epitaxial base layer 7 of opposite conductivity type on the upper surface and a second sidewall conductive layer 8 covering the first sidewall conductive layer 6 at the same time, and as shown in FIG. A step of forming a sidewall insulating layer 9 in the opening 5 so as to cover the second sidewall conductive layer 8, and the epitaxial base layer 7 in the opening 5 as shown in FIG. And the step of forming the emitter diffusion layer 11 therein.

[0018]

With the means for solving the above-mentioned problems, the method of manufacturing a self-aligned transistor effective for miniaturization of a device is improved by first forming a self-aligned transistor in an opening of a semiconductor substrate.
After the sidewall conductive layer is formed, the epitaxial base layer and the second sidewall conductive layer are grown simultaneously, so that the base width can be made thin and the base parasitic resistance can be made low.

[0019]

2 to 4 are schematic cross-sectional views in order of the processes of first to third embodiments of the present invention relating to a bipolar transistor.

In the figure, 13 is a Si substrate, 14 is the first SiO ₂
15 is a first poly-Si film, 16 is a second SiO ₂ film, 17 is an opening, 18 and 18 'are first sidewall poly-Si films, 19 is an epitaxial base layer, and 20 is a second Sidewall poly
Si film, 20 'is poly-Si film, 21 is sidewall SiO ₂ film, 22
Is a second poly-Si film, and 23 is an emitter diffusion layer.

First, a first embodiment in which the present invention is applied to manufacture of a bipolar transistor will be described with reference to FIG. As shown in FIG. 2 (a), C is formed on the p-type Si substrate 13.
The first SiO ₂ film 14 by the VD method was continuously grown to a thickness of about 1,500 Å, and the first poly-Si film 15 doped with boron was continuously grown to a thickness of about 3,000 Å. Poly Si
The film 15 is patterned by a resist mask and removed by etching.

Then, the second SiO ₂ film 16 formed by the CVD method is removed.
It grows on the entire surface of the Si substrate 13 to a thickness of 3,000Å. After that, anisotropic etching by RIE is performed using a resist (not shown) as a mask to form the second SiO ₂ film 16 and the first poly-Si.
The film 15 and the first SiO ₂ film 14 are continuously removed by etching,
An opening 17 for the element formation region that reaches the surface layer of the Si substrate 13 is formed.

Up to this point, the process is the same as the above-mentioned conventional technique, but the subsequent steps are the essential part of the present invention. Figure 2
As shown in (b), poly-Si
After coating the film to a thickness of about 300 to 1,000 Å and then applying resist to the entire surface, anisotropic etching of the resist is performed to remove the resist except the opening 17, and the inside of the opening 17 is removed. Only leave resist.

Next, the poly-Si film is etched to remove the poly-Si film exposed on the surface layer, and further over-etched to remove the poly-Si film existing on the side wall of the second SiO ₂ film 16.
Remove up to Si film.

Next, after removing the resist, polySi
Anisotropic etching of the film was performed to remove the Si substrate 13 in the opening 17.
At the same time that the upper poly-Si film is removed, at least the second SiO ₂ film higher than the first SiO ₂ film 14 is formed on the side wall inside the opening 17.
A first sidewall poly-Si film 18 made of a poly-Si film having a height lower than the uppermost end of 16 is formed.

The above process is performed according to the "first SiO ₂ film 14".
The purpose is to form a "sidewall of the conductor, which is located at a height higher than at least the uppermost end of the second SiO ₂ film 16", and another method may be used.

For example, after forming a poly-Si film on the entire surface, over-anisotropic etching is performed, and the first SiO ₂ film is suddenly formed.
The sidewalls of the poly-Si film may be formed at a height higher than 14 and lower than at least the second SiO ₂ film 16.

At this time, the Si substrate surface other than the poly Si sidewall in the opening 17 is etched by the amount of over-etching and becomes concave, but due to the optimized conditions, the characteristics are inferior to those of the above method. Although it does, the device can still be formed.

As shown in FIG. 2C, in the opening 17,
The second sidewall poly-Si film 20 is selectively grown to a thickness of about 200 to 1,000 Å so as to cover the first sidewall poly-Si film 18, and at the same time, the Si substrate exposed at the bottom of the opening 17 is formed. An epitaxial base layer 19 is grown on 13.

As shown in FIG. 3D, by the CVD method,
A SiO ₂ film is grown to a thickness of 3,000 Å on the Si substrate 13, and anisotropic dry etching by RIE is performed to cover the second sidewall poly-Si film 20 and form a sidewall SiO ₂ film 21.

As shown in FIG. 3E, the second poly-Si film is formed.
Approximately 1,000Å on the entire surface of the Si substrate 13 by filling 22 with the opening 17
After forming to a thickness of, the resist is patterned as a mask to form an emitter electrode 34.

In order to form the emitter diffusion layer 23 on the Si substrate 13, arsenic ions (As ⁺ ) are implanted into the second poly-Si film 22 by an ion implantation method at an acceleration voltage of 40 keV and a dose amount of 1 × 10 ¹⁶ / cm ² . Then, heat treatment is performed at 1,050 ° C for 2 seconds in an oxygen (O ₂ ) atmosphere.

By this heat treatment, the above-mentioned second poly-Si film is formed.
The arsenic impurities in 22 are diffused into the epitaxial base layer 19 to form the emitter diffusion layer 23, and the bipolar IC,
Alternatively, the bipolar transistor of the present invention in a MOSIC or BiCMOSIC device is completed.

Next, a second embodiment of the present invention will be described with reference to FIG. The steps shown in FIGS.
This is exactly the same as the step shown in FIGS. 2A and 2B of the first embodiment.

As shown in FIG. 3 (c), the selective growth of the second sidewall poly-Si film 20 'is performed by changing the growth conditions.
The second side wall poly-Si film 20 'is grown on the second SiO ₂ film 16 and, as shown in FIG.
A resist film (not shown) is buried in 17 and then etched to form a second sidewall poly-Si film 20 as in the first embodiment.

After this, the steps shown in FIGS. 3D to 3F are exactly the same as the steps shown in FIGS. 2C to 2E.
Further, a third embodiment of the present invention will be described with reference to FIG.

The step shown in FIG. 4A is exactly the same as the step shown in FIG. 3A of the second embodiment. As shown in Fig. 4 (b), a poly-Si film is deposited on the Si substrate 13 by the CVD method to about
After coating to a thickness of 0 to 1,000 Å, this poly
Anisotropic dry etching is performed on the Si film to form a first
Forming a sidewall poly-Si film 18 '.

After this, the steps shown in FIGS. 4 (c) to 4 (f) are exactly the same as the steps shown in FIGS. 3 (c) to 3 (f).
Unlike the process shown in FIGS. 1 to 3, the process shown in FIG. 4 does not use selective growth. As a result, compared to the process using selective growth, this process that does not use selective growth is a little longer, but it also has the advantage of not using a special technique called selective growth.

[0039]

As described above, according to the present invention,
After first forming the first sidewall conductive layer in the opening of the semiconductor substrate, the epitaxial base layer and the second sidewall conductive layer are selectively grown at the same time to reduce the base width and lower the base parasitic resistance. The object of the present invention can be achieved at the same time, and a high-speed bipolar transistor can be formed.

As a result, the present invention largely contributes to the development of a bipolar transistor in a highly integrated and ultra-miniaturized integrated circuit.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of the present invention.

2A to 2C are schematic cross-sectional views in order of the processes of the first embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view in order of the steps of a second embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view in order of the steps of a third embodiment of the present invention.

FIG. 5 is an explanatory diagram of a conventional example.

[Explanation of symbols]

In the figure, 1 semiconductor substrate 2 first insulating layer 3 first conductive layer 4 second insulating layer 5 opening 6 first sidewall conductive layer 7 epitaxial base layer 8 second sidewall conductive layer 9 sidewall insulation Layer 10 Second conductive layer 11 Emitter diffusion layer 13 Si substrate 14 First SiO ₂ film 15 First poly Si film 16 Second SiO ₂ film 17 Openings 18, 18 'First sidewall poly Si film 19 Epitaxial base layer 20 Second sidewall poly-Si film 20 'Poly-Si film 21 Side-wall SiO ₂ film 22 Second poly-Si film 23 Emitter diffusion layer

Claims (1)

[Claims] 1. A first conductive layer (2), a first conductive layer (3) and a second insulating layer (4) are sequentially stacked on a semiconductor substrate (1) of one conductivity type, The second insulating layer (4), the first conductive layer (3) and the first insulating layer (2) are removed by etching to form an opening (5) reaching the surface layer of the semiconductor substrate (1). The step of forming the first side wall on the side wall of the opening (5) to a height higher than the first insulating layer (2) and lower than the uppermost end of the second insulating layer (4). A step of forming a wall conductive layer (6), and an epitaxial base layer (7) of opposite conductivity type on the semiconductor substrate (1) exposed in the opening (5) and at the same time the first sidewall Forming the second sidewall conductive layer (8) over the conductive layer (6), and covering the second sidewall conductive layer (8) through the opening.
Including a step of forming a sidewall insulating layer (9) in (5) and a step of forming an emitter diffusion layer (11) in the epitaxial base layer (7) in the opening (5). A method of manufacturing a semiconductor device, which is characterized.