JPH05219032A - Switching circuit - Google Patents

Abstract

PURPOSE:To provide the switching circuit which securely informs an opposite- side device that data are switched. CONSTITUTION:The switching circuit equipped with a switch 6 which selects one normal route between two routes is equipped with an all-'1' signal generating circuit 9 which generates an all-'1' signal, a time setting circuit 10 which passes the all-'1' signal for a time of specific frame length by actuating a route changeover switch 7, and an exclusive OR circuit 3 which exclusively ORs an input signal and the all-'1' signal. Further, the circuit is equipped with a data verifying circuit 2 which verifies the data of the output signal of the exclusive OR circuit 3, a multiplexing circuit 1 which multiplexes respective information signals such as data and a flag, a CRC adding circuit 4 which adds CRC codes to the multiplexed data, the route changeover switch 7 which is a manual switch, a delay circuit 8 which delays the state change information of this route changeover switch 7, and a switching control circuit 5 which controls the switching of the switch 6 with the output of the delay circuit 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching circuit, and more particularly to a switching circuit suitable for route switching of a PCM cache relay information transmission device.

[0002]

2. Description of the Related Art Conventionally, this type of switching circuit has a system in which a route in which no abnormality is detected is selected based on the data verification result of each route, and one of the routes is forcibly selected by a route changeover switch. ing. As shown in FIG. 2, the input signal A is cyclically sent with necessary data arranged in time slots having a frame structure.

When the input signal A is input to the multiplexing circuit 1, it is also input to the data verification circuit 2. In the data verification circuit 2, a CRC test is performed in frame units,
The test result is output as a frame unit 12 signal g, and the multiplex circuit 1 superimposes the test result on the bit position of the data defect flag. Further, when the result of the continuous verification of four frames becomes defective, the signal m is output, which becomes one element of the switching control. A CRC code is added to the multiplexed data by the CRC adding circuit 4 and the data is connected to the switch 6.

In the switching control circuit 5, a switching logic is calculated from the data test result of the input signal A and the data test result of the input signal B, and the result is output to the switch 6 as the switching signal P to switch the input signal. Output as an output signal. The route changeover switch 7 directly acts on the changeover logic performed by the changeover control circuit 5, forcibly determines the changeover signal P, and operates the changeover device 6.

[0005]

In the conventional switching circuit, in the state of automatic switching, the data test result is flagged in the frame format to notify the opposite device that the data is invalid. In the manual switching by the route changeover switch, the flag is not set in the frame format, and the mechanical switching is simply performed, so it is not possible to know when the switching was performed in the opposite device, or whether there was a real switching. Fall into.

Further, as a special case, the switching by the route changeover switch in the state where the input signal A and the input signal B are in frame synchronization is performed by the opposite device even though the frame synchronization is achieved. The contents were completely different, and there was probably a risk of causing a malfunction if the connection between the front and back was broken.

[0007]

SUMMARY OF THE INVENTION It is an object of the present invention to improve the disadvantages of the conventional example, and in particular to provide a switching circuit capable of reliably notifying the opposite device of data switching.

[0008]

According to the present invention, in a switching circuit equipped with a switch for selecting one normal route from two routes, an all "1" signal generating circuit for generating all "1" signals and a route switching. A time setting circuit that allows all "1" signals to pass for a predetermined frame length when the switch is activated, an exclusive OR circuit that calculates an exclusive OR of the input signal and all "1" signals, and this exclusive logic A data verification circuit for verifying the output signal of the sum circuit, a multiplexing circuit for multiplexing each information signal such as a data flag, a CRC adding circuit for adding a CRC code to the data after the multiplexing, and a route change switch for a manual switch. A delay circuit for delaying the state change notification of the route changeover switch, and a switching control circuit for controlling the switching of the switcher by the output of the delay circuit, It adopts a cormorant configuration. This aims to achieve the above-mentioned object.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram of a switching circuit according to an embodiment of the present invention. The overall signal flow is as follows: input signal A, input signal B
Is output by the switch 6 as the output signal C.
The all "1" signal generation circuit 9 constantly generates a signal of "1". The time setting circuit 10 fixes the output u at the “1” level unless the route changeover switch 7 starts up, and when the route changeover switch 7 starts up, the gate is opened for a certain set frame length time. The output t of the all "1" signal generation circuit 9 is directly output as the output u and is connected to one input of the exclusive OR circuit 3. In the exclusive OR circuit 3, since the output u is always at "1" level, the input signal A and the input signal B are output as they are and become the signal f or the signal j.

If an all "1" signal is input, the signal is inverted with respect to the input signal A or the input signal B by the exclusive OR operation, and the signal is completely different from the input signal.

The data verification circuit 2 applies CR to the signal f or j in frame units sent cyclically.
The C test is performed, the pass / fail result in units of frames is output as g or k, and is superimposed as a data defect flag at a predetermined bit position in the multiplexing circuit 1. Further, in the case of the 4-frame continuous verification failure, the signal m from the data verification circuit 2
Alternatively, n is output and used as a logical element in the switching control circuit 5 as one element of switching control.

The CRC adding circuit 4 adds a CRC code to the multiplexed data to form a frame format and outputs the frame format to the switch 6. The switching control circuit 5 monitors the data verification results m and n, and switches to a normal route when a continuous 4-frame verification failure is detected. The condition for abnormal recovery is when the continuous four-frame verification becomes good from the abnormal detection state.

The switch 6 is switched by a switching signal P from the switching control circuit 5. The route changeover switch 7 can set a state of route selection and an automatic state, and has a configuration in which priority is given to the data verification result when the route is selected. At the time of setting the route selection, the data defect flag is superimposed on the multiplexing circuit 1, and the state notification signal q of the route changeover switch 7 is delayed by about 4 frames so that the defect flag is surely received by the opposite device. The delay circuit 8 is connected.

[0014]

As described above, according to the present invention,
By controlling the data failure flag to be set in the frame format in response to the change in the state of the route changeover switch, it becomes possible to reliably notify the opposite device of the data switching. Therefore, in the opposite device, From a certain point in time, the data with the data defect flag is input, it is judged that the data is invalid, and then the normal data is input, which means that the reliability of the entire system can be improved. It is possible to provide an excellent switching circuit that has never been provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

[Explanation of symbols]

 1 Multiplexing circuit 2 Data verification circuit 3 Exclusive OR circuit 4 CRC addition circuit 5 Switching control circuit 6 Switching device 7 Route changeover switch 8 Delay circuit 9 All "1" signal generation circuit 10 Time setting circuit

Claims (1)

[Claims] 1. A switching circuit having a switching device for selecting one normal route from two routes, an all "1" signal generating circuit for generating all "1" signals, and a predetermined frame length when a route changeover switch is activated. A time setting circuit that passes all "1" signals only for a time, an exclusive OR circuit that calculates the exclusive OR of the input signal and all "1" signals, and a data test of the output signal of this exclusive OR circuit. Data verification circuit, a multiplexing circuit that multiplexes each information signal such as a data flag, a CRC adding circuit that adds a CRC code to the data after multiplexing, a route changeover switch of a manual switch, and a state change of this route changeover switch. A switching circuit comprising: a delay circuit for delaying notification and a switching control circuit for controlling switching of the switcher by an output of the delay circuit.