JPH01318379A - Picture signal decoding method - Google Patents

Abstract

PURPOSE:To hold a picture signal of a frame just preceding the frame, where error occurs, without extending a frame memory by outputting the picture signal of the just preceding frame, which is used for inter-frame decoding of a received picture signal, to a holding means. CONSTITUTION:A difference signal (b) from a transmission line and the picture signal of the preceding frame from a frame memory 2 are inputted to a decoding means 1, and this means 1 adds them to reproduce the picture signal inputted to the transmission side and outputs it to the frame memory 2 and an error detecting means 3. This picture signal is delayed in the frame memory 2 by one frame and is outputted to the decoding means 1 and a holding means 4, and the presence or the absence of error is detected by the error detecting means 3, and the detection result is outputted to the holding means 4. The holding means 4 holds and outputs the picture signal of the preceding frame when error is detected by the error detecting means 3. Thus, the picture signal of the frame just preceding the frame where error occurs can be held without extending the frame memory though error exists in the picture signal.

Description

[Detailed Description of the Invention] [Summary] Regarding the image signal decoding method, even if there is an error in the image signal, the image signal of one frame before the frame in which the error occurred can be retained without adding a frame memory. In this case, the image signal is decoded using the image signal of the previous frame from the frame memory and the difference information sent from the transmitting side, and an error in the decoded image signal is detected. An image signal decoding method in which an image signal of a previous frame l is held and outputted, wherein an output of a frame memory is used as the decoded output to be held.

(Industrial Application Field) The present invention relates to an image signal decoding method, and in particular, when an error is detected in a decoded image signal, the image signal of one frame before the frame in which the error was detected is retained and outputted. This invention relates to a signal decoding method.

When an image signal with a small difference value between two consecutive frames, such as an image signal from a video conference, is inter-frame encoded, decoded, and transmitted/received, the difference value between two consecutive frames is stored in the frame memory of the transmitter and the receiver. It is assumed that the image data match. However, an error occurred on the transmission path on the receiving side,
If an error occurs in the image difference signal, the image data stored in the frame memories on the transmitting side and the receiving side will become inconsistent. At this time, if you place the image data without matching it,
Since an image containing an error will be displayed on a display means such as a monitor, if an error is detected in the received image signal on the receiving side, the updating of the displayed image signal will be stopped and the image data in the frame memory will be updated. Correct mistakes.

[Conventional technology]

A conventional image decoding device is shown in FIG. 3, and a correspondence diagram between an image decoded signal and an error detection code is shown in FIG.

In the figure, a decoder 61 inputs a difference signal from a transmission path, adds the difference signal to a predicted signal, and generates an image decoded signal f.
is output to a decoding frame memory 62, an error detector 63, and a holding frame memory 64.

The decoding frame memory 62 delays the input image decoded signal by one frame, and sends it to the decoder 61 as a predicted signal.
It is output to. The error detector 63 detects the presence or absence of an error in the input image decoded signal and outputs an error signal g to the holding circuit 65. The holding frame memory 64 delays the input image decoded signal f by one frame and outputs the delayed image decoded signal to the holding circuit 65. The holding circuit 65 inputs the error signal g and the image decoded signal delayed by one frame, and holds and outputs the image signal of one frame before the frame in which the error was detected. At this time, as shown in FIG. 4, when the image decoded signal f of the Nth frame output from the decoder 61 is input as is to the holding circuit 65, the error detector 63 detects an error in the Nth frame and holds it. When it is output to the circuit, the image decoded signal of the Nth frame has already been input to the holding circuit C. Therefore, even if the image decoded signal is held immediately after an error is detected, the image containing the error will be held. Therefore, the image decoded signal f decoded by the decoder 61 is delayed by one frame in the one frame delay frame memory 64 and output as an image signal. In this way, even if an error occurs in the Nth frame by delaying the image decoded signal f by one frame, the holding circuit
If the image decoded signal is held immediately after inputting the frame error signal, a normal image of one frame before the frame in which the error was detected can be held.

[Problems to be Solved by the Present Invention] As described above, in the conventional image decoding device, when an error is detected, the error is detected in order to prevent the image signal of the frame in which the error is detected from being output. The image signal of the detected frame is output after being delayed by one frame by the frame memory. Therefore, it becomes necessary to add one frame memory for holding, which is unnecessary during normal operation, resulting in a problem that the circuit configuration of the decoding device becomes larger.

Therefore, it is an object of the present invention to make it possible to hold the image signal of one frame before the frame in which the error occurred, without adding a frame memory even if there is an error in the image signal.

[Means to solve the problem]

The first part shows a diagram of the principle of the present invention. At this time, the decoding means 1 inputs the difference signal from the transmission line and the image signal of the previous frame from the frame memory 2, and reproduces the image signal input to the transmitting side by adding the difference signal from the frame memory 2. It is output as a decoded signal to the frame memory 2 and error detection means 3. The frame memory 2 receives the image decoded signal, delays it by one frame, and outputs it to the decoding means 1 and the holding means 4. The error detection means 3 inputs the image decoded signal, detects whether there is an error in the image decoded signal, and stores the detection result in the error detection means 4.
It is output to. When the error detection means 3 detects an error, the holding means 4 does not output the image signal inputted from the frame memory 2, but holds and outputs the image signal of the previous frame.

Furthermore, one frame delay means can also be used as the frame memory 2.

[Effect]

The image signal a of the previous frame used for interframe decoding of the received image signal is output to the holding means 4, and error detection is performed from the decoded image signal C.

Therefore, the image of one frame before the frame in which the error has occurred can be held without providing a new frame memory.

(Example〕 A detailed description will be given below based on the embodiments shown in the drawings.

The decoding means 1 in FIG. 1 corresponds to the adder 11 in FIG.
The frame memory 2 in Figure 1 is the frame memory 2 in Figure 2.
1, the error detection means 3 in FIG. 1 corresponds to the parity check circuit 31 in FIG. 2, and the holding means 4 in FIG. 1 corresponds to the subtracter 41. AND circuit 42. frame memory 4
3. This corresponds to the part consisting of the adder 44.

In FIG. 2, a separator 51 inputs the multiplexed differential signal, parity information, and switching signal from the upstream transmission path, separates them, and outputs them. The difference signal separated by the separator 51 is input to the adder 11, the parity information is input to the parity check circuit 31, and the switching signal is input to the selector 53. The adder 11 adds the predicted signal to the input difference signal, reproduces the image signal input to the transmitting side, and outputs it as an image decoded signal C. Adder 1
The image decoded signal C output from the frame memory 21
and is input to the intraframe memory 52 and parity check circuit 31. The frame memory 21 delays the manually generated image decoded signal by one frame and outputs it to the selector 53 as an interframe prediction signal, and outputs it to the holding means 4 as the image decoded signal a delayed by one frame. There is. The intra-frame memory 52 delays the input image decoded signal C by one pixel and outputs it to the selector 53 as an intra-frame predicted signal. The selector 53 inputs the inter-frame predicted signal and the intra-frame predicted signal, and outputs the intra-frame predicted signal to the adder 11 only when an intra-frame encoded signal is input by the switching signal. The parity check circuit 31 creates parity information from the input image decoded signal C, and compares the parity information with the parity information input from the separator 51. If they match, 1 is set, and if they do not match, 0 is set as the error signal d. It notifies the sending side and also outputs it to the holding means 4.

In the holding means 4, first, a subtracter 41 detects the difference value between the image decoded signal a delayed by one frame and the predicted signal S output from the frame memory 43, and outputs AN as the difference signal.
It is output to the D circuit 42. The AND circuit 42 receives the error signal d input from the parity check circuit 31 and the difference signal, and outputs the difference signal to the adder 44 only when the error signal d is 1. Furthermore, when the error signal d is 0, the AND circuit 42 outputs O as a difference signal. When the adder 44 receives the difference signal and the predicted signal S, it adds the two signals together and outputs the result to the frame memory 43 as well as to a display means such as a monitor. In the frame memory 43, the input signal is delayed by one frame and output as a prediction signal S to the subtracter 41 and the adder 44.

〔Effect of the invention〕

As described above, according to the present invention, the image signal (prediction signal) of the previous frame output from the frame memory used for interframe decoding of the image signal is used as the image output.

Therefore, in the present invention, even if there is an error in the image signal, the image signal of one frame before the frame in which the error occurred can be held without adding a frame memory.

[Brief explanation of the drawing]

Fig. 1 is a diagram of the principle of the present invention, Fig. 2 is an embodiment of the present invention, Fig. 3 is a conventional image decoding device, and Fig. 4 is a correspondence diagram of an image signal and an error detection signal. ...Decoding means 2...Frame memory 3.
...Error detection means 4...Holding means ll...Additional X
unit 21... frame memory 31... parity check circuit 41... subtracter 42... AND circuit 43
...Frame memory 44...Adder 51...Separator 52...Intra-frame memory 53...
Selector 61...Decoder 62...Decoding frame memory 63...Error detector 65...Holding means 64...Holding frame memory

Claims (1)

[Claims] 1. Decoding the image signal (c) using the image signal (a) of the previous frame from the frame memory (2) and the difference information (b) sent from the transmitting side ( 1) and, when an error in the decoded image signal (c) is detected (3), a predetermined image signal is held (4) and outputted. (e) In the image signal decoding method, the holding (4) An image signal decoding method characterized in that the image signal (a) of the previous frame from the frame memory (2) is used as the predetermined image signal to be processed.