JPH0595345A - Changeover circuit - Google Patents

Abstract

PURPOSE:To improve the reliability of a system by delaying changeover control in order to inform a frame with a defect flag set to a receiver side with a signal from a route changeover switch so as to inform the changeover of data to an opposite device. CONSTITUTION:A route changeover switch 6 takes precedence over the condition of propriety of the result of data check in the state of A route selection and B route selection set by the route changeover switch 6. Then a time width setting circuit 3 outputs a '1' pulse by 4 frames when the route changeover switch 6 selects the A route or the B route, and OR circuits 4a, 4b OR data check result (f) or (j) to set the state as if the data check result were defective and multiplexer circuits 1a, 1b superimpose it as a defective flag. The defect flag is a signal for state notice of the route changeover switch 6 to be connected to a changeover control circuit 8 so that the defect flag is surely delivered to the opposite device. A delay circuit 7 is provided to give a delay of nearly 4 frames to a switch state signal (q).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching circuit for selecting one normal route from two routes, and more particularly to a switching circuit for realizing route switching of a PCM carrier relay information transmission device.

[0002]

2. Description of the Related Art Conventionally, a switching circuit of this type has a system in which a route in which no abnormality is detected is selected on the basis of a data verification result of each route, and one of the routes is forcibly selected by a route changeover switch. ..

An example of a conventional switching circuit will be described with reference to FIG. As shown in FIG. 2, input signal A has necessary data arranged in time slots having a frame structure and cyclically sent. This input signal A is the multiplex circuit 11a.
Is input to the data verification circuit 12a at the same time. Then, in the data verification circuit 12a, CRC (Cyclic Redundancy Ch) is performed for each frame.
eck) test is performed, the test result is output as a signal f in frame units, and the test result is superimposed on the bit position of the defective flag in the multiplexing circuit 11a. Further, when the result of the continuous verification of four frames becomes defective, the signal m is output, which becomes one element of the switching control.

A CRC code is added to the data multiplexed by the CRC adding circuit 13a and the data is connected to the switch 16. The switching control circuit 15 calculates the switching logic from the data test result of the input signal A and the data test result of the input signal B,
The result is output to the switch 16 as the switching signal p, the input signal is switched, and the output signal c is output. Then, the route changeover switch 14 directly acts on the changeover logic performed by the changeover control circuit 15 to forcibly determine the changeover signal p and operate the changeover device 16.

In FIG. 2, a shows the input signal A, b is the signal after multiplexing, d is the input signals B and e, the signals after multiplexing, j is the data test result, and m and n are 4 frames consecutive failures. A signal, q indicates a switch state signal.

[0006]

In this conventional switching circuit, a defective flag is set in the data format of the data verification result to notify the opposite device that the data is invalid. In the switching, the mechanical switching is simply performed without setting a flag in the data format, so that there is a problem in that it is impossible to know when the switching was performed in the opposite device or whether the switching actually occurred. Further, as a special case, when switching is performed by the route changeover switch in the state where the frame synchronization of the input signal A and the input signal B is matched, the content of the data is completely different although the frame synchronization is matched in the opposite device. Therefore, there is a problem that there is a risk of causing malfunction.

[0007]

The switching circuit according to the present invention comprises two switching circuits.
In the switching circuit that selects one normal route from the routes,
A multiplexing circuit that multiplexes each information bit such as data and flag, a data verification circuit that performs data verification of the input signal of each information such as the above data and flag, and a time width that sets the time to add the flag for a predetermined frame length A setting circuit, a logical sum circuit for performing a logical sum operation of the data verification result by the data verification circuit and the output of the time width setting circuit, and a CRC adding circuit for adding a CRC code to the data multiplexed by the multiplexing circuit. , The route changeover switch of the manual switch, the delay circuit for delaying the state change notification of this route changeover switch, and the switching control of the output signal of the above data verification circuit controlled by the delayed switch state signal from this delay circuit. A switching control circuit for performing the switching and a switching device for switching according to a signal from the switching control circuit are provided.

[0008]

In the present invention, the defective flag is controlled to be set in the data format in response to the state change of the route changeover switch.

[0009]

1 is a block diagram showing an embodiment of a switching circuit according to the present invention. In FIG. 1, 1a and 1b are multiplex circuits for multiplexing information bits such as data and flags,
Reference numerals 2a and 2b are data verification circuits that perform data verification of input signals of each information such as this data and flags. Reference numeral 3 is a time width setting circuit that sets a time for adding a flag for a predetermined frame length. 4a and 4b are data verification. A logical sum circuit for performing a logical sum operation of the data test result by the circuits 2a, 2b and the output of the time width setting circuit 3 is a CRC addition circuit for adding a CRC code to the data after multiplexing by the multiplexing circuits 1a, 1b. , 6 is a route changeover switch of a manual switch, 7 is a delay circuit for delaying the state change notification of the route changeover switch 6, 8 is a data verification circuit 2a controlled by a delayed switch state signal from the delay circuit 7, A switching control circuit that controls switching of the output signal of 2b, and a switch 9 that performs switching by a signal from the switching control circuit 8.

Then, a indicates an input signal A, b is a signal after multiplexing, c is an output signal, d is an input signal B, e is a signal after multiplexing, f is a data test result, g is a defective flag, and h is h. Is C
RC code, j is a data test result, k is a defective flag, l is a CRC code, m and n are four consecutive frame defective signals, p is a switching signal, q is a switch state signal, r is a delayed switch state signal, s indicates a switch state signal, and t indicates a "1" pulse for 4 frames.

Next, the operation of the embodiment shown in FIG. 1 will be described. First, in the overall signal flow, one of the input signal A and the input signal B is selected as the output signal c by the switch 9 and output. Then, the data verification circuits 2a and 2b perform a CRC test on the input signal A and the input signal B on a frame-by-frame basis sent cyclically, and the pass / fail result on a frame-by-frame basis is used as a data test result f or a data test result j. Is output as a defect flag and superimposed on the bit position of a predetermined time slot in the multiplexing circuits 1a and 1b. Also,
When the 4-frame consecutive verification result is defective, the 4-frame consecutive defective signal m or n is output and used in the logical operation in the switching control circuit 8 as one element of the switching control. CRC
CR is applied to the multiplexed data in the additional circuits 5a and 5b.
The C code is added and the frame is output to the switch 9. Then, the switching control circuit 8 monitors the 4-frame continuous failure signal m, n which is the data verification result, and switches to the normal route when the continuous 4-frame verification failure is detected. At that time, if the switching destination is defective in verification, the switching is not performed. Furthermore, if the switching destination recovers abnormally in this state, switching is performed. Here, the condition for the abnormality recovery is the case where the continuous 4-frame verification is good from the state of the abnormality detection. The switch 9 is a switching signal p from the switching control circuit 8.
To switch.

Next, the route changeover switch 6 can set three states of A route selection, B route selection, and automatic.
In the state where the A route is selected and the B route is selected, the route changeover switch 6 is prioritized over the condition of the quality of the data verification result. Then, the time width setting circuit 3 outputs a "1" pulse for four frames when the route changeover switch 6 is in the state of selecting the A route or the B route, and the data verification result f is obtained by the OR circuits 4a and 4b. Alternatively, the logical sum of j and j is taken to make it as if the data verification result is defective and superposed as a defective flag in the multiplex circuits 1a and 1b. The delay circuit 7 adds a delay of about 4 frames to the switch status signal q which is a status notification signal of the route changeover switch 6 connected to the switching control circuit 8 so that the superimposed defect flag is surely transmitted to the opposite device. Is provided.

[0013]

As described above, according to the present invention, the defective flag is set in the data format in response to the change of the state of the route changeover switch.
This has the effect of reliably notifying the opposite device of data switching. In the opposite device, data with a defective flag is input from a certain point, it is determined that this data is invalid, route switching occurs after that, and normal data is input. It also has the effect of improving reliability.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a switching circuit according to the present invention.

FIG. 2 is a block diagram showing an example of a conventional switching circuit.

[Explanation of symbols]

 1a, 1b Multiplexing circuit 2a, 2b Data verification circuit 3 Time width setting circuit 4a, 4b Logical sum circuit 5a, 5b CRC addition circuit 6 Route changeover switch 7 Delay circuit 8 Changeover control circuit 9 Changer

Claims (1)

[Claims] 1. A switching circuit that selects one normal route from two routes, a multiplexing circuit that multiplexes each information bit such as data and a flag, and data that performs a data test of an input signal of each information such as the data and a flag. A test circuit, a time width setting circuit that sets a time for adding a flag for a predetermined frame length, and a logical sum circuit that performs a logical sum operation of the data test result by the data test circuit and the output of the time width setting circuit. CRC is added to the data after being multiplexed by the multiplexing circuit.
A CRC adding circuit for adding a code, a route changeover switch of a manual switch, a delay circuit for delaying the state change notification of this route changeover switch, and the data verification controlled by a delayed switch state signal from this delay circuit. A switching circuit comprising: a switching control circuit that controls switching of an output signal of the circuit; and a switching device that performs switching by a signal from the switching control circuit.