JPH05218291A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH05218291A JPH05218291A JP4040317A JP4031792A JPH05218291A JP H05218291 A JPH05218291 A JP H05218291A JP 4040317 A JP4040317 A JP 4040317A JP 4031792 A JP4031792 A JP 4031792A JP H05218291 A JPH05218291 A JP H05218291A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- hybrid integrated
- metal substrate
- lead terminal
- conductor pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は混成集積回路装置に関
し、特に金属基板を用いた混成集積回路の構造に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit device, and more particularly to the structure of a hybrid integrated circuit using a metal substrate.
【0002】[0002]
【従来の技術】従来の金属基板を用いた混成集積回路
は、図4に示すように金属基板1をベースと、この金属
基板1上にエポキシあるいはポリイミドなどの樹脂から
なる絶縁層2を介して銅箔を貼付し、次にフォトリソグ
ラフィ法を用いて導体パターン3を形成する。次にハン
ダペースト6をスクリーン印刷により供給し、セラミッ
クチップコンデンサ4、ミニモールドトランジスタ5等
の電子部品を搭載し、リフロー法により基板側電極と電
子部品の電極をハンダ接続する。次に外部リード7を基
板側の端子ランドにハンダ付けを行って完成させる。2. Description of the Related Art A conventional hybrid integrated circuit using a metal substrate has a metal substrate 1 as a base and an insulating layer 2 made of a resin such as epoxy or polyimide on the metal substrate 1 as shown in FIG. A copper foil is attached, and then the conductor pattern 3 is formed by using the photolithography method. Next, the solder paste 6 is supplied by screen printing, electronic parts such as the ceramic chip capacitor 4 and the mini mold transistor 5 are mounted, and the substrate side electrode and the electrode of the electronic part are solder-connected by the reflow method. Next, the external leads 7 are soldered to the terminal lands on the substrate side to complete.
【0003】[0003]
【発明が解決しようとする課題】上述した従来の金属基
板を用いた混成集積回路装置では、チップ抵抗やチップ
セラミックコンデンサ4などのセラミック製のチップ部
品をアルミニウム金属基板1上に搭載する場合、セラミ
ックとアルミニウムの熱膨張係数がそれぞれ6.4×1
0-6/℃;22.9×10-6/℃と異なるため、部品の
サイズが大きくなると熱膨張差に起因するストレスによ
り、ハンダ接続部6にクラック等が発生し、接続の信頼
性が低下するという問題点があった。In the above-mentioned conventional hybrid integrated circuit device using a metal substrate, when a ceramic chip component such as a chip resistor or a chip ceramic capacitor 4 is mounted on the aluminum metal substrate 1, a ceramic is used. And aluminum have a coefficient of thermal expansion of 6.4 × 1
0 -6 / ° C; 22.9 × 10 -6 / ° C, so when the size of the component increases, the stress due to the difference in thermal expansion causes cracks in the solder joint 6 and the connection reliability is improved. There was a problem that it decreased.
【0004】[0004]
【課題を解決するための手段】本発明の要旨は、金属基
板上に絶縁膜を介して形成された導体パターンと、該導
体パターンに接続されるセラミック製の構成部品とを備
えた混成集積回路装置において、上記セラミック製の構
成部品は自らの電極から延在するリード端子を有してお
り、該リード端子が導体パターンに固定されることであ
る。SUMMARY OF THE INVENTION The gist of the present invention is a hybrid integrated circuit comprising a conductor pattern formed on a metal substrate via an insulating film, and a ceramic component connected to the conductor pattern. In the device, the ceramic component has a lead terminal extending from its own electrode, and the lead terminal is fixed to the conductor pattern.
【0005】[0005]
【発明の作用】セラミック製構成部品が導体パターンに
固定される際にセラミックと金属の熱膨張係数差に起因
してストレスが発生しても、リード端子がストレスを吸
収し、固定部に過大な応力は発生しない。When the ceramic component is fixed to the conductor pattern and stress is generated due to the difference in coefficient of thermal expansion between the ceramic and the metal, the lead terminal absorbs the stress and the fixing portion is excessively large. No stress is generated.
【0006】[0006]
【実施例】次に本発明について図面を参照し説明する。
図1は本発明の一実施例の金属基板を用いた混成集積回
路装置を示す断面図である。アルミニウムからなる1.
5mmの厚さの金属基板1上に厚さ約100μmの樹脂
絶縁層2を形成し、更に厚さ18μmの銅箔を貼付け
る。次に、銅箔をフォトリソグラフィ技術を用いてパタ
ーン形成し、導体パターン3を形成する。The present invention will be described below with reference to the drawings.
FIG. 1 is a sectional view showing a hybrid integrated circuit device using a metal substrate according to an embodiment of the present invention. Made of aluminum 1.
A resin insulating layer 2 having a thickness of about 100 μm is formed on a metal substrate 1 having a thickness of 5 mm, and a copper foil having a thickness of 18 μm is attached. Next, the copper foil is patterned using a photolithography technique to form the conductor pattern 3.
【0007】図2の斜視図2示すように、あらかじめ大
型サイズのセラミックチップコンデンサ4は電極にリー
ド端子7をハンダ接続しておく。As shown in the perspective view of FIG. 2, the lead terminals 7 are soldered to the electrodes of the large-sized ceramic chip capacitor 4 in advance.
【0008】次にハンダペースト6をスクリーン印刷法
により基板1上のハンダ付ランドに供給し、前記チップ
コンデンサ4及びミニモールドトランジスタ5を搭載
し、リフロー法によりハンダ接続する。最後に外部リー
ド7をハンダ接続して完成する。Next, the solder paste 6 is supplied to the soldered land on the substrate 1 by the screen printing method, the chip capacitor 4 and the mini mold transistor 5 are mounted, and the solder connection is made by the reflow method. Finally, the external leads 7 are soldered and completed.
【0009】図3は本発明の第2実施例の要部を示す断
面図である。第2実施例は大型セラミックコンデンサ4
に取り付けるリード端子7の高さを、ミニモールドトラ
ンジスタや小型チップ部品の高さより0.5〜1.0m
m以上高く設定することにより、大型セラミックコンデ
ンサ下部にも部品を実装することができるようにしたも
のである。その結果、実装密度が向上し、小形化が可能
となる。FIG. 3 is a sectional view showing the main part of the second embodiment of the present invention. The second embodiment is a large ceramic capacitor 4
The height of the lead terminal 7 to be attached to the
By setting the height higher than m, components can be mounted under the large ceramic capacitor. As a result, the packaging density is improved and the size can be reduced.
【0010】[0010]
【発明の効果】以上説明したように本発明は、大型のセ
ラミックチップコンデンサを金属基板に搭載する場合、
あらかじめ大型セラミックコンデンサに表面実装が可能
なリード端子を接続しておき、これを搭載することによ
り、セラミックコンデンサと金属基板の熱膨張差による
ストレスをリード端子が吸収するので、ハンダ接続部の
信頼性が飛躍的に向上するという効果を有する。As described above, according to the present invention, when a large-sized ceramic chip capacitor is mounted on a metal substrate,
The surface mountable lead terminals are connected in advance to the large ceramic capacitor, and by mounting this, the lead terminals absorb the stress due to the difference in thermal expansion between the ceramic capacitor and the metal substrate, so the reliability of the solder joint is improved. Has the effect of being dramatically improved.
【0011】例えばセラミックチップコンデンサのサイ
ズが12.5mm×10mm×3mmの大きさの場合、
温度サイクル(−55℃〜+125℃)試験で比較する
と、従来のコンデンサを直接金属基板に搭載した構造で
は、160サイクルで約30%不良が発生したのに対
し、本発明の構造では不良の発生は認められなかった。For example, when the size of the ceramic chip capacitor is 12.5 mm × 10 mm × 3 mm,
Comparing in the temperature cycle (-55 ° C to + 125 ° C) test, in the structure in which the conventional capacitor is directly mounted on the metal substrate, about 30% failure occurs in 160 cycles, whereas in the structure of the present invention, the failure occurs. Was not recognized.
【図1】第1実施例を示す断面図である。FIG. 1 is a cross-sectional view showing a first embodiment.
【図2】第1実施例のセラミックチップコンデンサの斜
視図である。FIG. 2 is a perspective view of a ceramic chip capacitor of the first embodiment.
【図3】第2実施例の断面図である。FIG. 3 is a sectional view of a second embodiment.
【図4】従来例の断面図である。FIG. 4 is a sectional view of a conventional example.
1 金属基板 2 絶縁層 3 導体パターン 4 セラミックチップコンデンサ 5 ミニモールドトランジスタ 6 ハンダ 7 外部リード 8 リード端子 1 Metal Substrate 2 Insulating Layer 3 Conductor Pattern 4 Ceramic Chip Capacitor 5 Mini Molded Transistor 6 Solder 7 External Lead 8 Lead Terminal
Claims (1)
導体パターンと、該導体パターンに接続されるセラミッ
ク製の構成部品とを備えた混成集積回路装置において、
上記セラミック製の構成部品は自らの電極から延在する
リード端子を有しており、該リード端子が導体パターン
に固定されることを特徴とする混成集積回路。1. A hybrid integrated circuit device comprising: a conductor pattern formed on a metal substrate via an insulating film; and a ceramic component connected to the conductor pattern.
The above-mentioned ceramic component has a lead terminal extending from its own electrode, and the lead terminal is fixed to a conductor pattern.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4040317A JP2842013B2 (en) | 1992-01-30 | 1992-01-30 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4040317A JP2842013B2 (en) | 1992-01-30 | 1992-01-30 | Hybrid integrated circuit device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH05218291A true JPH05218291A (en) | 1993-08-27 |
JP2842013B2 JP2842013B2 (en) | 1998-12-24 |
Family
ID=12577238
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4040317A Expired - Lifetime JP2842013B2 (en) | 1992-01-30 | 1992-01-30 | Hybrid integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2842013B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000013138A (en) * | 1998-06-18 | 2000-01-14 | Mitsubishi Electric Corp | Array antenna feeding device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01103163A (en) * | 1987-10-15 | 1989-04-20 | Toshiba Corp | Semiconductor rectifier |
-
1992
- 1992-01-30 JP JP4040317A patent/JP2842013B2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01103163A (en) * | 1987-10-15 | 1989-04-20 | Toshiba Corp | Semiconductor rectifier |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000013138A (en) * | 1998-06-18 | 2000-01-14 | Mitsubishi Electric Corp | Array antenna feeding device |
Also Published As
Publication number | Publication date |
---|---|
JP2842013B2 (en) | 1998-12-24 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19980310 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19980922 |