JPH05218040A - Semiconductor device with solder bump - Google Patents

Abstract

PURPOSE:To easily form a solder bump on input/output electrode metal by composing a protective film covering the entire surface of a semiconductor device except an external input/output electrode metal part and a scribing region, and setting a surface roughness of its surface layer to a special value or less. CONSTITUTION:A solder bump 7 is formed directly on external input/output electrode metal 5 formed of the same metal as the material of an inner interconnection 6 for electrically connecting a semiconductor element. In such a semiconductor device 3, protective films 8, 9 covering the entire surface of the device except the metal 5 and a scribing region 2 of the device are formed of at least two types of inorganic series substances. The surface roughness of the substances of the layer 9 on the device is set to Rz<=0.05mum. For example, the films 8, 9 are formed of a CVD-SiO2 semiconductor element protective film 9 and a flat film 9 in which TEOS is used as a material.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device having a solder bump on an external input / output electrode, and more particularly to a structure of a semiconductor device having a solder bump directly formed on an external input / output electrode metal.

[0002]

2. Description of the Related Art A conventional semiconductor device having a structure in which a tin-lead solder bump is directly formed on an external input / output electrode metal is formed by the following two methods.

The first method is to immerse a semiconductor device in a wafer state in a jet type ultrasonic soldering bath, and in the molten solder, apply strong ultrasonic waves to the surface of the semiconductor device in a wafer state, and The cavitation effect caused by removing the oxide layer etc. on the metal surface of the external input / output electrode and directly wetting the clean external input / output electrode metal surface with the solder, and then pulling up the wafer from the jet ultrasonic solder bath ,
The solder bumps are formed only on the external input / output electrode metal that is wet with the solder.

In the second method, first, a semiconductor device in a wafer state is put into a sputtering device, the entire surface of the semiconductor device on the wafer is cleaned by RF etching, and then a metallic protective film for preventing oxidation such as tin is formed. , After forming on the entire surface of the wafer, if this wafer is immersed in a jet solder bath,
The external input / output electrode metal with a clean surface that appeared when the anti-oxidation metallic protective film was dissolved in the solder bath got wet with the solder, and then when the wafer was pulled up from the jet solder bath, it got wet with the solder. The solder bumps are formed only with the external input / output electrode metal.

[0005]

Among the conventional methods for manufacturing a semiconductor device in which solder bumps are directly formed on an electrode metal, the first method of manufacturing solder bumps is a wafer state in a molten solder bath. In order to prevent the destruction of the semiconductor element and the wear of the electrode metal due to the application of strong ultrasonic waves to the semiconductor device, it is necessary to cover the surface of the semiconductor device with a substance having a large attenuation rate against ultrasonic vibration such as polyimide. there were. However, even with the polyimide coating this surface, decomposition products generated by the influence of strong ultrasonic waves and heat from molten solder adhere to the external input / output electrode metal, so that the molten solder and external input / output electrode metal There is a problem in that the wettability between the layers decreases, which reduces the solder bump formation rate.

The structure of the semiconductor device of the second method does not apply strong ultrasonic vibration to the semiconductor device. Therefore, a protective film having a large vibration damping rate such as polyimide is not required, and a nitride film for protecting semiconductor elements is used. A semiconductor device having a structure in which only a thin surface protective film such as a film or an oxide film is coated is used. These nitride films and oxide films are often used because they have good coverage for irregularities on the surface to be formed, but conversely, they have the property of faithfully reflecting irregularities due to internal wiring on the semiconductor device on the surface. There is.

However, after immersing such a wafer having large irregularities on the surface of the semiconductor device in a jet solder bath,
When the wafer is pulled up from the jet solder bath, there is a problem that the solder that has entered the recesses on the surface of the semiconductor device remains on the surface of the wafer. There may be a problem that the solder bumps on the external input / output electrodes are bridged with each other.

[0008]

Therefore, in the semiconductor device of the present invention, an inorganic protective film is provided on the surface of the semiconductor device, which is not destroyed or decomposed even with respect to the heat history of the molten solder in the bath.
Further, the surface of the uppermost protective film of the semiconductor device excluding the external input / output electrode portion has a surface roughness of 0.0 so that the unevenness is eliminated.
It has a structure formed of a film flattened to 5 μm or less.

[0009]

The present invention will be described below with reference to the drawings.

FIG. 1 is a vertical sectional view of a semiconductor device according to a first embodiment of the present invention. Semiconductor devices 3 are each divided by a scribe region 2 on a silicon substrate 1, and each semiconductor device 3 has a diffusion layer and internal electrode wiring 4 on the silicon substrate 1, and an external input / output electrode made of aluminum is formed on the diffusion layer. Part 5
And an aluminum internal wiring 6 forming a part of the semiconductor element are formed, and a solder bump 7 of a tin-lead eutectic composition is formed on the input / output electrode portion 5 of aluminum. The semiconductor device protective film 8 of CVD-SiO ₂ and TEOS are formed on the semiconductor device except the region where
The surface roughness of (tetraethoxysilane) as a raw material is 0.
A flat film 9 having a thickness of 05 μm or less is coated.

Next, the manufacturing method of the first embodiment will be described with reference to FIG.
This will be described with reference to FIG. First, diameter 125mm, thickness 60
N ⁻ with a resistance value of about 10 Ω to cm sliced to 0 μm
On the Si substrate 1 by a self-alignment method with one mask
An n-well 10 and a p-well 11 are formed (FIG. 2
(A)). After that, the field oxide film 12 is formed and gate oxidation is performed (FIG. 2B). Then, the first layer p-S
The i film is deposited by the CVD method, and the conductivity type of the gate p-Si portion is changed to the n ⁺ type by diffusing the n type impurity. This p
In order to leave -Si only in the portion that will become the gate, after processing with a plasma etching device, in order to form n ⁺ layer 13 and p ⁺ layer 14 that will become the source and drain, using As and B in this order as a mask, using a photoresist as a mask, Ion implantation is performed (FIG. 2 (c)). The p-channel portion is formed later in order to form the shallow p ⁺ layer by reducing the thermal history after implantation of B as much as possible. Then 700
After the SiO ₂ interlayer insulating film 15 is formed by the high temperature CVD method at ˜900 ° C., the second p-Si film 16 is deposited. After patterning by reduction projection exposure using the positive resist as a mask and processing the second layer p-Si16 by a parallel plate type dry etching device (FIG. 2D), the passivation film 1 is formed.
7 is formed and the contact hole 18 is opened to form the diffusion layer 4 (FIG. 2E). Aluminum is vapor-deposited thereon to a thickness of 1 μm and processed by a parallel plate type dry etching device to form aluminum external input / output electrode portions 5 and aluminum wirings 6 (FIG. 2 (f)).

Subsequently, on the semiconductor device 2 excluding the portion where the solder bumps 7 are formed, the laminated surface is reformed to improve the formability of a film made of TEOS as a raw material and having a flat surface, and the semiconductor element is protected. As a step, a semiconductor element protection film 8 of CVD-SiO ₂ is deposited (FIG. 3A).

Furthermore, at the formation temperature of 375 ° C., O ₃
A gas having a flow rate ratio of / TEOS of 10.5 is flowed to deposit a flat film 9 having a highly flat surface and using TEOS as a raw material, and the TEOS is entirely etched back on the semiconductor device 3 using RIE to perform TEOS. Film 9 with a flat surface made of
The surface is further flattened to have a surface roughness of 0.05 μm or less. After that, a photoresist was applied to the entire surface of the silicon substrate 1 to cover the parts other than the external input / output electrodes 5. And RI
By taper etching by a combination of E and wet etching, on the external input / output electrode portion 5 of aluminum,
Flat surface film 9 made of TEOS and CVD-Si
The semiconductor element protection film 8 of O ₂ and the flat film 9 made of TEOS and having a flat surface on the scribe region 2 are removed (FIG. 3B).

Thereafter, the semiconductor device 3 is put into a sputtering device for each silicon substrate 1, and the degree of vacuum is 4.0 × 10 ^-7.
The aluminum external input / output electrode 5 was cleaned by applying Ar sputtering for 30 minutes twice in an atmosphere of mmTorr. Then, tin 19 is placed on the entire surface of the silicon substrate 1 including the semiconductor device 3 by 0.5 μm (FIG. 3C).

Finally, the semiconductor device 3 having tin 19 on the entire surface is immersed in a jet type solder bath at a temperature of 210 ° C. for 1 min.
The tin 19 was completely dissolved in the solder bath by leaving it in the bath. Then, N ₂ gas is blown to the position where the semiconductor device 3 is pulled up from the solder bath, and the speed is 10 mm in the same atmosphere.
/ Sec, the Si substrate 1 is pulled up and the solder bumps 7
Are formed (FIG. 3D).

By the above, the solder bumps can be formed on the input / output electrodes without breaking or damaging the surface of the semiconductor device, and the desired structure can be obtained.

FIG. 4 is a vertical sectional view of a semiconductor device according to the second embodiment of the present invention. Semiconductor devices 3 are each divided by a scribe region 2 on a silicon substrate 1, and each semiconductor device 3 has a diffusion layer 4 on a silicon substrate 1 and an external input / output electrode portion 5 made of aluminum on the diffusion layer 4. Aluminum internal wiring 6 forming a part of a semiconductor element is formed, and a solder bump 7 of tin-lead eutectic composition is formed on the external input / output electrode 5 of aluminum. On the semiconductor device except the formed region, CVD-
The semiconductor element protective film 8 of SiO ₂ and the SOG (Spin
On-Glass) film 20 having a flat surface and CV
The surface protective film ₂ of D-SiO ₂ covers the scribe region 2 between the soldering devices 3 and the silicon substrate 1 is directly covered with a film 20 having a flat surface by SOG.

Next, the manufacturing method of the second embodiment is
A description will be given with reference to FIG. 5 focusing on the points different from the embodiment of FIG.

According to the first embodiment, the CVD-Si is formed on the semiconductor device 1 having the aluminum external input / output electrodes 5 and the aluminum internal wiring 6 formed on the diffusion layer 4.
A semiconductor element protective film 8 of O ₂ is formed, and the scribe region 2 is formed.
The upper CVD-SiO ₂ semiconductor element protective film 8 is removed by dry etching (FIG. 5A).

Subsequently, a film 20 having a flat surface by SOG is used.
Is coated on the silicon substrate 1 while rotating the silicon substrate in a wafer state, and then baked (FIG. 5B), and the surface protection film 21 of CVD-SiO ₂ is formed thereon.
After that, apply photoresist to the entire surface of the silicon substrate,
The surface protection film 21 of the CVD-SiO ₂ of the external input / output electrode 5 is covered by using a C ₂ F ₆ gas having a C / F _free gas ratio of 0.38 to 0.42 so as to cover a portion other than the external input / output electrode 5. To etch.

Then, a photoresist is newly applied to the entire surface of the silicon substrate 1 to cover the external input / output electrodes 5 and the area other than the scribe area 2, and the C / F _ferr gas ratio is 0.3.
SOG is preferentially used by using C ₂ F ₆ gas of _{2 to} 0.36.
Remove the flat film 20 on the surface by (FIG. 5C),
Subsequently, C / F _free and C _{2 with a} gas ratio of 0.38 to 0.42
CVD-Si on the scribe region 2 using F ₆ gas
O ₂ surface protection film 21 and CVD on external input / output electrode 5
The semiconductor element protection film 8 of —SiO ₂ is preferentially etched.

After that, the silicon substrate 1 was cleaned in the same manner as in the first embodiment, 0.2 μm of silver 22 was placed thereon (FIG. 5 (d)), and a eutectic crystal containing 1.5% of silver was added. By dipping the silicon substrate 1 together in a solder bath, solder bumps 7 are formed on the external input / output electrode portions 5 (see FIG. 5).
(E)).

In this embodiment, the SO is also on the scribe area 2.
Since it is covered with the flat film 20 made of G, the solder bumps 7 can be stably formed on the external input / output electrodes 5 without the adhesion of solder on the scribe regions 2.

[0024]

As described above, according to the present invention, by adopting the structure in which the surface of the semiconductor device is covered with the film of the inorganic type whose surface is flat, the solder bump can be formed only on the input / output electrode metal. It has the effect of being able to.

[Brief description of drawings]

FIG. 1 is a vertical sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a vertical cross-sectional view showing the manufacturing method of the first embodiment of the present invention.

FIG. 3 is a vertical cross-sectional view showing the manufacturing method of the first embodiment of the present invention.

FIG. 4 is a vertical sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a schematic drawing of a portion different from the first embodiment,
It is a longitudinal cross-sectional view of the manufacturing method of the second embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Scribing region 3 Semiconductor device 4 Diffusion layer 5 External input / output electrode 6 Internal wiring 7 Solder bump 8 Semiconductor element protective film 9 Flat surface film made of TEOS as a raw material 10 n-well 11 p-well 12 Field oxide film 13 n ⁺ layer 14 p ⁺ layer 15 SiO ₂ interlayer insulating film 16 second layer p-Si film 17 passivation film 18 contact hole 19 tin 20 SOG flat surface film 21 surface protection film 22 silver

Claims (2)

[Claims] 1. A semiconductor device in which a solder bump is directly formed on an external input / output electrode metal formed of the same metal as a metal forming an internal wiring for electrically connecting a semiconductor element, The protective film covering the entire surface of the semiconductor device except the metal part of the external input / output electrode and the scribe region of the semiconductor device is made of at least two kinds of inorganic substances, and the inorganic material of the surface layer on the semiconductor device is A semiconductor device with a solder bump, wherein the surface roughness of the base material is R _z ≦ 0.05 μm. 2. A scribe region existing between one semiconductor device and another semiconductor device is filled with an inorganic substance, and the surface of the scribe region and the surface of the inorganic substance are separated from each other. The semiconductor device with solder bumps according to claim 1, wherein the height difference is 2 μm or less.