JPH0521763A - Semiconductor substrate, device and its manufacturing method - Google Patents

Abstract

PURPOSE:To diminish resistance in heat radiation, by forming an insulating layer thinly in an SOI structure, and by using a supporting substrate made of a material having thermal conductivity larger than that of an Si substrate. CONSTITUTION:A silicon oxide film is formed on the surface of an Si substrate 1 in a thermal oxidation step. On the other hand, a silicon film 4 is deposited on an aluminum nitride substrate 3, and the residual strain is attenuated in thermal treatment, and moreover the main face is abraded with a wafer lapping apparatus. In a dust-free condition, the abraded face of the aluminum nitride substrate 3 is directly bonded to the silicon oxide film of the Si substrate 1, and then the substrate is ground and abraded from the Si-substrate side. According to the measurement in heat radiation, the temperature of a semiconductor substrate prepared in this way rises only by 3 deg.C, and the result of effective heat radiation can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate, a semiconductor device, and a method of manufacturing the same, and more particularly to a semiconductor substrate having excellent heat dissipation characteristics, preventing an increase in wiring resistance and a decrease in reliability due to heat generation during operation. The present invention relates to a semiconductor substrate, a semiconductor device, and a method for manufacturing the same, which are configured to enable high current operation, high speed, and high integration of the device.

[0002]

2. Description of the Related Art A structure in which an insulating film is provided on the bottom of a semiconductor layer which constitutes a semiconductor device is called a SOI (Silicon on Insu
known as a solid phase growth method or a liquid phase growth method, an oxygen ion implantation method, a wafer bonding method, etc. (for example, Showa 61).
Proceedings of 4th International Sy, Procedings of 4th International Sy
mposium on Silicon‐on‐Insulator Technology and D
evices, May 6-11, 1990, Montreol "SILICON WAF"
ER‐BONDING PROCESS TECHNOLOGY FOR SOI STRUCTURE
S) etc .. From the viewpoint of defect-free SOI layer, the wafer bonding method is the most practical method and has the structure and manufacturing procedure shown in FIG. A first silicon (Si) substrate 1 having an oxide film 2 on the main surface and a second Si substrate 5 having the same flat main surface are prepared, and b) these are bonded in a dust-free state. Without using a chemical agent, etc., the main surfaces are directly bonded to each other, and heat treatment is performed to strengthen the bonding strength. C) Finally, the back surface of the Si substrate 1 is thinned by grinding and mirror polishing so that A semiconductor substrate 1 having a silicon oxide film 2 can be obtained.The SOI structure obtained by such a manufacturing procedure is most characterized in that the semiconductor layer 1 which constitutes a semiconductor device is a perfect crystal. As a structural feature, a semiconductor device is formed on the insulating film 2. Is constructed,
It can be pointed out that between the respective semiconductor devices forming the integrated circuit, the element can be completely separated by the insulating film, including the path through the bottom semiconductor substrate. Therefore, malfunctions due to α-ray irradiation, interference between adjacent elements called a latch-up phenomenon, etc. can be completely prevented.

[0003]

However, the biggest problem of the SOI structure is that the silicon oxide film is used as the insulating film. In other words, the thermal conductivity of the silicon oxide film is small, and it is two orders of magnitude smaller than that of single crystal Si. Therefore, it is reliable to apply the SOI structure to semiconductor devices that generate heat significantly, such as ultra-high speed and ultra high integration semiconductor integrated circuits. Problems may occur in terms of sex. However, the silicon oxide film is the most excellent as a semiconductor process material, and at present, no alternative material having high heat conductivity and high quality has been found. In order to deal with this problem, a method of reducing the heat radiation resistance by making the film thickness of the silicon oxide film 2 thin may be considered, but in this case, the capacitance between the semiconductor layer 1 and the semiconductor substrate 5 increases. As a result, there is a new defect that the high speed operation of the ultra high speed semiconductor device is hindered.

The object of the present invention is to solve the problems of the prior art described above, to provide excellent heat dissipation characteristics, to prevent an increase in wiring resistance and a decrease in reliability due to heat generation during operation, and It is an object of the present invention to provide a semiconductor substrate and a semiconductor device having a configuration that enables high current operation, high speed, and high integration, and a manufacturing method thereof.

[0005]

The above object is to provide a first substrate, a first thin film provided so as to cover at least the main surface of the substrate, and a first insulating film provided on the thin film. A semiconductor substrate composed of a single crystal semiconductor layer provided on the insulating film, wherein the first substrate has a thermal conductivity higher than that of the single crystal semiconductor layer. Can be achieved by

The basic idea of the present invention is to use a silicon oxide film, which is essential as a semiconductor process material, as an insulating film for SOI structure. However, the silicon oxide film is made thin so as to reduce the heat radiation resistance. In addition, by introducing a method of reducing the capacitance and using a material with a large thermal conductivity as a supporting substrate instead of the semiconductor substrate made of single crystal Si, not only the conventional SOI type semiconductor substrate but also
It is to realize a semiconductor substrate having a heat dissipation effect superior to that of an ordinary single crystal substrate.

Examples of the above-mentioned supporting substrate material having a large thermal conductivity include aluminum nitride, silicon carbide, beryllium oxide and the like. In order to adapt these materials to the semiconductor manufacturing process, the surface of the substrate using these materials may be covered with a thin silicon film and then protected and stabilized.

[0008]

[Function] By adopting a thinner insulating film that constitutes SOI and a supporting substrate made of a material having a higher thermal conductivity than that of a Si substrate, the heat radiation resistance can be greatly reduced. Even in an ultra-high-speed semiconductor device that generates a lot of heat, ultra-high integration is possible.
Also, it is possible to avoid an increase in wiring resistance due to heat generation,
Furthermore, it becomes possible to pursue ultra-high speed operation. Further, the occurrence of parasitic capacitance due to depletion, which has been a problem in the conventional structure when the insulating film is made thin, is basically eliminated by adopting an insulating support substrate. In the case of the structure of the present invention, the insulating film is merely necessary for forming the wafer bonding surface. When using an insulating support substrate, if it is a substrate material whose oxidation resistance is inferior to that of Si, it is necessary to coat it with a silicon thin film or a silicon nitride film in advance, so that The process is also equivalent to the heat treatment process in an inert atmosphere. The coating with the silicon nitride film has a function of preventing harmful impurities that may be contained in the supporting substrate from diffusing into the SOI layer, that is, the semiconductor device.

[0009]

EXAMPLES The contents of the present invention will be described in more detail below with reference to examples. For convenience of description, the description will be made with reference to the drawings, but it should be noted that the drawings show enlarged main parts. Further, in order to simplify the description, the material of each part, the conductivity type of the semiconductor layer, the manufacturing conditions and the like will be specifically illustrated and described in the examples, but the present invention is limited to these examples. is not.

[0010]

[Embodiment 1] FIGS. 1 and 3 are cross-sectional views showing a structure and a manufacturing process of an embodiment of a semiconductor substrate of the present invention. First, a silicon oxide film having a thickness of 50 nm was formed on the surface of a 4-inch diameter single crystal Si substrate 1 having a plane orientation (100), a resistivity of 10 Ωcm, ap conductivity type and a thickness of 525 μm and a diameter of 4 inches. on the other hand,
After a chemical vapor phase reaction of monosilane (SiH ₄ ) at 620 ° C. on an aluminum nitride (AlN) substrate 3 having a thickness of 525 μm and a diameter of 4 inches, a silicon film 4 is deposited to a thickness of 5 μm, and then 1000
Heat treatment is performed under the condition of 2 ° C. for 2 hours to reduce the residual strain, and further, it is installed in a well-known wafer polishing apparatus to measure the mean square surface roughness.
The main surface was polished to have a thickness of 0.5 nm or less. (Note that
The silicon film 4 after the heat treatment was a polycrystalline film having a grain size of about 50 nm). Subsequently, the polishing surface and the silicon oxide film of the single crystal Si substrate are directly bonded in a dust-free state,
Furthermore, after heat treatment for strengthening the adhesiveness is performed at 1000 ° C. for 2 hours, the thickness of the substrate is 1 μm from the Si substrate 1 side by a known grinding method and mechanical / chemical polishing method.
Grinding / polishing was performed by controlling so that At this time, the variation in in-plane Si thickness was within ± 0.5 μm.

Regarding the semiconductor substrate prepared as described above,
In order to examine the heat radiation effect, a resistance element was formed on the Si substrate 1 by a known semiconductor manufacturing method, and the temperature rise due to energization was measured by an infrared microscope. The measurement is performed with the substrate placed on a water-cooled sample table and vacuum suctioned. For comparison, a sample with a resistance element formed on a normal SOI substrate having a silicon oxide film with a thickness of 1 μm inside. Was also measured. As a result, with the power consumption of 70 mW, the temperature rise of the comparative sample reaches 27 ° C.,
In the case of the sample of this example, the temperature rise was only 3 ° C.,
It has been known that it exhibits an excellent heat dissipation effect.

[0012]

Example 2 Aluminum nitride (AlN) in Example 1
A silicon carbide (SiC) substrate was used instead of the substrate 3, and a semiconductor substrate was prepared in the same manner as in Example 1.

As a result of measuring the temperature rise of the resistance element on the semiconductor substrate under the same conditions as in Example 1, the temperature rise was 10 ° C. or less, and the result showing excellent heat dissipation characteristics as compared with the conventional SOI substrate was obtained. Was obtained. Note that beryllium oxide (beryria; BeO) having similar thermal conductivity is used instead of the silicon carbide substrate.
Similar results were obtained with.

[0014]

[Embodiment 3] FIG. 4 is a cross-sectional view showing a manufacturing procedure of another embodiment of the present invention. In this embodiment, before a thermal oxide film is formed on a single crystal Si substrate 1, a desired oxide film is formed on the substrate. An example of patterning according to the configuration of the semiconductor device is shown. In this case, a) First, the patterning depth is set to 0.2 μm, patterning is performed, and then thermal oxide films 2 and 21 are formed to a thickness of 0.1 μm, and chemical vapor deposition using disilane (Si ₂ H ₆ ) is performed. The reaction is performed at a temperature of 525 ° C. to form a 2 μm thick amorphous film on the thermal oxide film 21.
After depositing the Si film 6, a heat treatment at 800 ° C. was performed. In this state, the surface roughness of the amorphous Si film 6 showed extremely good flatness. Next, the surface was further planarized by mechanical polishing so that the mean square roughness was 0.5 nm or less, and then a silicon nitride film 7 having a thickness of 50 nm was deposited on the surface by chemical vapor phase reaction at 780 ° C. . b) Subsequently, the substrate obtained above was directly bonded to the separately prepared aluminum nitride supporting substrate 3 covered with the silicon film 4, and further subjected to an adhesion strengthening heat treatment. c) Further, as in the case of Example 1, the Si substrate 1 was thinned by grinding and mechanical / chemical polishing. As a mechanical / chemical polishing method, the polishing rate of the thermal oxide film was set to that of silicon. By using a well-known selective polishing method that is orders of magnitude slower than that, polishing was stopped when the thermal oxide film 21 was exposed, and the islands 1 of the Si substrate were selectively left.

By applying the manufacturing method of the above procedure, as shown in FIG. 4c), the ultra-thin (0.15 μm) single crystal Si substrate 1 which is insulated and isolated from each other by the oxide film 21 is previously formed at a desired position. It was possible to obtain a semiconductor substrate arranged and configured. The thickness of the island 1 of the single crystal Si substrate can be controlled by setting the patterning depth and the film thickness of the thermal oxide film to predetermined values. A heat resistance test was conducted using the resistance element formed on the island 1 of the single crystal Si substrate obtained above, but it showed only a temperature rise of 10 ° C or less, and the conventional SOI
Compared with the case of the structure, it showed significantly better heat dissipation characteristics.

[0016]

[Embodiment 4] FIG. 5 is a cross-sectional view showing a manufacturing procedure of still another embodiment of the present invention. In the case of Embodiment 3, the single crystal Si substrate 1 is patterned according to the structure of a desired semiconductor device. Although the thermal oxide film 21 is formed on the entire surface, this embodiment shows an example in which the oxide film 21 is selectively formed in accordance with the configuration of the desired semiconductor device to form the element isolation insulating film. Oxide film 21
For the formation of the
The substrate 1 may be selectively etched to a desired depth in advance, and then the oxide film 21 may be selectively formed.

A) First, after the oxide film 21 is selectively formed, the silicon nitride film used for the selective oxidation is removed, and then a silicon thermal oxide film having a thickness of 7 nm is formed, and then the first gate oxide film 22 is formed. And Next, the gate oxide film 22 in the bipolar transistor region is selectively removed to partially expose the surface of the Si substrate 1 and the polycrystalline silicon film 8 of 150 nm thick and arsenic of high concentration and the 200 nm thick Tungsten silicide film 9
Was deposited on the entire surface. Then, the polycrystalline silicon film 8
And a tungsten silicide film 9 are selectively left, and an electrode wiring according to a desired circuit configuration is formed, and then an oxide film by chemical vapor reaction is deposited on the entire surface to form a surface stabilizing film.
It was 10. Further, after depositing the Si film 6 by chemical vapor reaction, heat treatment and planarization polishing, the silicon nitride film 7 is formed.
Was deposited. Here, the deposited film thickness of the Si film 6 is 5 μm.
set to m.

B) Next, the aluminum nitride supporting substrate 3 coated with the silicon film 4 prepared separately in the same manner as in Example 3 and the substrate obtained above are bonded and further bonded. Strengthening heat treatment and thinning were performed. As the mechanical / chemical polishing method, the selective polishing method is used as in the case of the third embodiment, and when the surface of the thermal oxide film 21 is exposed, the polishing is stopped to selectively remove the islands of the Si substrate. 1 was left.

In the semiconductor substrate having the structure of this embodiment, the ultra-thin (0.15 μm) single crystal isolated from each other by the oxide film 21 is used.
It was possible to construct a semiconductor substrate which was constructed by arranging the Si substrate 1 in a desired position in advance and a buried wiring made of a refractory metal silicide film under the semiconductor substrate. In this embodiment, an example in which a two-layer film composed of the refractory metal silicide film 9 and the polycrystalline silicon film 8 is used as the embedded wiring is shown, but unless the embedded wiring and the semiconductor substrate are directly connected, It may be a refractory metal or a silicified film thereof.

The semiconductor substrate of this embodiment also has
A heat generation test was conducted using a resistance element configured on island 1 of a single crystal Si substrate, but it showed only a temperature rise of 10 ° C or less, and the conventional SOI
The heat dissipation characteristics were far superior to the structure.

[0021]

Fifth Embodiment A MOS transistor is formed in the region of the Si substrate 1 of the semiconductor substrate (FIG. 4c) obtained in the third embodiment by using a known MOS transistor manufacturing process. In addition,
In the case of this example, the thickness of the Si substrate 1 was set to be 80 nm.

In the transistor of this embodiment, Si
Since the thickness of the substrate is less than the thickness of the depletion layer, the effect of the drain strong electric field on the gate electric field, so-called two-dimensional effect, is effectively alleviated, and the improvement of the short channel effect and the increase in current can be realized. In addition, heat generation was also significantly reduced compared to the conventional SOI structure transistor.

[0023]

[Embodiment 6] FIG. 6 is a sectional view showing the structure of an embodiment of the semiconductor device of the present invention. In the case of this embodiment, the fourth embodiment
Using the semiconductor substrate obtained in step 5, the arsenic added to the polycrystalline silicon film of the buried wiring in FIG. 5 is diffused from the connection region on the bottom surface of the Si substrate 1 by the heat treatment process after the bonding process to form the N-type high concentration region 19. Formed. Then area 19
In the region of the Si substrate 1 in which the substrate is formed, the base diffusion layer 20, the N-type high-concentration emitter diffusion layer 23, the base extraction electrode composed of the stacked film of the polycrystalline silicon film 16 and the tungsten silicide film 17, are formed by a known bipolar transistor manufacturing method, The wiring interlayer insulating film 18, the emitter electrode 23, etc. were formed. Where Si
The buried wirings 8 and 9 directly connected to the substrate 1 region function as collector extraction electrodes. Further, the source diffusion layer 14, the drain diffusion layer 15, the gate insulating film 11, the polycrystalline silicon film 12 and the tungsten silicide film 17 are stacked on each other in the Si substrate 1 region which is not directly connected to the buried wiring by a known MOS transistor manufacturing method. Form the gate electrode, source electrode 25, etc. composed of a film, and
We have created a semiconductor device in which OS transistors are mixed.

In the semiconductor device manufactured as described above, since the collector extraction electrode can be formed on the bottom surface of the semiconductor layer, the area occupied by the transistor can be reduced to about 2/3 or less as compared with the conventional structure. Also, in the MOS transistor, since the embedded electrode can be used as the second gate electrode, the entire Si substrate 1 can be controlled as a current path, and the drivable current is 5 times or more that of the conventional structure. I was able to Furthermore, the semiconductor device of this example is superior in heat dissipation characteristics to the SOI transistor having the conventional configuration, and the heat generation can be significantly reduced.

[0025]

Seventh Embodiment FIG. 7 shows another embodiment of the semiconductor device of the present invention. In this case, first, a) a normal Si substrate 1 in which a semiconductor device is formed on a single crystal semiconductor substrate by a known method is bonded to a separately prepared polishing support jig 30 with wax 31, and thinned by grinding and polishing from the back surface. Turned into Here, the selective polishing method described in Example 5 was used for polishing, and the polishing was terminated when the bottom surface of the element isolation insulating film 21 was exposed, and only the active region of the Si substrate 1 was left selectively. b) Then, the above Si
The substrate 1 is adhered using an adhesive 32 to a 500 μm thick silicon carbide substrate 3 having a surface-stabilized insulating film thinly deposited on the polished surface by a low temperature chemical vapor reaction in a plasma atmosphere and then the surface is polished flat. Then, the wax was peeled off from the polishing support jig by heating at 100 ° C., and further, the wax was washed to completely remove the wax to complete the semiconductor device.

In the semiconductor device of this embodiment, unlike the case of the above-described sixth embodiment, the Si substrate 1 is subjected to a semiconductor device manufacturing process including all high-temperature heat treatments before being bonded to the high thermal conductivity substrate 3. Therefore, it is not necessary to change the conventional manufacturing conditions for controlling the impurity distribution of the diffusion layer and the like, and it has been possible to easily and inexpensively manufacture a semiconductor device having an SOI structure having excellent heat dissipation characteristics.

[0027]

Eighth Embodiment FIG. 8 is a block diagram of a computer using the semiconductor device of the present invention. That is, this is an example in which the semiconductor device of the present invention is applied to a high-speed large-scale computer in which a plurality of processors 500 for processing instructions and operations are connected in parallel. Since the high-speed semiconductor device embodying the present invention has excellent heat dissipation and can be highly integrated, a processor 50 for processing instructions and operations
0, storage control device 501, main storage device 502, etc.
It could be configured on a chip of 0-30 mm. The processor 500, the storage controller 501, and the data communication interface 503 composed of a compound semiconductor integrated circuit are mounted on the same water-cooled substrate 506. In addition, the data communication interface 5
03 and the data communication control device 504 are mounted on the same water-cooled board 507. These water-cooled substrates 506 and 507, and the main storage device 502
The water-cooled board on which is mounted is mounted on a board having a side of about 50 cm or less, and a central processing unit 508 of a large-scale computer is formed. The data communication in the central processing unit 508, the data communication between a plurality of central processing units, or the data communication between the data communication interface 503 and the board 509 on which the input / output processor 505 is mounted is indicated by double-ended arrow lines in the figure. This is done via the illustrated optical fiber 501.

In this computer, semiconductor devices such as a processor 500 for processing instructions and operations, a storage control device 501, a main storage device 502, and the like operate in parallel at high speed, and data communication is performed using light as a medium. As a result, the number of instruction processings per second can be significantly increased.

[0029]

As described above, by incorporating the semiconductor substrate and the semiconductor device and the manufacturing method thereof into the contents of the constitution of the present invention, the problems which the prior art has had are solved and the heat dissipation characteristics are excellent. Provided are a semiconductor substrate and a semiconductor device having a configuration capable of preventing an increase in wiring resistance and a decrease in reliability due to heat generation during operation and enabling high current operation, high speed, and high integration of the semiconductor device, and a manufacturing method thereof. We were able to. Also,
In the semiconductor device according to the present invention, a highly reliable SOI structure can be provided without increasing parasitic capacitance.
This has the effect of completely preventing malfunctions due to radiation of rays and interference between adjacent elements called a latch-up phenomenon.

[Brief description of drawings]

FIG. 1 is a sectional view showing a configuration of an embodiment of a semiconductor substrate of the present invention.

FIG. 2 is a sectional view showing the structure of a conventional semiconductor substrate.

FIG. 3 is a cross-sectional view showing the manufacturing process of the semiconductor substrate according to the first embodiment of the present invention.

FIG. 4 is a sectional view showing a manufacturing process of a semiconductor substrate according to a third embodiment of the present invention.

FIG. 5 is a sectional view showing a manufacturing process of a semiconductor substrate according to a fourth embodiment of the present invention.

FIG. 6 is a sectional view showing a manufacturing process of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 7 is a sectional view showing a manufacturing process of a semiconductor device according to a seventh embodiment of the present invention.

FIG. 8 is a configuration diagram showing a computer configuration of an eighth embodiment using the semiconductor device of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Single crystal Si substrate, 2 ... 1st insulating film which comprises SOI structure, 3 ... Support substrate with a larger thermal conductivity than a semiconductor substrate, 4 ... 1st thin film which protects a support substrate, 5 ... Si support Substrate, 6 ... Si film, 7 ... Silicon nitride film, 8 ... Buried polycrystalline Si film forming wiring, 9 ... Buried metal silicide film forming wiring, 10 ... Wiring protective insulating film, 11 ... Gate insulating film , 12 ...
Polycrystalline Si film forming wiring, 13 ... Metal silicide film forming wiring, 14 ... Source diffusion layer, 15 ... Drain diffusion layer, 16 ...
Polycrystalline Si film forming wiring, 17 ... Metal silicide film forming wiring, 18 ... Wiring protective insulating film, 19 ... Collector diffusion layer, 20
… Base diffusion layer, 21… Thermal oxide film, 22… Gate oxide film, 23
... emitter diffusion layer, 24 ... emitter electrode, 25 ... source electrode, 26 ... extraction electrode, 30 ... polishing support jig, 31 ... wax,
32 ... Adhesive, 500 ... Processor that processes instructions and operations, 5
01 ... Storage control device, 502 ... Main storage device, 503 ... Data communication interface, 504 ... Data communication control device, 505 ... Input / output processor, 506, 507 ... Ceramic substrate, 508 ... Central processing unit, 509 ... Input / output processor implementation Substrate, 510 ...
Optical fiber for data communication.

Claims (6)

[Claims] 1. A first substrate, a first thin film provided so as to cover at least the main surface of the substrate, a first insulating film provided on the thin film, and provided on the insulating film. A semiconductor substrate comprising a single crystal semiconductor layer, wherein the first substrate has a thermal conductivity higher than that of the single crystal semiconductor layer. 2. The semiconductor substrate according to claim 1, wherein the first substrate is made of any one of aluminum nitride, silicon carbide and beryllium oxide. 3. The semiconductor substrate according to claim 1, wherein the single crystal semiconductor layer is a single crystal semiconductor layer separated from each other by a second insulating film. 4. A semiconductor film, a refractory metal film or a refractory metal silicide film at least between the single crystal semiconductor layer and the first insulation film or in the first insulation film. The semiconductor substrate according to claim 3, further comprising a wiring layer configured. 5. A semiconductor device, which is formed on the single crystal semiconductor layer of the semiconductor substrate according to claim 3 or 4. 6. A step of polishing a semiconductor substrate on which a semiconductor device is formed by polishing from the back surface to form a thin layer, and a supporting substrate having a thermal conductivity higher than that of the semiconductor substrate and the semiconductor substrate at least with an adhesive layer interposed therebetween. A method of manufacturing a semiconductor device, comprising the steps of: