JPH05167073A - Semiconductor integrated circuit device and fabrication thereof - Google Patents

Abstract

PURPOSE:To set and control threshold voltage of a MOS transistor to a desired one by voltages applied to buried gate electrodes by constructing the buried gate electrode through a buried insulating film on the lower part of a single crystal ultra-thin film semiconductor layer completely insulated from a support substrate. CONSTITUTION:A title device is constructed that buried gates 61, 62 are buried at the bottom of a single crystal semiconductor layer through a buried gate insulating film 51. Hereby, threshold voltages of the transistors 1 and 2 are set mutually independently by setting voltages applied to the buried gate electrodes 61 and 62 to arbitrary values. More specifically such threshold voltages for SOI transistors are controlled independently for each transistor or for each group of transistors irrespective of the substrate impurity concentration, gate material, and gate insulating film thickness, and the like.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing method thereof, and more particularly to a semiconductor integrated circuit device in which a semiconductor circuit including a MOS transistor is integrated on an insulating film and a manufacturing method thereof.

[0002]

2. Description of the Related Art A structure in which a semiconductor circuit is formed on an insulating film is an SOI (silicon on insulator "Silic
On On Insulator ”) structure, it is not easily affected by α-ray irradiation, has no latch-up phenomenon, and has the advantages of large current and high-speed operation due to complete depletion of the ultra-thin semiconductor layer. . SOI MOS transistor
The SOI transistor (hereinafter abbreviated as SOI transistor) has a structure shown in the cross-sectional view of FIG. The single crystal semiconductor layer 3 (source diffusion layer 7, drain diffusion layer 8) of the SOI transistor is formed on the support substrate 1 with the insulating film 2 interposed therebetween, and the element isolation insulating film 4 and the gate are formed on the single crystal semiconductor layer 3. The insulating film 5, the gate electrode 6, the source electrode 9, the drain electrode 10 and the like are formed. S
In the OI transistor, the single crystal semiconductor layer 3 is extremely thin, about 100 nm, and under the condition that the gate voltage applied to the gate electrode 6 causes complete depletion, it is about 1.5 times that of the conventional transistor. It has the feature that a large current can be obtained.

On the other hand, the threshold voltage value of the SOI transistor tends to be lower than that of a normal transistor, and it is difficult to control the threshold voltage value to an arbitrary value. Therefore, inverters, flip-flop circuits, memory circuits,
There was a limitation in forming other logic circuits. MO
The control of the threshold voltage value of the S-transistor is generally based on the impurity concentration of the single crystal semiconductor layer 3, the work function of the gate electrode 6, the thickness of the gate insulating film 5 and the substrate voltage applied to the supporting substrate 1. However, since the single crystal semiconductor layer 3 of the SOI transistor is extremely thin, the threshold voltage value can be controlled very little by the impurity concentration. To raise the impurity concentration to the extreme
It causes a decrease in transfer conductance. Gate electrode 6
Setting the material and the thickness of the gate insulating film 5 for each desired transistor causes the manufacturing process to be complicated, resulting in a decrease in manufacturing yield and an increase in manufacturing cost.

H. Lim and J. Fossum, Threshold Voltage of Thin-Film Silicon-on Insulator (S-O-I) MOSFE
T, s Eye E E E Transaction Action
Electron Device ED-30 Vol. 10, No. 12
Pages 44 to 12511 October 1983 "Thresho
ld Voltage of Thin-Film Silicon-on Insuator (SOI)
MOSFET's; IEEE Trans. Electron Devices, vol. ED-3
As reported in 0, No. 10, pp1244-12511 (Oct) 1983, the method of controlling the threshold voltage value by the substrate voltage applied to the supporting substrate is usually a thick silicon oxide film of about 1 μm as the insulating film 2. Since it is used, the effect cannot be obtained unless a high voltage is applied, and it cannot be said to be practical to use a high voltage. It is also impossible to control the substrate voltage for each specific transistor in the integrated circuit.

[0005]

Therefore, the main object of the present invention is to determine the threshold voltage value of a MOS transistor formed in the SOI structure, the impurity concentration of the SOI transistor, the gate electrode material, the gate insulating film thickness. , And the voltage applied to the supporting substrate regardless of the applied voltage. That is, it is to realize a semiconductor integrated circuit device that can be controlled without lowering the breakdown voltage and the transfer conductance. Another object of the present invention is to control the threshold voltage value of the MOS transistor to an arbitrary value for each desired transistor or each desired transistor group when the semiconductor integrated circuit device formed in the SOI structure includes a plurality of MOS transistors. It is to realize a semiconductor integrated circuit device that can be set. Still another object of the present invention is to achieve the above-mentioned object, and to realize a method of manufacturing a semiconductor integrated circuit device which is relatively simple in manufacturing process, has a high manufacturing yield, and can economically manufacture an SOI transistor. ..

[0006]

In order to achieve the above object, the present invention provides a semiconductor integrated circuit device in which a semiconductor integrated circuit including a MOS transistor is formed in an SOI structure, in which an active layer of the MOS transistor is formed. A buried gate is formed below the crystalline semiconductor layer via a buried insulating film.
A semiconductor integrated circuit device is constituted by providing a structure having a gate electrode and providing a circuit means for setting the embedded gate electrode to a desired potential. By connecting a predetermined voltage to the embedded gate electrode based on the circuit configuration, the desired threshold voltage value is controlled for each desired transistor or each transistor group. For example, in the above complementary transistor, each buried gate electrode of the p-channel transistor group is set to a positive desired potential, and each buried gate electrode of the n-channel transistor group is
The ground electrode is fixed to zero potential or a desired potential negative with respect to the source potential. Further, depending on the configuration circuit, different potentials may be set for the same channel transistor group.

The manufacturing of the semiconductor integrated circuit device having the buried gate electrode according to the present invention is based on the manufacturing process of the MOS type transistor, the element isolation insulating film, the buried gate insulating film, the buried gate electrode and the wiring protection. Manufacture a multi-layered semiconductor substrate in which a first semiconductor substrate manufactured up to the film and a second semiconductor substrate having an oxide film formed on the main surface are bonded together, and the back side of the first semiconductor substrate of the multi-layered semiconductor substrate is ground. Further, the main surface of the multi-layer structure semiconductor substrate is newly obtained by thinning by polishing and selectively polishing the first semiconductor substrate up to the surface defined by the back surface of the element isolation insulating film. Note that a thick semiconductor film is deposited on the wiring protection insulating film to enable the above bonding, and the surface is processed to be ultra-flat by mechanical / chemical polishing, and then the bonding step is performed. By selective polishing up to the surface defined by the back surface of the element isolation insulating film, the single crystal ultra-thin film semiconductor layer having a film thickness of about half of the element isolation insulating film is left in a state of being separated from each other, A buried gate electrode is formed in a lower region of the single crystal ultra thin film semiconductor layer with a structure buried via a buried gate insulating film. The buried gate electrode extends to the lower part of the element isolation insulating film, and an opening may be provided at a desired portion of the element isolation insulating film to connect it to the main surface side of the multilayer structure semiconductor substrate in a circuit manner. A MOS transistor is formed on the exposed single crystal ultra-thin film semiconductor layer by a known manufacturing process.

[0008]

According to the semiconductor integrated circuit device of the present invention, since the embedded gate electrode is formed below the single crystal ultra-thin film semiconductor layer completely insulated and separated from the supporting substrate, the single gate ultra-thin semiconductor layer is formed. MOS composed of crystalline ultra-thin semiconductor layer
The threshold voltage value of the transistor can be set and controlled to a desired value by the voltage applied to the embedded gate electrode. Taking an n-channel transistor as an example, in order to increase the threshold voltage value, a voltage higher than a certain negative value is applied to the buried gate electrode so that the lower portion of the single crystal ultra-thin semiconductor layer is in an accumulation state. To do. In order to reduce the threshold voltage value, a voltage above a certain positive value may be applied to bring it into an inversion state. The above threshold voltage value control can be performed for each desired transistor or each desired transistor group, and thus a semiconductor integrated circuit device configured with an SOI transistor having a desired threshold voltage value is configured and is effective as a component device of an electronic device. It will be a means.

In the control of the threshold voltage value of the semiconductor integrated circuit device according to the present invention, the impurity concentration of the single crystal semiconductor layer may be a desired concentration, that is, a low impurity concentration of 10 ¹⁶ / cm ³ or less, and the source / drain breakdown voltage. It is possible to avoid a decrease in transfer conductance. Further, it is not necessary to set the gate electrode material and the gate insulating film thickness for each desired transistor, and therefore, there is no fear that the manufacturing process is complicated, the manufacturing yield is lowered, and the manufacturing cost is increased. The semiconductor integrated circuit device according to the present invention has the characteristics of a conventional SOI transistor, namely, excellent α-ray irradiation resistance due to the transistor being completely separated from the semiconductor substrate by an insulating film, and a complete solution from the latch-up phenomenon. Moreover, the features such as large current and high speed operation due to complete depletion of the ultra-thin semiconductor layer are not impaired.

[0010]

EXAMPLES The present invention will be described in detail below with reference to examples. Embodiment 1 FIGS. 2 to 5 are sectional views sequentially showing manufacturing steps of a first embodiment of a semiconductor integrated circuit device according to the present invention. Figure 2
In the step shown in (1), first, a thermal oxide film having a thickness of 300 nm is selectively formed on the main surface of a single crystal silicon (Si) substrate 30 having a plane orientation (100), a resistivity of 10 Ωcm, a diameter of 12.5 cm, and p conductivity type. Then, the element isolation insulating film 4 was formed. Subsequently, a silicon thermal oxide film having a thickness of 8 nm is formed on the surface of the substrate 30 in the desired active region to form a buried insulating film 51, and buried electrodes 61 and 62 are formed by a stacked deposition film of a polycrystalline silicon film and a tungsten silicide film. .. In this state, the electrode protection insulating film 41 is deposited on the entire surface, then the polycrystalline silicon film 31 having a thickness of 5 μm is deposited, and the surface thereof is subjected to mechanical / chemical polishing so that the root mean square roughness becomes 0.3 nm. It was mirror-polished.

In the step shown in FIG. 3, the surface of the oxide film 2 of the second single crystal Si substrate 1 having a 200 nm thick silicon thermal oxide film 2 formed on a separately prepared main surface and the polycrystalline silicon of FIG. The surface of the membrane 31 was directly attached. The single crystal Si substrate 1 had the same specifications as the single crystal Si substrate 30.
In the direct bonding, if the bonding surface is extremely clean and the fine irregularities on the surface are flat at about 5 nm or less, the bonding can be performed uniformly without generating voids.

In the process shown in FIG. 4, heat treatment for improving the adhesive strength is performed at 1000 ° C. for 2 times as compared with the state shown in FIG.
It was given under the condition of time. After the above heat treatment, the adhesion strength was examined by a tensile test to find that it was about 800 kg / cm ² , and a fracture strength similar to that of Si single crystal was obtained. From this state, the single crystal Si substrate 30 is thinned from the back surface side (upper side of the drawing) by a high precision grinding machine to a thickness of about 10 μm, and then ethylenediamine pyrocateco-
Mechanical and chemical polishing was carried out using a polishing liquid to which silver was added. The above polishing is performed by using a polishing cloth provided on the rotating disk with Si.
The substrate was pressed at a pressure of 1.9 × 10 ⁴ Pa and the polishing liquid was supplied, but the polishing rate of the inter-element isolation insulating film 4 exposed as the polishing progressed was much slower than that of single crystal Si. Was less than 1/10 ⁴ times. Therefore, the single crystal Si substrate 30 was completely flattened by the above polishing, and became flush with the back surface of the element isolation insulating film 4. As a result, the single crystal semiconductor layer 3 which is an ultrathin film having a thickness of about 100 nm is separated from each other by the element isolation insulating film 4 corresponding to the active region.
2 and 33 were obtained.

FIG. 5 is a final step diagram and is a sectional view showing the structure of the first embodiment of the semiconductor integrated circuit device according to the present invention, and FIG. 6 is an equivalent circuit diagram thereof. In the state of FIG. 4, 8 nm is formed in the regions of the single crystal semiconductor layers 32 and 33 based on the conventionally known method of manufacturing a MOS transistor.
A thick gate oxide film 52, gate electrodes 63 and 64, source regions 71 and 72 of high-concentration impurity layers, drain regions 81 and 82, and metal electrodes 91, 92 and 93.
Formed. The embedded gate electrodes 61 and 62 are taken out before the gate electrodes 63 and 64 or the metal electrodes 91, 92 and 93 are formed, and the embedded gate electrodes 61 and 62 are extended below the element isolation insulating film 4. It was carried out by an opening (not shown) in the region where the region was formed.

In the semiconductor integrated circuit device manufactured by the above manufacturing method, the buried gate electrodes 61 and 62 are buried at the bottoms of the single crystal semiconductor layers 32 and 33 with the buried gate insulating film 51 interposed therebetween. The threshold voltage value of each of the transistors 1 and 2 is set to an independent value by setting the voltage applied to the embedded gate electrodes 61 and 62 to an arbitrary value. Further, the single crystal semiconductor layers 32 and 33 are extremely thin, 100 nm, and are fully depleted by the gate voltage applied to the gate electrodes 63 and 64 to obtain 1.8 times the transfer conductance of the normal structure transistor. It was possible to realize high current and high speed operation. Further, no interference was observed between the two transistors 1 and 2, and it was confirmed that the latch-up phenomenon did not occur.

Second Embodiment FIG. 7 is a circuit configuration diagram showing a second embodiment of the semiconductor integrated circuit device according to the present invention. In this embodiment, a semiconductor integrated circuit device including a complementary transistor inverter is used.
It is manufactured according to the manufacturing method described in. The single crystal semiconductor layers (for example, 33 in FIG. 4) of the transistors (abbreviated as Tr) 1 and Tr2 are made n-conductivity type by ion implantation from the state of FIG. 4 by boron ion implantation and subsequent activation heat treatment. .. In addition, the source region in the single crystal semiconductor layer in FIG. 5 (for example, 72 in FIG. 5, 10 in FIG. 7).
3 and 109) and the drain region (eg 82 in FIG. 5,
In FIG. 7, 102 and 108) are p-type high-concentration impurity layers formed by the ion implantation method, and other manufacturing steps are based on the first embodiment. In the semiconductor integrated circuit device according to the present embodiment, Tr
The embedded gate electrodes of 1 and Tr3 are connected to the wiring 150 to which a positive constant voltage is applied at 105 and 111, respectively, and the embedded gate electrodes of Tr2 and Tr4 are at 106 and 112, respectively, with respect to the source potential. Is connected to the wiring 250 to which a negative potential is applied. The wiring 100 is a power supply voltage line,
Wiring 200 is a ground potential line, 101 is an input, 102 and 10
7 is a connection line between the inverters in the next stage, and 108 is an output line. In the semiconductor integrated circuit device according to this embodiment, a normal inverter operation can be realized by applying a voltage of desired polarity to the buried gate electrode for each of the p-channel and n-channel transistors. Further, the delay time can be reduced by about 30% as compared with the conventional device due to the effect of the high speed operation characteristic of the basic transistor.

Third Embodiment FIG. 8 is a circuit configuration diagram showing a third embodiment of the semiconductor integrated circuit device according to the present invention. In this embodiment, a semiconductor integrated circuit device including n-channel transistor groups having different threshold voltage values and including a reference voltage generating circuit was manufactured according to the first embodiment. Constant current supply transistor T
The embedded gate electrodes of r5 and the source-following transistors Tr7 and Tr8 are connected to the wiring 180 to which a negative low potential is applied at 117, 123 and 124, respectively, and Tr6 is connected to the wiring 250 to which a negative high potential is applied. did. The wiring 100 was connected to the power supply voltage line, the wiring 200 was connected to the ground potential line, and the output 120 was connected to one end of the differential amplifier. With the above configuration, Tr
5, Tr7 and Tr8 operated as a depletion type transistor, and Tr6 operated as an enhanced type transistor, and a stable reference potential corresponding to the threshold voltage difference could be generated at the output 120.

Fourth Embodiment FIG. 9 is a cross sectional view showing a fourth embodiment of the semiconductor integrated circuit device according to the present invention. FIG. 10 is an equivalent circuit diagram of the semiconductor integrated circuit device of FIG. In this embodiment, a semiconductor integrated circuit device including a write / read (RAM) memory device is manufactured according to the first embodiment. In the manufacturing process of FIG. 2, with the element isolation insulating film 4 in the central portion not provided,
After the electrode protective insulating film 41 is deposited, the electrode protective insulating film 41 in the desired region is selectively opened, and the capacitive element electrode 75 and the capacitor element electrode 75 are formed by the deposition and patterning of the low resistance polycrystalline Si film to which impurities are added. 751 was formed. Then, the capacitor element electrode 7
A thin insulating film 53 having a thickness of 6 nm was formed on the surface of No. 5, and then a low-resistance silicon film 34 having a thickness of 5 μm and serving as a plate electrode was deposited. Thereafter, the semiconductor integrated circuit device of this example was manufactured according to the manufacturing process of Example 1. In this embodiment, the gate insulating film 52 is provided on the single crystal semiconductor layer 73, and the gate electrode 65 serving as a word line.
After forming 651 and 651, a wiring interlayer insulating film 42 was deposited and a hole was formed at a desired position to form a bit line 94 of metal wiring. In the semiconductor integrated circuit device manufactured through the above manufacturing process, each transistor can be made an enhanced type by setting the embedded electrodes 66 and 661 to a negative potential. As a result, it has been possible to realize a semiconductor integrated circuit device including a semiconductor memory device that is extremely fast and is resistant to soft errors by taking advantage of the features of the ultrathin film transistor.

Embodiment 5 FIG. 11 is a circuit configuration diagram showing a fifth embodiment of a semiconductor integrated circuit device according to the present invention. In this embodiment, a semiconductor integrated circuit device including a static memory device having a flip-flop circuit as one unit of a memory circuit is manufactured according to the second embodiment. Tr forming a flip-flop circuit
Of the transistors from 9 to Tr12, Tr9 and Tr
11 is a p-channel type, and Tr10 and Tr12 are n-channel types. Switch transistors Tr13 and Tr1
4 is also an n-channel type. Each embedded gate electrode of the n-channel transistor was connected at 106 and 112 to the wiring 250 to which a negative potential with respect to the source potential was applied.
The buried gate electrode of the p-channel transistor was connected at 105 and 111 to the wiring 150 to which a positive constant voltage was applied. The wiring 200 is a ground potential line, the wiring 100 is a power supply voltage line, and 126 and 127 are data lines. In the semiconductor integrated circuit device according to this embodiment, a normal memory operation can be realized by applying a voltage of desired polarity to the buried gate electrode for each of p-channel and n-channel transistors. This makes it possible to take advantage of the characteristics of the ultra-thin film transistor and achieve 1.3 times faster speed and soft error than conventional devices.
It has been possible to realize a semiconductor integrated circuit device including a semiconductor memory device that is resistant to aging.

Embodiment 6 FIG. 12 is an example in which the semiconductor integrated circuit device according to the present invention is applied to a high-speed large-scale computer in which a plurality of processors 500 for processing instructions and operations are connected in parallel. Example 6
Since the high-speed semiconductor integrated circuit device according to the present invention has a high degree of integration, a processor 500 for processing instructions and operations,
The storage control device 501, the main storage device 502, and the like can be configured by a silicon semiconductor chip having a side of about 10 to 30 mm. Data communication interface 5 including processor 500, storage controller 501, and compound semiconductor integrated circuit
03 was mounted on the same ceramic substrate 506. Also,
The data communication interface 503 and the data communication control device 504 are mounted on the same ceramic substrate 507. These ceramic substrates 506 and 507 and the ceramic substrate on which the main memory device 502 is mounted have a size of about 5 per side.
A central processing unit 508 of a large-scale computer was formed by mounting on a substrate having a size of 0 cm or less. The data communication in the central processing unit 508, the data communication between a plurality of central processing units, or the board 509 on which the data communication interface 503 and the input / output processor 505 are mounted.
The communication of data between and was carried out via an optical fiber 510 indicated by a double-ended arrow line in the figure. In this computer, a processor 500 that processes instructions and operations, a silicon semiconductor integrated circuit such as a storage control device 501 and a main storage device 502 operate in parallel at high speed, and data communication is performed using light as a medium. Therefore, the number of instruction processings per second could be significantly increased.

[0020]

According to the present invention, the substrate impurity concentration, the gate material, and the gate material for the SOI transistor which can operate at an ultra-high speed as compared with the conventional transistor and is resistant to the soft error and the latch-up failure. The threshold voltage value can be independently controlled for each transistor or each transistor group regardless of the insulating film thickness. As a result, various circuit devices can be realized by a semiconductor integrated circuit device including an SOI transistor, and a semiconductor integrated circuit device having an ultrahigh speed and high reliability can be provided.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of an SOI transistor which is a conventional semiconductor integrated circuit device.

FIG. 2 is a cross-sectional view showing the manufacturing process of the first embodiment of the semiconductor integrated circuit device according to the present invention.

FIG. 3 is a cross-sectional view showing the manufacturing process of Embodiment 1 of the semiconductor integrated circuit device according to the present invention.

FIG. 4 is a cross-sectional view showing the manufacturing process of Embodiment 1 of the semiconductor integrated circuit device according to the present invention.

FIG. 5 is a cross-sectional view showing the manufacturing process of Embodiment 1 of the semiconductor integrated circuit device according to the present invention.

FIG. 6 is a diagram showing an equivalent circuit of Example 1 of the semiconductor integrated circuit device according to the present invention.

FIG. 7 is a diagram showing an equivalent circuit of a second embodiment of the semiconductor integrated circuit device according to the present invention.

FIG. 8 is a diagram showing an equivalent circuit of a third embodiment of the semiconductor integrated circuit device according to the present invention.

FIG. 9 is a sectional view showing a configuration of a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

FIG. 10 is a fourth embodiment of the semiconductor integrated circuit device according to the present invention.
It is a figure which shows the equivalent circuit of.

FIG. 11 is a fifth embodiment of the semiconductor integrated circuit device according to the present invention.
It is a figure which shows the equivalent circuit of.

FIG. 12 is a configuration diagram of a computer using the semiconductor integrated circuit device of the present invention.

[Explanation of symbols]

1: support substrate, 81, 82: drain region, 2: insulating film, 91, 92, 93: metal electrode,
3: semiconductor thin film, 94: bit line,
4: element isolation insulating film, 100: power supply voltage line, 5: gate insulating film, 101: input, 6: gate electrode, 102 and 1
08: p-type drain region, 7: source diffusion layer,
103 and 109: p-type source region, 8: drain diffusion layer, 120: output, 9: source electrode, 126 and 127: data line, 10: drain electrode, 150: positive voltage line, 30: Single crystal Si substrate, 180 and 250: Negative voltage line, 31: Polycrystalline silicon film, 200:
Ground potential line, 32 and 33: single crystal ultra thin film, 50
0: Processor for processing instructions and operations, 34: Low resistance silicon film, 501: Semiconductor integrated circuit (memory control device), 41: Electrode protection insulating film, 50
2: semiconductor integrated circuit (main memory device), 51: embedded gate insulating film, 503: data communication interface, 52: gate oxide film, 504: data communication control device, 53: thin insulating film,
505: Input / output processor, 61, 62, 66, 661: Embedded gate electrode, 506, 507: Ceramic substrate, 63, 64, 6
5, 651: Gate electrode, 508: Central processing unit, 71, 72: Source area, 509: Input / output processor mounting board, 75, 751: Capacitance element electrode
510: Optical fiber for data communication.

Claims (11)

[Claims] 1. A device in which a semiconductor integrated circuit including at least one MOS transistor is formed on an upper side of the insulating film of a support substrate on which a first insulating film is laminated, the active region of the MOS transistor being formed. A semiconductor integrated circuit device characterized in that a buried insulating film and a buried electrode provided on the buried insulating film are formed on the side of the single crystal semiconductor layer opposite to the gate oxide film side. 2. The semiconductor integrated circuit device according to claim 1, wherein an electrode protection insulating film and a polycrystalline silicon film are interposed between the buried insulating film and the buried electrode and the first insulating film. A semiconductor integrated circuit device characterized by the above. 3. The semiconductor integrated circuit device according to claim 1, wherein a plurality of the MOS transistors are provided,
A semiconductor integrated circuit device, wherein a circuit for selectively applying the same or different voltages is added to a plurality of embedded electrodes corresponding to the plurality of MOS transistors. 4. The semiconductor integrated circuit device according to claim 1 or 2, wherein a plurality of the MOS transistors are provided,
The single crystal semiconductor layers of the plurality of some of the MOS transistors are of the first conductivity type, and the other part of the plurality of MO transistors of the plurality of MO transistors are
The single crystal semiconductor layer of the S transistor is of the second conductivity type, the embedded electrode provided in the first conductivity type MOS transistor is fixed at a first constant potential, and the second conductivity type MOS transistor is fixed. A semiconductor integrated circuit device, wherein the embedded electrode provided in the transistor is fixed to a second constant potential. 5. The semiconductor integrated circuit device according to claim 1, wherein there are a plurality of the MOS transistors, and a part of the plurality of MOS transistors is a single crystal semiconductor layer of the same conductivity type, and A semiconductor integrated circuit device characterized in that a fixed voltage applied to an embedded electrode is different. 6. The semiconductor integrated circuit device according to claim 1 or 2, wherein a plurality of the MOS transistors are provided,
A capacitive element is formed in a part of the single crystal semiconductor layer forming the active layer of the MOS transistor on the embedded electrode side, and the semiconductor element is configured such that each of the MOS transistors is a unit of a memory element. A semiconductor integrated circuit device characterized in that. 7. The semiconductor integrated circuit device according to claim 1, wherein the MOS transistor is plural, and at least a part of the MOS transistor forms a complementary MOS inverter circuit. .. 8. The semiconductor integrated circuit device according to claim 1, wherein the MOS transistor is plural, and at least a part of the MOS transistor constitutes a flip-flop circuit. 9. An electronic computer comprising at least a part of the semiconductor integrated circuit device according to claim 1. Description: 10. A gate insulating film embedded in a single crystal substrate,
A step of forming a first semiconductor substrate in which a buried gate electrode, a wiring protective film and a polycrystalline semiconductor layer are sequentially laminated, and a step of forming a second semiconductor substrate in which an insulating film is formed on the main surface of the polycrystalline semiconductor layer. And a step of making a multilayer structure semiconductor substrate in which the surface of the single crystal substrate of the first semiconductor substrate and the surface of the polycrystalline semiconductor layer of the second semiconductor substrate are bonded together, Polishing a single crystal substrate of a semiconductor substrate, MOS
A method of manufacturing a semiconductor integrated circuit device, comprising: a step of forming a single crystal semiconductor layer of a transistor; and a step of forming a MOS transistor on the formed single crystal semiconductor layer. 11. A first semiconductor substrate and a first semiconductor substrate in which an element isolation insulating film, a buried gate insulating film, a buried gate electrode, a wiring protective film and a polycrystalline semiconductor layer are formed on a single crystal substrate. And a step of forming a second semiconductor substrate having an oxide film formed on the main surface thereof, and a surface of the single crystal substrate of the first semiconductor substrate and a surface of the polycrystalline semiconductor layer of the second semiconductor substrate. The step of making a laminated multi-layered semiconductor substrate, thinning from the back surface side of the first semiconductor substrate of the above-mentioned multi-layered semiconductor substrate by grinding and polishing, and the first surface up to the surface defined by the back surface of the element isolation insulating film A step of forming a main surface of the multilayer structure semiconductor substrate by selectively polishing the semiconductor substrate; and a step of forming a MOS type transistor on the single crystal semiconductor layer separated by the element isolation insulating film by the selective polishing. Semiconductor integrated circuit including Device manufacturing method.