JPH0521703A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0521703A JPH0521703A JP3170885A JP17088591A JPH0521703A JP H0521703 A JPH0521703 A JP H0521703A JP 3170885 A JP3170885 A JP 3170885A JP 17088591 A JP17088591 A JP 17088591A JP H0521703 A JPH0521703 A JP H0521703A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chips
- semiconductor
- device hole
- leads
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 239000011347 resin Substances 0.000 claims abstract description 6
- 229920005989 resin Polymers 0.000 claims abstract description 6
- 239000003566 sealing material Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 abstract description 13
- 238000009413 insulation Methods 0.000 abstract 1
- 238000004806 packaging method and process Methods 0.000 abstract 1
- 238000009616 inductively coupled plasma Methods 0.000 description 11
- 235000010384 tocopherol Nutrition 0.000 description 11
- 235000019731 tricalcium phosphate Nutrition 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000013256 coordination polymer Substances 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に係り、特
には表面実装型のテープキャリアパッケージ(以下、Ｔ
ＣＰという)の構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a surface mount type tape carrier package (hereinafter referred to as T
CP).
【０００２】[0002]
【従来の技術】一般に、半導体装置としてのＴＣＰは、
テープ基材上に予め形成されたインナーリードに対して
半導体チップをバンプを用いて接合した後、この半導体
チップを樹脂封止し、次に、テープ基材に形成されたア
ウタリードを打ち抜き等により切り離すことにより製作
される。2. Description of the Related Art Generally, a TCP as a semiconductor device is
After bonding the semiconductor chip to the inner lead previously formed on the tape base material by using bumps, this semiconductor chip is resin-sealed, and then the outer lead formed on the tape base material is separated by punching or the like. It is produced by
【０００３】図７は、このような一つのＴＣＰをプリン
ト基板に実装した状態を示す断面図である。FIG. 7 is a sectional view showing a state in which one such TCP is mounted on a printed circuit board.
【０００４】同図において、aはＴＣＰ、bはプリント基
板、cは半導体チップ、dは封止樹脂、eはバンプ、fはイ
ンナリード、gはテープ基材、hはアウタリード、iはプ
リント基板b上に形成された金属配線層、jはアウタリー
ドhを金属配線層iに接合するための半田である。In the figure, a is TCP, b is a printed circuit board, c is a semiconductor chip, d is a sealing resin, e is a bump, f is an inner lead, g is a tape base material, h is an outer lead, and i is a printed circuit board. The metal wiring layer formed on b is a solder for joining the outer lead h to the metal wiring layer i.
【０００５】[0005]
【発明が解決しようとする課題】ところで、多数の回路
素子を組み合わて一つのデバイスを構成するために、図
８に示すように、一つのプリント基板b上に回路素子と
しての各ＴＣＰaをそれぞれ異なる位置に平面的に配置
する場合には、実装面積が多くなり、小型化が困難であ
る。By the way, in order to combine a large number of circuit elements into one device, as shown in FIG. 8, each TCPa as a circuit element is different on one printed board b. In the case of arranging it in a plane in a position, the mounting area becomes large and it is difficult to reduce the size.
【０００６】その対策として、たとえば、図９に示すよ
うに、各ＴＣＰaをプリント基板bの同一箇所に積み重ね
ることが考えられる。As a countermeasure, for example, as shown in FIG. 9, it is conceivable to stack each TCPa at the same position on the printed circuit board b.
【０００７】しかしながら、この場合は、前者の場合に
比較すると実装面積は少なくてすむものの、ＴＣＰaの
数が多くなればなるほど、全体として嵩が高くなり、表
面実装型としてのＴＣＰの利点が損なわれる。However, in this case, although the mounting area is smaller than that in the former case, the larger the number of TCPa, the higher the bulk as a whole, and the advantage of TCP as a surface mounting type is impaired. .
【０００８】[0008]
【課題を解決するための手段】本発明は、上述した課題
を解決するためになされたもので、従来よりも一層実装
密度の高いＴＣＰ方式の半導体装置が得られるようにす
るものである。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object thereof is to provide a TCP type semiconductor device having a higher packing density than ever before.
【０００９】そのため、本発明の半導体装置では、テー
プ基材にはデバイスホールが形成され、このデバイスホ
ールの位置に複数の半導体チップが絶縁層を介して順次
積層され、かつ、前記テープ基材上に形成されたリード
がデバイスホール上にインナリードとして延設されて前
記各半導体チップに個別に接続され、前記半導体チッ
プ、デバイスホール、およびインナリードがいずれも樹
脂等の封止材料で封止されて１つのＴＣＰとして構成さ
れるようにした。Therefore, in the semiconductor device of the present invention, a device hole is formed in the tape base material, and a plurality of semiconductor chips are sequentially stacked at the position of the device hole via an insulating layer, and the tape base material is formed. The leads formed on the device holes are extended as inner leads on the device holes and individually connected to the respective semiconductor chips, and the semiconductor chips, the device holes, and the inner leads are all sealed with a sealing material such as resin. Configured as one TCP.
【００１０】[0010]
【作用】上記構成によれば、複数の半導体チップを積層
し、各半導体チップがインナリードに接合された後、全
体を封止して一つのＴＣＰとしているため、これをプリ
ント基板等に実装する際には、従来のように、多数のＴ
ＣＰをプリント基板に平面的に並べる場合よりも実装面
積は少なくてすみ、また、従来のように、完成された個
々のＴＣＰを積層する場合よりも全体を薄肉にすること
ができる。According to the above construction, since a plurality of semiconductor chips are laminated and each semiconductor chip is bonded to the inner lead and then the whole is sealed to form one TCP, this is mounted on a printed circuit board or the like. At that time, as in the past, many T
The mounting area is smaller than that in the case where the CPs are arranged in a plane on the printed board, and the whole can be made thinner than in the case where the completed individual TCPs are stacked as in the conventional case.
【００１１】[0011]
【実施例】図１は本発明の実施例に係る半導体装置の平
面図、図２は図１のＡ−Ａ線に沿う断面図、図３は図１
のＢ−Ｂ線に沿う断面図である。1 is a plan view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view taken along the line A--A of FIG. 1, and FIG.
It is sectional drawing which follows the BB line.
【００１２】これらの図において、符号１はＴＣＰ方式
の半導体装置の全体を示し、２はポリイミドテープなど
でできたテープ基材、４はテープ基材２を上下に貫通し
て形成された方形のデバイスホール、６，６はこのデバ
イスホール４の位置において互いに直交して積層配置さ
れた複数(本例では２つ)の半導体チップである。In these figures, reference numeral 1 denotes the whole of a TCP type semiconductor device, 2 denotes a tape base material made of a polyimide tape or the like, and 4 denotes a square formed by vertically penetrating the tape base material 2. The device holes 6 and 6 are a plurality (two in this example) of semiconductor chips that are laminated and arranged orthogonally to each other at the position of the device hole 4.
【００１３】図中、下側の半導体チップ６は上面に、上
側の半導体チップ６には下面にそれぞれ回路パターンが
形成されており、したがって、本例では、両半導体チッ
プ６，６は、回路パターンの形成面(表面)同士が対面し
ている。この場合、各半導体チップ６，６の回路パター
ンの形成面上には、回路パターンの損傷を防止するた
め、予めポリイミド樹脂等の保護膜(図示省略)が薄く均
一に塗布されており、したがって、両半導体チップ６，
６はこの保護膜が絶縁層として作用するため、互いの回
路パターン同士が短絡することはない。In the figure, a circuit pattern is formed on the upper surface of the lower semiconductor chip 6 and on the lower surface of the upper semiconductor chip 6, respectively. Therefore, in the present example, both semiconductor chips 6 and 6 have circuit patterns. The formation surfaces (surfaces) of are facing each other. In this case, a protective film (not shown) such as a polyimide resin is thinly and evenly applied in advance on the formation surface of the circuit pattern of each of the semiconductor chips 6 and 6 in order to prevent damage to the circuit pattern. Both semiconductor chips 6,
In No. 6, since the protective film acts as an insulating layer, the circuit patterns of each other are not short-circuited.
【００１４】一方、テープ基材２上には予めデバイスホ
ール４の各辺にＣu箔等からなるリード８が形成されて
おり、これらの各リード８はデバイスホール４上にイン
ナリード８aとして延設されて各半導体チップ６，６の
バンプ１０を介して個別に接続されている。そして、各
半導体チップ６，６、デバイスホール４、およびインナ
リード８aを含むかたちでいずれも樹脂等の封止材料１
２で封止されている。On the other hand, leads 8 made of Cu foil or the like are formed in advance on each side of the device hole 4 on the tape base material 2, and these leads 8 extend on the device hole 4 as inner leads 8a. The semiconductor chips 6 and 6 are individually connected via the bumps 10. Each of the semiconductor chips 6 and 6, the device hole 4, and the inner lead 8a includes a sealing material 1 such as a resin.
It is sealed with 2.
【００１５】なお、図示省略しているが、各リード８の
他端は、テープ基材２よりも外方に延設されてアウタリ
ードとしてプリント基板等に接続できるようにフォーミ
ング加工されている。Although not shown, the other end of each lead 8 is formed outside the tape substrate 2 so that it can be connected as an outer lead to a printed circuit board or the like.
【００１６】したがって、この半導体装置１を製作する
には、各半導体チップ６，６を重ね合せた後、各バンプ
８にインナリード８を接合し、次に、これらの各半導体
チップ６，６、デバイスホール４、およびインナリード
８aをいずれも樹脂等の封止材料１２で封止し、アウタ
リードが切断されてＴＣＰとなる。Therefore, in order to manufacture the semiconductor device 1, the semiconductor chips 6 and 6 are superposed on each other, the inner leads 8 are joined to the bumps 8, and then the semiconductor chips 6 and 6, respectively. Both the device hole 4 and the inner lead 8a are sealed with a sealing material 12 such as a resin, and the outer lead is cut to form a TCP.
【００１７】なお、各半導体チップ６，６の重ね合せの
都合上、図４に示すように、半導体チップ６，６の回路
パターンの非形成面(裏面)どうしが互いに対面するよう
に積層される場合には、そのままでは短絡の恐れがある
ので、両半導体チップ６，６の間に必ず絶縁層１４を介
在させる必要がある。For the convenience of stacking the semiconductor chips 6 and 6, as shown in FIG. 4, the semiconductor chips 6 and 6 are stacked so that the surfaces (back surfaces) where the circuit patterns are not formed face each other. In this case, the insulating layer 14 must be interposed between the semiconductor chips 6 and 6 because there is a risk of a short circuit if left as it is.
【００１８】また、上記の実施例では、２つの半導体チ
ップ６，６が互いに直交配置される場合を示したが、こ
れに限定されるものではなく、各半導体チップ６，６に
接続されるリード８が互いに重ならない配線パターンを
テープ基材２上に形成することができれば、たとえば、
図５に示すような接合の仕方であってもよい。さらに、
半導体チップの数も２個に限らず、図６に示すように多
数の半導体チップ６を積層することも可能である。Further, in the above embodiment, the case where the two semiconductor chips 6 and 6 are arranged orthogonal to each other has been shown, but the present invention is not limited to this, and the leads connected to the respective semiconductor chips 6 and 6 are provided. If a wiring pattern in which 8 does not overlap each other can be formed on the tape base material 2, for example,
The joining method as shown in FIG. 5 may be used. further,
The number of semiconductor chips is not limited to two, and a large number of semiconductor chips 6 can be stacked as shown in FIG.
【００１９】[0019]
【発明の効果】本発明によれば、複数の半導体チップを
積層し、各半導体チップがインナリードに接合された
後、全体を封止して一つのＴＣＰとしているため、高密
度実装でかつ比較的薄肉の半導体装置が得られるように
なる。According to the present invention, a plurality of semiconductor chips are stacked, and after each semiconductor chip is bonded to the inner lead, the whole is sealed to form one TCP. A thin semiconductor device can be obtained.
【図１】本発明の実施例に係る半導体装置の平面図であ
る。FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention.
【図２】図１のＡ−Ａ線に沿う断面図である。FIG. 2 is a sectional view taken along the line AA of FIG.
【図３】図１のＢ−Ｂ線に沿う断面図である。FIG. 3 is a sectional view taken along line BB of FIG.
【図４】本発明の他の実施例に係る半導体装置の断面図
である。FIG. 4 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.
【図５】本発明の他の実施例に係る半導体装置の平面図
である。FIG. 5 is a plan view of a semiconductor device according to another embodiment of the present invention.
【図６】本発明の他の実施例に係る半導体装置の平面図
である。FIG. 6 is a plan view of a semiconductor device according to another embodiment of the present invention.
【図７】従来の半導体装置をプリント基板に実装した状
態を示す断面図である。FIG. 7 is a cross-sectional view showing a state in which a conventional semiconductor device is mounted on a printed board.
【図８】従来技術として、一つのプリント基板に多数の
半導体装置を散在的に実装した状態を示す斜視図であ
る。FIG. 8 is a perspective view showing a state in which a large number of semiconductor devices are scatteredly mounted on one printed circuit board as a conventional technique.
【図９】従来技術として、一つのプリント基板に多数の
半導体装置を積層した状態を示す断面図である。FIG. 9 is a cross-sectional view showing a state in which a large number of semiconductor devices are stacked on one printed circuit board as a conventional technique.
１…半導体装置、２…テープ基材、４…デバイスホー
ル、６…半導体チップ、８…リード、８a…インナリー
ド、１２…封止材料、１４…絶縁層。DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Tape base material, 4 ... Device hole, 6 ... Semiconductor chip, 8 ... Lead, 8a ... Inner lead, 12 ... Sealing material, 14 ... Insulating layer.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 23/28 Ｅ 8617−4Ｍ Ｔ 8617−4Ｍ 23/29 23/31 23/50 Ｓ 9272−4Ｍ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification number Office reference number FI technical display location H01L 23/28 E 8617-4M T 8617-4M 23/29 23/31 23/50 S 9272-4M
Claims (1)
れ、このデバイスホールの位置に複数の半導体チップが
絶縁層を介して順次積層され、かつ、前記テープ基材上
に形成されたリードがデバイスホール上にインナリード
として延設されて前記各半導体チップに個別に接続さ
れ、前記各半導体チップ、デバイスホール、およびイン
ナリードがいずれも樹脂等の封止材で封止されて１つの
テープキャリアパッケージとして構成されていることを
特徴とする半導体装置。Claim: What is claimed is: 1. A tape substrate has a device hole formed therein, and a plurality of semiconductor chips are sequentially stacked at the position of the device hole with an insulating layer interposed therebetween. The formed leads are extended as inner leads on device holes and individually connected to each of the semiconductor chips, and each of the semiconductor chips, the device holes, and the inner leads are sealed with a sealing material such as resin. A semiconductor device characterized by being configured as a single tape carrier package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3170885A JPH0521703A (en) | 1991-07-11 | 1991-07-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3170885A JPH0521703A (en) | 1991-07-11 | 1991-07-11 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0521703A true JPH0521703A (en) | 1993-01-29 |
Family
ID=15913123
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3170885A Pending JPH0521703A (en) | 1991-07-11 | 1991-07-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0521703A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0531257U (en) * | 1991-09-30 | 1993-04-23 | 船井電機株式会社 | Semiconductor mounting structure |
| US5501003A (en) * | 1993-12-15 | 1996-03-26 | Bel Fuse Inc. | Method of assembling electronic packages for surface mount applications |
| US6664618B2 (en) | 2001-05-16 | 2003-12-16 | Oki Electric Industry Co., Ltd. | Tape carrier package having stacked semiconductor elements, and short and long leads |
| US6737736B2 (en) | 2001-02-08 | 2004-05-18 | Renesas Technology Corp. | Semiconductor device |
| KR100497974B1 (en) * | 2001-06-13 | 2005-07-01 | 마쯔시다덴기산교 가부시키가이샤 | Semiconductor device and manufacturing method thereof |
-
1991
- 1991-07-11 JP JP3170885A patent/JPH0521703A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0531257U (en) * | 1991-09-30 | 1993-04-23 | 船井電機株式会社 | Semiconductor mounting structure |
| US5501003A (en) * | 1993-12-15 | 1996-03-26 | Bel Fuse Inc. | Method of assembling electronic packages for surface mount applications |
| US6737736B2 (en) | 2001-02-08 | 2004-05-18 | Renesas Technology Corp. | Semiconductor device |
| US6965154B2 (en) | 2001-02-08 | 2005-11-15 | Renesas Technology Corp. | Semiconductor device |
| DE10142585B4 (en) * | 2001-02-08 | 2007-08-09 | Mitsubishi Denki K.K. | Semiconductor arrangement and associated method for its production |
| US6664618B2 (en) | 2001-05-16 | 2003-12-16 | Oki Electric Industry Co., Ltd. | Tape carrier package having stacked semiconductor elements, and short and long leads |
| KR100497974B1 (en) * | 2001-06-13 | 2005-07-01 | 마쯔시다덴기산교 가부시키가이샤 | Semiconductor device and manufacturing method thereof |
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